Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 3 | # Enable deep Sx states |
Duncan Laurie | 1fe32d6 | 2017-04-10 21:02:13 -0700 | [diff] [blame] | 4 | register "deep_s5_enable_ac" = "1" |
| 5 | register "deep_s5_enable_dc" = "1" |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 6 | register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" |
| 7 | |
| 8 | # GPE configuration |
| 9 | # Note that GPE events called out in ASL code rely on this |
| 10 | # route. i.e. If this route changes then the affected GPE |
| 11 | # offset bits also need to be changed. |
Duncan Laurie | d6a42f9 | 2015-09-08 16:28:21 -0700 | [diff] [blame] | 12 | register "gpe0_dw0" = "GPP_B" |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 13 | register "gpe0_dw1" = "GPP_D" |
| 14 | register "gpe0_dw2" = "GPP_E" |
| 15 | |
Subrata Banik | 89f6d60 | 2016-07-26 15:37:11 +0530 | [diff] [blame] | 16 | # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 17 | register "gen1_dec" = "0x00fc0801" |
Subrata Banik | 89f6d60 | 2016-07-26 15:37:11 +0530 | [diff] [blame] | 18 | register "gen2_dec" = "0x000c0201" |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 19 | |
Duncan Laurie | 74b964e | 2015-09-04 10:41:02 -0700 | [diff] [blame] | 20 | # Enable DPTF |
| 21 | register "dptf_enable" = "1" |
| 22 | |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 23 | # FSP Configuration |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 24 | register "DspEnable" = "1" |
| 25 | register "IoBufferOwnership" = "3" |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 26 | register "ScsEmmcHs400Enabled" = "1" |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 27 | register "SkipExtGfxScan" = "1" |
Praveen Hodagatta Pranesh | aa6a8fb | 2019-10-29 14:47:11 +0800 | [diff] [blame] | 28 | register "SaGv" = "SaGv_Enabled" |
Rizwan Qureshi | fb87998 | 2015-11-19 16:06:28 +0530 | [diff] [blame] | 29 | |
| 30 | # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch |
| 31 | # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s |
| 32 | register "PmConfigSlpS3MinAssert" = "0x02" |
| 33 | |
| 34 | # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s |
| 35 | register "PmConfigSlpS4MinAssert" = "0x04" |
| 36 | |
| 37 | # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s |
| 38 | register "PmConfigSlpSusMinAssert" = "0x03" |
| 39 | |
| 40 | # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s |
| 41 | register "PmConfigSlpAMinAssert" = "0x03" |
| 42 | |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 43 | |
Michael Niewöhner | dd32103 | 2019-10-09 21:02:36 +0200 | [diff] [blame] | 44 | # VR Settings Configuration for 4 Domains |
| 45 | #+----------------+-----------+-----------+-------------+----------+ |
| 46 | #| Domain/Setting | SA | IA | GT Unsliced | GT | |
| 47 | #+----------------+-----------+-----------+-------------+----------+ |
| 48 | #| Psi1Threshold | 20A | 20A | 20A | 20A | |
| 49 | #| Psi2Threshold | 4A | 5A | 5A | 5A | |
| 50 | #| Psi3Threshold | 1A | 1A | 1A | 1A | |
| 51 | #| Psi3Enable | 1 | 1 | 1 | 1 | |
| 52 | #| Psi4Enable | 1 | 1 | 1 | 1 | |
| 53 | #| ImonSlope | 0 | 0 | 0 | 0 | |
| 54 | #| ImonOffset | 0 | 0 | 0 | 0 | |
| 55 | #| IccMax | 7A | 34A | 35A | 35A | |
| 56 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | |
| 57 | #+----------------+-----------+-----------+-------------+----------+ |
Rizwan Qureshi | 3fc4277 | 2015-11-20 11:47:40 +0530 | [diff] [blame] | 58 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
Michael Niewöhner | dd32103 | 2019-10-09 21:02:36 +0200 | [diff] [blame] | 59 | .vr_config_enable = 1, |
| 60 | .psi1threshold = VR_CFG_AMP(20), |
| 61 | .psi2threshold = VR_CFG_AMP(4), |
| 62 | .psi3threshold = VR_CFG_AMP(1), |
| 63 | .psi3enable = 1, |
| 64 | .psi4enable = 1, |
| 65 | .imon_slope = 0x0, |
| 66 | .imon_offset = 0x0, |
| 67 | .icc_max = VR_CFG_AMP(7), |
| 68 | .voltage_limit = 1520, |
Rizwan Qureshi | 3fc4277 | 2015-11-20 11:47:40 +0530 | [diff] [blame] | 69 | }" |
| 70 | |
| 71 | register "domain_vr_config[VR_IA_CORE]" = "{ |
Michael Niewöhner | dd32103 | 2019-10-09 21:02:36 +0200 | [diff] [blame] | 72 | .vr_config_enable = 1, |
| 73 | .psi1threshold = VR_CFG_AMP(20), |
| 74 | .psi2threshold = VR_CFG_AMP(5), |
| 75 | .psi3threshold = VR_CFG_AMP(1), |
| 76 | .psi3enable = 1, |
| 77 | .psi4enable = 1, |
| 78 | .imon_slope = 0x0, |
| 79 | .imon_offset = 0x0, |
| 80 | .icc_max = VR_CFG_AMP(34), |
| 81 | .voltage_limit = 1520, |
Rizwan Qureshi | 3fc4277 | 2015-11-20 11:47:40 +0530 | [diff] [blame] | 82 | }" |
| 83 | |
| 84 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
Michael Niewöhner | dd32103 | 2019-10-09 21:02:36 +0200 | [diff] [blame] | 85 | .vr_config_enable = 1, |
| 86 | .psi1threshold = VR_CFG_AMP(20), |
| 87 | .psi2threshold = VR_CFG_AMP(5), |
| 88 | .psi3threshold = VR_CFG_AMP(1), |
| 89 | .psi3enable = 1, |
| 90 | .psi4enable = 1, |
| 91 | .imon_slope = 0x0, |
| 92 | .imon_offset = 0x0, |
| 93 | .icc_max = VR_CFG_AMP(35), |
| 94 | .voltage_limit = 1520, |
Rizwan Qureshi | 3fc4277 | 2015-11-20 11:47:40 +0530 | [diff] [blame] | 95 | }" |
| 96 | |
| 97 | register "domain_vr_config[VR_GT_SLICED]" = "{ |
Michael Niewöhner | dd32103 | 2019-10-09 21:02:36 +0200 | [diff] [blame] | 98 | .vr_config_enable = 1, |
| 99 | .psi1threshold = VR_CFG_AMP(20), |
| 100 | .psi2threshold = VR_CFG_AMP(5), |
| 101 | .psi3threshold = VR_CFG_AMP(1), |
| 102 | .psi3enable = 1, |
| 103 | .psi4enable = 1, |
| 104 | .imon_slope = 0x0, |
| 105 | .imon_offset = 0x0, |
| 106 | .icc_max = VR_CFG_AMP(35), |
| 107 | .voltage_limit = 1520, |
Rizwan Qureshi | 3fc4277 | 2015-11-20 11:47:40 +0530 | [diff] [blame] | 108 | }" |
| 109 | |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 110 | # Enable Root port 1 and 5. |
| 111 | register "PcieRpEnable[0]" = "1" |
| 112 | register "PcieRpEnable[4]" = "1" |
| 113 | # Enable CLKREQ# |
| 114 | register "PcieRpClkReqSupport[0]" = "1" |
| 115 | register "PcieRpClkReqSupport[4]" = "1" |
| 116 | # RP 1 uses SRCCLKREQ1# while RP 5 uses SRCCLKREQ2# |
| 117 | register "PcieRpClkReqNumber[0]" = "1" |
| 118 | register "PcieRpClkReqNumber[4]" = "2" |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 119 | |
Subrata Banik | 2c3054c | 2016-11-22 20:21:49 +0530 | [diff] [blame] | 120 | register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-C Port 1 |
| 121 | register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # Type-C Port 2 |
| 122 | register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth |
| 123 | register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # Type-A Port (card) |
| 124 | register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera |
| 125 | register "usb2_ports[8]" = "USB2_PORT_LONG(OC3)" # Type-A Port (board) |
Duncan Laurie | 2b9595a | 2015-08-28 17:48:11 -0700 | [diff] [blame] | 126 | |
Subrata Banik | 2c3054c | 2016-11-22 20:21:49 +0530 | [diff] [blame] | 127 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 |
| 128 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 |
| 129 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port (card) |
| 130 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port (board) |
Duncan Laurie | c8d45ac | 2016-06-06 17:21:00 -0700 | [diff] [blame] | 131 | |
Aaron Durbin | ed14a4e | 2016-11-09 17:04:15 -0600 | [diff] [blame] | 132 | register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V |
Rizwan Qureshi | 9cd8e5a | 2015-10-05 19:13:01 +0530 | [diff] [blame] | 133 | |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 134 | # Must leave UART0 enabled or SD/eMMC will not work as PCI |
Felix Singer | 21b5a9a | 2023-10-23 07:26:28 +0200 | [diff] [blame^] | 135 | register "SerialIoDevMode" = "{ |
| 136 | [PchSerialIoIndexI2C0] = PchSerialIoPci, |
| 137 | [PchSerialIoIndexI2C1] = PchSerialIoPci, |
| 138 | [PchSerialIoIndexI2C2] = PchSerialIoDisabled, |
| 139 | [PchSerialIoIndexI2C3] = PchSerialIoDisabled, |
| 140 | [PchSerialIoIndexI2C4] = PchSerialIoPci, |
| 141 | [PchSerialIoIndexI2C5] = PchSerialIoDisabled, |
| 142 | [PchSerialIoIndexSpi0] = PchSerialIoDisabled, |
| 143 | [PchSerialIoIndexSpi1] = PchSerialIoDisabled, |
| 144 | [PchSerialIoIndexUart0] = PchSerialIoPci, |
| 145 | [PchSerialIoIndexUart1] = PchSerialIoDisabled, |
| 146 | [PchSerialIoIndexUart2] = PchSerialIoSkipInit, |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 147 | }" |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 148 | |
pchandri | f28929d | 2016-01-19 10:49:51 -0800 | [diff] [blame] | 149 | # PL2 override 25W |
Sumeet R Pawnikar | 97c5464 | 2020-05-10 01:24:11 +0530 | [diff] [blame] | 150 | register "power_limits_config" = "{ |
| 151 | .tdp_pl2_override = 25, |
| 152 | }" |
pchandri | f28929d | 2016-01-19 10:49:51 -0800 | [diff] [blame] | 153 | |
Subrata Banik | 9a8b67d | 2016-04-20 14:19:53 +0530 | [diff] [blame] | 154 | # Send an extra VR mailbox command for the PS4 exit issue |
| 155 | register "SendVrMbxCmd" = "2" |
| 156 | |
Duncan Laurie | 9482cf6 | 2016-06-22 11:31:51 -0700 | [diff] [blame] | 157 | # Use default SD card detect GPIO configuration |
Angel Pons | 6bd99f9 | 2021-02-20 00:16:47 +0100 | [diff] [blame] | 158 | register "sdcard_cd_gpio" = "GPP_A7" |
Duncan Laurie | 9482cf6 | 2016-06-22 11:31:51 -0700 | [diff] [blame] | 159 | |
Arthur Heymans | 69cd729 | 2022-11-07 13:52:11 +0100 | [diff] [blame] | 160 | device cpu_cluster 0 on end |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 161 | device domain 0 on |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 162 | device pci 00.0 on end # Host Bridge |
| 163 | device pci 02.0 on end # Integrated Graphics Device |
Felix Singer | 9c1c009 | 2020-07-29 20:48:08 +0200 | [diff] [blame] | 164 | device pci 04.0 on end # SA thermal subsystem |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 165 | device pci 14.0 on end # USB xHCI |
| 166 | device pci 14.1 off end # USB xDCI (OTG) |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 167 | device pci 14.2 on end # Thermal Subsystem |
Duncan Laurie | 9482cf6 | 2016-06-22 11:31:51 -0700 | [diff] [blame] | 168 | device pci 15.0 on |
| 169 | chip drivers/i2c/generic |
| 170 | register "hid" = ""ELAN0001"" |
| 171 | register "desc" = ""ELAN Touchscreen"" |
Furquan Shaikh | 5b9b593 | 2017-02-21 13:16:30 -0800 | [diff] [blame] | 172 | register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" |
Duncan Laurie | 9482cf6 | 2016-06-22 11:31:51 -0700 | [diff] [blame] | 173 | device i2c 10 on end |
| 174 | end |
| 175 | end # I2C #0 |
| 176 | device pci 15.1 on |
| 177 | chip drivers/i2c/generic |
| 178 | register "hid" = ""ELAN0000"" |
| 179 | register "desc" = ""ELAN Touchpad"" |
Furquan Shaikh | 5b9b593 | 2017-02-21 13:16:30 -0800 | [diff] [blame] | 180 | register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" |
Duncan Laurie | 9482cf6 | 2016-06-22 11:31:51 -0700 | [diff] [blame] | 181 | register "wake" = "GPE0_DW0_05" |
| 182 | device i2c 15 on end |
| 183 | end |
| 184 | end # I2C #1 |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 185 | device pci 15.2 off end # I2C #2 |
| 186 | device pci 15.3 off end # I2C #3 |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 187 | device pci 16.0 on end # Management Engine Interface 1 |
| 188 | device pci 16.1 off end # Management Engine Interface 2 |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 189 | device pci 16.2 off end # Management Engine IDE-R |
| 190 | device pci 16.3 off end # Management Engine KT Redirection |
| 191 | device pci 16.4 off end # Management Engine Interface 3 |
| 192 | device pci 17.0 off end # SATA |
| 193 | device pci 19.0 on end # UART #2 |
| 194 | device pci 19.1 off end # I2C #5 |
Duncan Laurie | 9482cf6 | 2016-06-22 11:31:51 -0700 | [diff] [blame] | 195 | device pci 19.2 on |
| 196 | chip drivers/i2c/nau8825 |
Furquan Shaikh | 5b9b593 | 2017-02-21 13:16:30 -0800 | [diff] [blame] | 197 | register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F10_IRQ)" |
Duncan Laurie | 9482cf6 | 2016-06-22 11:31:51 -0700 | [diff] [blame] | 198 | register "jkdet_enable" = "1" |
| 199 | register "jkdet_pull_enable" = "1" |
| 200 | register "jkdet_pull_up" = "1" |
| 201 | register "jkdet_polarity" = "1" # ActiveLow |
| 202 | register "vref_impedance" = "2" # 125kOhm |
| 203 | register "micbias_voltage" = "6" # 2.754 |
| 204 | register "sar_threshold_num" = "4" |
| 205 | register "sar_threshold[0]" = "0x08" |
| 206 | register "sar_threshold[1]" = "0x12" |
| 207 | register "sar_threshold[2]" = "0x26" |
| 208 | register "sar_threshold[3]" = "0x73" |
| 209 | register "sar_hysteresis" = "0" |
| 210 | register "sar_voltage" = "6" |
| 211 | register "sar_compare_time" = "1" # 1us |
| 212 | register "sar_sampling_time" = "1" # 4us |
| 213 | register "short_key_debounce" = "3" # 30ms |
| 214 | register "jack_insert_debounce" = "7" # 512ms |
| 215 | register "jack_eject_debounce" = "0" |
| 216 | device i2c 1a on end |
| 217 | end |
| 218 | chip drivers/i2c/generic |
| 219 | register "hid" = ""INT343B"" |
| 220 | register "desc" = ""SSM4567 Left Speaker Amp"" |
| 221 | register "uid" = "0" |
| 222 | register "device_present_gpio" = "GPP_E3" |
| 223 | device i2c 34 on end |
| 224 | end |
| 225 | chip drivers/i2c/generic |
| 226 | register "hid" = ""INT343B"" |
| 227 | register "desc" = ""SSM4567 Right Speaker Amp"" |
| 228 | register "uid" = "1" |
| 229 | register "device_present_gpio" = "GPP_E3" |
| 230 | device i2c 35 on end |
| 231 | end |
| 232 | end # I2C #4 |
| 233 | device pci 1c.0 on |
Furquan Shaikh | a266d1e | 2020-10-04 12:52:54 -0700 | [diff] [blame] | 234 | chip drivers/wifi/generic |
Duncan Laurie | 9482cf6 | 2016-06-22 11:31:51 -0700 | [diff] [blame] | 235 | register "wake" = "GPE0_DW0_16" |
| 236 | device pci 00.0 on end |
| 237 | end |
| 238 | end # PCI Express Port 1 |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 239 | device pci 1c.1 off end # PCI Express Port 2 |
| 240 | device pci 1c.2 off end # PCI Express Port 3 |
| 241 | device pci 1c.3 off end # PCI Express Port 4 |
Pratik Prajapati | f1acb9b | 2015-08-13 15:21:37 -0700 | [diff] [blame] | 242 | device pci 1c.4 on end # PCI Express Port 5 |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 243 | device pci 1c.5 off end # PCI Express Port 6 |
| 244 | device pci 1c.6 off end # PCI Express Port 7 |
| 245 | device pci 1c.7 off end # PCI Express Port 8 |
Pratik Prajapati | f1acb9b | 2015-08-13 15:21:37 -0700 | [diff] [blame] | 246 | device pci 1d.0 off end # PCI Express Port 9 |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 247 | device pci 1d.1 off end # PCI Express Port 10 |
| 248 | device pci 1d.2 off end # PCI Express Port 11 |
| 249 | device pci 1d.3 off end # PCI Express Port 12 |
| 250 | device pci 1e.0 on end # UART #0 |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 251 | device pci 1e.1 off end # UART #1 |
| 252 | device pci 1e.2 off end # GSPI #0 |
| 253 | device pci 1e.3 off end # GSPI #1 |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 254 | device pci 1e.4 on end # eMMC |
| 255 | device pci 1e.5 off end # SDIO |
| 256 | device pci 1e.6 on end # SDCard |
| 257 | device pci 1f.0 on |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 258 | chip drivers/pc80/tpm |
| 259 | device pnp 0c31.0 on end |
| 260 | end |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 261 | chip ec/google/chromeec |
| 262 | device pnp 0c09.0 on end |
| 263 | end |
| 264 | end # LPC Interface |
Archana Patni | 30f53cd | 2015-11-11 01:30:41 +0530 | [diff] [blame] | 265 | device pci 1f.1 on end # P2SB |
Naveen Krishna Chatradhi | 133dcd3 | 2015-07-10 16:00:51 +0530 | [diff] [blame] | 266 | device pci 1f.2 on end # Power Management Controller |
Duncan Laurie | 9482cf6 | 2016-06-22 11:31:51 -0700 | [diff] [blame] | 267 | device pci 1f.3 on |
| 268 | chip drivers/generic/max98357a |
Aamir Bohra | a1c82c5 | 2020-03-16 18:57:48 +0530 | [diff] [blame] | 269 | register "hid" = ""MX98357A"" |
Furquan Shaikh | 028200f | 2016-10-04 10:53:32 -0700 | [diff] [blame] | 270 | register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" |
Duncan Laurie | 9482cf6 | 2016-06-22 11:31:51 -0700 | [diff] [blame] | 271 | register "device_present_gpio" = "GPP_E3" |
| 272 | register "device_present_gpio_invert" = "1" |
| 273 | device generic 0 on end |
| 274 | end |
| 275 | end # Intel HDA |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 276 | device pci 1f.4 on end # SMBus |
| 277 | device pci 1f.5 on end # PCH SPI |
| 278 | device pci 1f.6 off end # GbE |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 279 | end |
| 280 | end |