commit 89f6d6079ef88ff20c7da3422d1298d614ed6b5a
author Subrata Banik <subrata.banik@intel.com> Tue Jul 26 15:37:11 2016 +0530
committer Andrey Petrov <andrey.petrov@intel.com> Thu Jul 28 05:17:56 2016 +0200
tree f2856afcff4ce1e104dcc16d75ceea1d7575a9b6
parent 50b9258a0bbe6cf99606c87a5b9b835ff0689a7d

skylake/devicetree: Add LPC EC decode range

Define LPC decode ranges for EC communication.

BUG=chrome-os-partner:55357
BRANCH=none
TEST=Built and boot kunimitsu to ensure no EC timeout error

Change-Id: Idefdd79e67e89a794195c6821fee16550d1eda53
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/15898
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/mainboard/intel/kunimitsu/devicetree.cb

diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index 4aeb0b1..07efd54 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -12,8 +12,9 @@
 	register "gpe0_dw1" = "GPP_D"
 	register "gpe0_dw2" = "GPP_E"
 
-	# EC host command range is in 0x800-0x8ff
+	# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
 	register "gen1_dec" = "0x00fc0801"
+	register "gen2_dec" = "0x000c0201"
 
 	# Enable "Intel Speed Shift Technology"
 	register "speed_shift_enable" = "1"