Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 3 | # Enable deep Sx states |
| 4 | register "deep_s3_enable" = "1" |
| 5 | register "deep_s5_enable" = "1" |
| 6 | register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" |
| 7 | |
| 8 | # GPE configuration |
| 9 | # Note that GPE events called out in ASL code rely on this |
| 10 | # route. i.e. If this route changes then the affected GPE |
| 11 | # offset bits also need to be changed. |
| 12 | register "gpe0_dw0" = "GPP_C" |
| 13 | register "gpe0_dw1" = "GPP_D" |
| 14 | register "gpe0_dw2" = "GPP_E" |
| 15 | |
| 16 | # EC host command range is in 0x800-0x8ff |
| 17 | register "gen1_dec" = "0x00fc0801" |
| 18 | |
Duncan Laurie | 74b964e | 2015-09-04 10:41:02 -0700 | [diff] [blame^] | 19 | # Enable DPTF |
| 20 | register "dptf_enable" = "1" |
| 21 | |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 22 | # FSP Configuration |
| 23 | register "ProbelessTrace" = "0" |
| 24 | register "EnableLan" = "0" |
| 25 | register "EnableSata" = "0" |
| 26 | register "SataSalpSupport" = "0" |
| 27 | register "SataMode" = "0" |
| 28 | register "SataPortsEnable[0]" = "0" |
| 29 | register "EnableAzalia" = "1" |
| 30 | register "DspEnable" = "1" |
| 31 | register "IoBufferOwnership" = "3" |
| 32 | register "EnableTraceHub" = "0" |
| 33 | register "XdciEnable" = "0" |
| 34 | register "SsicPortEnable" = "0" |
| 35 | register "SmbusEnable" = "1" |
| 36 | register "Cio2Enable" = "0" |
| 37 | register "ScsEmmcEnabled" = "1" |
| 38 | register "ScsEmmcHs400Enabled" = "1" |
| 39 | register "ScsSdCardEnabled" = "2" |
| 40 | register "IshEnable" = "0" |
| 41 | register "PttSwitch" = "0" |
| 42 | register "InternalGfx" = "1" |
| 43 | register "SkipExtGfxScan" = "1" |
| 44 | register "Device4Enable" = "1" |
| 45 | |
| 46 | # Enable Root port 1 and 5. |
| 47 | register "PcieRpEnable[0]" = "1" |
| 48 | register "PcieRpEnable[4]" = "1" |
| 49 | # Enable CLKREQ# |
| 50 | register "PcieRpClkReqSupport[0]" = "1" |
| 51 | register "PcieRpClkReqSupport[4]" = "1" |
| 52 | # RP 1 uses SRCCLKREQ1# while RP 5 uses SRCCLKREQ2# |
| 53 | register "PcieRpClkReqNumber[0]" = "1" |
| 54 | register "PcieRpClkReqNumber[4]" = "2" |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 55 | |
Duncan Laurie | cae067f | 2015-08-31 10:01:03 -0700 | [diff] [blame] | 56 | register "PortUsb20Enable[0]" = "1" # Type-C Port 1 |
| 57 | register "PortUsb20Enable[1]" = "1" # Type-C Port 2 |
| 58 | register "PortUsb20Enable[2]" = "1" # Bluetooth |
| 59 | register "PortUsb20Enable[4]" = "1" # Type-A Port (card) |
| 60 | register "PortUsb20Enable[6]" = "1" # Camera |
| 61 | register "PortUsb20Enable[8]" = "1" # Type-A Port (board) |
Duncan Laurie | 2b9595a | 2015-08-28 17:48:11 -0700 | [diff] [blame] | 62 | |
Duncan Laurie | cae067f | 2015-08-31 10:01:03 -0700 | [diff] [blame] | 63 | register "PortUsb30Enable[0]" = "1" # Type-C Port 1 |
| 64 | register "PortUsb30Enable[1]" = "1" # Type-C Port 2 |
| 65 | register "PortUsb30Enable[2]" = "1" # Type-A Port (card) |
| 66 | register "PortUsb30Enable[3]" = "1" # Type-A Port (board) |
Duncan Laurie | 2b9595a | 2015-08-28 17:48:11 -0700 | [diff] [blame] | 67 | |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 68 | # Must leave UART0 enabled or SD/eMMC will not work as PCI |
| 69 | register "SerialIoDevMode" = "{ \ |
| 70 | [PchSerialIoIndexI2C0] = PchSerialIoPci, \ |
| 71 | [PchSerialIoIndexI2C1] = PchSerialIoPci, \ |
| 72 | [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ |
| 73 | [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ |
| 74 | [PchSerialIoIndexI2C4] = PchSerialIoPci, \ |
| 75 | [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ |
| 76 | [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ |
| 77 | [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ |
| 78 | [PchSerialIoIndexUart0] = PchSerialIoPci, \ |
| 79 | [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ |
| 80 | [PchSerialIoIndexUart2] = PchSerialIoPci, \ |
| 81 | }" |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 82 | |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 83 | device cpu_cluster 0 on |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 84 | device lapic 0 on end |
| 85 | end |
| 86 | device domain 0 on |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 87 | device pci 00.0 on end # Host Bridge |
| 88 | device pci 02.0 on end # Integrated Graphics Device |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 89 | device pci 14.0 on end # USB xHCI |
| 90 | device pci 14.1 off end # USB xDCI (OTG) |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 91 | device pci 14.2 on end # Thermal Subsystem |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 92 | device pci 15.0 on end # I2C #0 |
| 93 | device pci 15.1 on end # I2C #1 |
| 94 | device pci 15.2 off end # I2C #2 |
| 95 | device pci 15.3 off end # I2C #3 |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 96 | device pci 16.0 on end # Management Engine Interface 1 |
| 97 | device pci 16.1 off end # Management Engine Interface 2 |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 98 | device pci 16.2 off end # Management Engine IDE-R |
| 99 | device pci 16.3 off end # Management Engine KT Redirection |
| 100 | device pci 16.4 off end # Management Engine Interface 3 |
| 101 | device pci 17.0 off end # SATA |
| 102 | device pci 19.0 on end # UART #2 |
| 103 | device pci 19.1 off end # I2C #5 |
| 104 | device pci 19.2 on end # I2C #4 |
Pratik Prajapati | f1acb9b | 2015-08-13 15:21:37 -0700 | [diff] [blame] | 105 | device pci 1c.0 on end # PCI Express Port 1 |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 106 | device pci 1c.1 off end # PCI Express Port 2 |
| 107 | device pci 1c.2 off end # PCI Express Port 3 |
| 108 | device pci 1c.3 off end # PCI Express Port 4 |
Pratik Prajapati | f1acb9b | 2015-08-13 15:21:37 -0700 | [diff] [blame] | 109 | device pci 1c.4 on end # PCI Express Port 5 |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 110 | device pci 1c.5 off end # PCI Express Port 6 |
| 111 | device pci 1c.6 off end # PCI Express Port 7 |
| 112 | device pci 1c.7 off end # PCI Express Port 8 |
Pratik Prajapati | f1acb9b | 2015-08-13 15:21:37 -0700 | [diff] [blame] | 113 | device pci 1d.0 off end # PCI Express Port 9 |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 114 | device pci 1d.1 off end # PCI Express Port 10 |
| 115 | device pci 1d.2 off end # PCI Express Port 11 |
| 116 | device pci 1d.3 off end # PCI Express Port 12 |
| 117 | device pci 1e.0 on end # UART #0 |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 118 | device pci 1e.1 off end # UART #1 |
| 119 | device pci 1e.2 off end # GSPI #0 |
| 120 | device pci 1e.3 off end # GSPI #1 |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 121 | device pci 1e.4 on end # eMMC |
| 122 | device pci 1e.5 off end # SDIO |
| 123 | device pci 1e.6 on end # SDCard |
| 124 | device pci 1f.0 on |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 125 | chip drivers/pc80/tpm |
| 126 | device pnp 0c31.0 on end |
| 127 | end |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 128 | chip ec/google/chromeec |
| 129 | device pnp 0c09.0 on end |
| 130 | end |
| 131 | end # LPC Interface |
Naveen Krishna Chatradhi | 133dcd3 | 2015-07-10 16:00:51 +0530 | [diff] [blame] | 132 | device pci 1f.2 on end # Power Management Controller |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 133 | device pci 1f.3 on end # Intel HDA |
| 134 | device pci 1f.4 on end # SMBus |
| 135 | device pci 1f.5 on end # PCH SPI |
| 136 | device pci 1f.6 off end # GbE |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 137 | end |
| 138 | end |