intel/kunimitsu: Add new configuration parameters
Add new configuration parameters eg. #SLP_S3 assert width
BRANCH=none
BUG=chrome-os-partner:44075
TEST=Build and booted on kunimitsu, verified that CB is doing
the Lockdowns which were previously done by FSP.
CQ-DEPEND=CL:310869
Change-Id: I782df49bbf73c121b191f0661907173c4fd29b64
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: de0742869b1b148597d3714a3bc29a0dc08642aa
Original-Change-Id: I2b4041cdc22a29e79d2ff7f2cc49f51f80da5567
Original-Reviewed-on: https://chromium-review.googlesource.com/313309
Original-Commit-Ready: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Tested-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12942
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index e377a51..ec67ce1 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -1,7 +1,6 @@
chip soc/intel/skylake
# Enable deep Sx states
- register "deep_s3_enable" = "0"
register "deep_s5_enable" = "1"
register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
@@ -20,28 +19,33 @@
register "dptf_enable" = "1"
# FSP Configuration
- register "ProbelessTrace" = "0"
- register "EnableLan" = "0"
- register "EnableSata" = "0"
- register "SataSalpSupport" = "0"
- register "SataMode" = "0"
- register "SataPortsEnable[0]" = "0"
register "EnableAzalia" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
- register "EnableTraceHub" = "0"
- register "XdciEnable" = "0"
- register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
- register "Cio2Enable" = "0"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "2"
- register "IshEnable" = "0"
- register "PttSwitch" = "0"
register "InternalGfx" = "1"
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
+ register "WakeConfigWolEnableOverride" = "0x01"
+
+ # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
+ # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
+ register "PmConfigSlpS3MinAssert" = "0x02"
+
+ # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s
+ register "PmConfigSlpS4MinAssert" = "0x04"
+
+ # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s
+ register "PmConfigSlpSusMinAssert" = "0x03"
+
+ # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s
+ register "PmConfigSlpAMinAssert" = "0x03"
+
+ # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled
+ register "SerialIrqConfigSirqEnable" = "0x01"
# Enable Root port 1 and 5.
register "PcieRpEnable[0]" = "1"