Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame^] | 1 | chip soc/intel/skylake |
| 2 | |
| 3 | # SerialIO device modes |
| 4 | register "SerialIoDevMode" = "{ \ |
| 5 | [PchSerialIoIndexI2C0] = PchSerialIoPci, \ |
| 6 | [PchSerialIoIndexI2C1] = PchSerialIoPci, \ |
| 7 | [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ |
| 8 | [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ |
| 9 | [PchSerialIoIndexI2C4] = PchSerialIoPci, \ |
| 10 | [PchSerialIoIndexI2C5] = PchSerialIoPci, \ |
| 11 | [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ |
| 12 | [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ |
| 13 | [PchSerialIoIndexUart0] = PchSerialIoPci, \ |
| 14 | [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ |
| 15 | [PchSerialIoIndexUart2] = PchSerialIoLegacyUart, \ |
| 16 | }" |
| 17 | |
| 18 | register "pirqa_routing" = "0x8b" |
| 19 | register "pirqb_routing" = "0x8a" |
| 20 | register "pirqc_routing" = "0x8b" |
| 21 | register "pirqd_routing" = "0x8b" |
| 22 | register "pirqe_routing" = "0x80" |
| 23 | register "pirqf_routing" = "0x80" |
| 24 | register "pirqg_routing" = "0x80" |
| 25 | register "pirqh_routing" = "0x80" |
| 26 | |
| 27 | # EC range is 0x800-0x9ff |
| 28 | register "gen1_dec" = "0x00fc0801" |
| 29 | register "gen2_dec" = "0x00fc0901" |
| 30 | |
| 31 | # EC_SMI |
| 32 | register "ec_smi_gpio" = "34" |
| 33 | register "alt_gp_smi_en" = "0x0400" |
| 34 | register "gpe0_en_1" = "0x00000000" |
| 35 | |
| 36 | # EC_SCI is GPIO36 |
| 37 | register "gpe0_en_2" = "0x00000010" |
| 38 | register "gpe0_en_3" = "0x00000000" |
| 39 | register "gpe0_en_4" = "0x00000000" |
| 40 | |
| 41 | # Memory related |
| 42 | register "IedSize" = "0x0" |
| 43 | register "ProbelessTrace" = "0" |
| 44 | |
| 45 | # Lan |
| 46 | register "EnableLan" = "0" |
| 47 | |
| 48 | # SATA related |
| 49 | register "EnableSata" = "0" |
| 50 | register "SataSalpSupport" = "0" |
| 51 | register "SataMode" = "0" |
| 52 | register "SataPortsEnable[0]" = "0" |
| 53 | register "SsicPortEnable" = "0" |
| 54 | |
| 55 | # Audio related |
| 56 | register "EnableAzalia" = "1" |
| 57 | register "EnableTraceHub" = "0" |
| 58 | register "DspEnable" = "1" |
| 59 | |
| 60 | # I/O Buffer Ownership: |
| 61 | # 0: HD-A Link |
| 62 | # 1 Shared, HD-A Link and I2S Port |
| 63 | # 3: I2S Ports |
| 64 | register "IoBufferOwnership" = "3" |
| 65 | |
| 66 | # SMBUS |
| 67 | register "SmbusEnable" = "1" |
| 68 | |
| 69 | # Camera |
| 70 | register "Cio2Enable" = "0" |
| 71 | |
| 72 | # eMMC |
| 73 | register "ScsEmmcEnabled" = "1" |
| 74 | register "ScsEmmcHs400Enabled" = "1" |
| 75 | register "ScsSdCardEnabled" = "2" |
| 76 | |
| 77 | # Integrated Sensor |
| 78 | register "IshEnable" = "0" |
| 79 | |
| 80 | # XDCI controller |
| 81 | register "XdciEnable" = "0" |
| 82 | |
| 83 | device cpu_cluster 0 on |
| 84 | device lapic 0 on end |
| 85 | end |
| 86 | device domain 0 on |
| 87 | # Refered from SKL EDS Vol 1 : Page No: 31-32 |
| 88 | device pci 00.0 on end # Host Bridge |
| 89 | device pci 02.0 on end # Integrated Graphics Device |
| 90 | device pci 14.0 on end # USB 3.0 xHCI Controller |
| 91 | device pci 14.1 off end # USB Device Controller (OTG) |
| 92 | device pci 14.2 on end # Thermal Subsystem |
| 93 | device pci 15.0 on end # I2C Controller #0 |
| 94 | device pci 15.1 on end # I2C Controller #1 |
| 95 | device pci 15.2 on end # I2C Controller #2 |
| 96 | device pci 15.3 on end # I2C Controller #3 |
| 97 | device pci 16.0 on end # Management Engine Interface 1 |
| 98 | device pci 16.1 off end # Management Engine Interface 2 |
| 99 | device pci 16.2 off end # Management Engine IDE Redirection (IDE-R) |
| 100 | device pci 16.3 off end # Management Engine Keyboard and Text (KT) Redirection |
| 101 | device pci 16.4 off end # Management Engine Intel MEI #3 |
| 102 | device pci 17.0 off end # SATA Controller |
| 103 | device pci 19.0 on end # UART Controller #2 |
| 104 | device pci 19.1 on end # I2C Controller #5 |
| 105 | device pci 19.2 on end # I2C Controller #4 |
| 106 | device pci 1c.0 off end # PCI Express Port 1 |
| 107 | device pci 1c.1 off end # PCI Express Port 2 |
| 108 | device pci 1c.2 off end # PCI Express Port 3 |
| 109 | device pci 1c.3 off end # PCI Express Port 4 |
| 110 | device pci 1c.4 off end # PCI Express Port 5 |
| 111 | device pci 1c.5 off end # PCI Express Port 6 |
| 112 | device pci 1c.6 off end # PCI Express Port 7 |
| 113 | device pci 1c.7 off end # PCI Express Port 8 |
| 114 | device pci 1d.0 on end # PCI Express Port 9 |
| 115 | device pci 1d.1 off end # PCI Express Port 10 |
| 116 | device pci 1d.2 off end # PCI Express Port 11 |
| 117 | device pci 1d.3 off end # PCI Express Port 12 |
| 118 | device pci 1e.0 on end # UART #0 |
| 119 | device pci 1e.1 on end # UART #1 |
| 120 | device pci 1e.2 on end # SPI #0 |
| 121 | device pci 1e.4 on end # eMMC |
| 122 | device pci 1e.5 off end # SDIO |
| 123 | device pci 1e.6 on end # SDCard |
| 124 | device pci 1f.0 on |
| 125 | chip ec/google/chromeec |
| 126 | device pnp 0c09.0 on end |
| 127 | end |
| 128 | end # LPC Interface |
| 129 | device pci 1f.3 on end # Intel High Definition Audio (Intel HD Audio) (Audio, Voice, Speech) |
| 130 | device pci 1f.4 off end # SMBus Controller |
| 131 | device pci 1f.5 on end # SPI |
| 132 | device pci 1f.6 off end # GbE Controller |
| 133 | end |
| 134 | end |