Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 3 | # Enable deep Sx states |
Duncan Laurie | 1fe32d6 | 2017-04-10 21:02:13 -0700 | [diff] [blame] | 4 | register "deep_s5_enable_ac" = "1" |
| 5 | register "deep_s5_enable_dc" = "1" |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 6 | register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" |
| 7 | |
| 8 | # GPE configuration |
| 9 | # Note that GPE events called out in ASL code rely on this |
| 10 | # route. i.e. If this route changes then the affected GPE |
| 11 | # offset bits also need to be changed. |
Duncan Laurie | d6a42f9 | 2015-09-08 16:28:21 -0700 | [diff] [blame] | 12 | register "gpe0_dw0" = "GPP_B" |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 13 | register "gpe0_dw1" = "GPP_D" |
| 14 | register "gpe0_dw2" = "GPP_E" |
| 15 | |
Subrata Banik | 89f6d60 | 2016-07-26 15:37:11 +0530 | [diff] [blame] | 16 | # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 17 | register "gen1_dec" = "0x00fc0801" |
Subrata Banik | 89f6d60 | 2016-07-26 15:37:11 +0530 | [diff] [blame] | 18 | register "gen2_dec" = "0x000c0201" |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 19 | |
Subrata Banik | 2a696c0 | 2016-02-08 17:19:10 +0530 | [diff] [blame] | 20 | # Enable "Intel Speed Shift Technology" |
| 21 | register "speed_shift_enable" = "1" |
| 22 | |
Duncan Laurie | 74b964e | 2015-09-04 10:41:02 -0700 | [diff] [blame] | 23 | # Enable DPTF |
| 24 | register "dptf_enable" = "1" |
| 25 | |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 26 | # FSP Configuration |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 27 | register "EnableAzalia" = "1" |
| 28 | register "DspEnable" = "1" |
| 29 | register "IoBufferOwnership" = "3" |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 30 | register "SmbusEnable" = "1" |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 31 | register "ScsEmmcEnabled" = "1" |
| 32 | register "ScsEmmcHs400Enabled" = "1" |
| 33 | register "ScsSdCardEnabled" = "2" |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 34 | register "SkipExtGfxScan" = "1" |
| 35 | register "Device4Enable" = "1" |
Archana Patni | 30f53cd | 2015-11-11 01:30:41 +0530 | [diff] [blame] | 36 | register "HeciEnabled" = "0" |
haridhar | f991bf0 | 2015-12-04 10:41:23 +0530 | [diff] [blame] | 37 | register "SaGv" = "3" |
Archana Patni | 4af905a | 2015-12-19 00:10:17 +0530 | [diff] [blame] | 38 | register "PmTimerDisabled" = "1" |
Rizwan Qureshi | fb87998 | 2015-11-19 16:06:28 +0530 | [diff] [blame] | 39 | |
Barnali Sarkar | 8f2f22d | 2016-08-03 12:15:22 +0530 | [diff] [blame] | 40 | register "pirqa_routing" = "PCH_IRQ11" |
| 41 | register "pirqb_routing" = "PCH_IRQ10" |
| 42 | register "pirqc_routing" = "PCH_IRQ11" |
| 43 | register "pirqd_routing" = "PCH_IRQ11" |
| 44 | register "pirqe_routing" = "PCH_IRQ11" |
| 45 | register "pirqf_routing" = "PCH_IRQ11" |
| 46 | register "pirqg_routing" = "PCH_IRQ11" |
| 47 | register "pirqh_routing" = "PCH_IRQ11" |
| 48 | |
Rizwan Qureshi | fb87998 | 2015-11-19 16:06:28 +0530 | [diff] [blame] | 49 | # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch |
| 50 | # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s |
| 51 | register "PmConfigSlpS3MinAssert" = "0x02" |
| 52 | |
| 53 | # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s |
| 54 | register "PmConfigSlpS4MinAssert" = "0x04" |
| 55 | |
| 56 | # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s |
| 57 | register "PmConfigSlpSusMinAssert" = "0x03" |
| 58 | |
| 59 | # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s |
| 60 | register "PmConfigSlpAMinAssert" = "0x03" |
| 61 | |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 62 | |
Michael Niewöhner | dd32103 | 2019-10-09 21:02:36 +0200 | [diff] [blame^] | 63 | # VR Settings Configuration for 4 Domains |
| 64 | #+----------------+-----------+-----------+-------------+----------+ |
| 65 | #| Domain/Setting | SA | IA | GT Unsliced | GT | |
| 66 | #+----------------+-----------+-----------+-------------+----------+ |
| 67 | #| Psi1Threshold | 20A | 20A | 20A | 20A | |
| 68 | #| Psi2Threshold | 4A | 5A | 5A | 5A | |
| 69 | #| Psi3Threshold | 1A | 1A | 1A | 1A | |
| 70 | #| Psi3Enable | 1 | 1 | 1 | 1 | |
| 71 | #| Psi4Enable | 1 | 1 | 1 | 1 | |
| 72 | #| ImonSlope | 0 | 0 | 0 | 0 | |
| 73 | #| ImonOffset | 0 | 0 | 0 | 0 | |
| 74 | #| IccMax | 7A | 34A | 35A | 35A | |
| 75 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | |
| 76 | #+----------------+-----------+-----------+-------------+----------+ |
Rizwan Qureshi | 3fc4277 | 2015-11-20 11:47:40 +0530 | [diff] [blame] | 77 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
Michael Niewöhner | dd32103 | 2019-10-09 21:02:36 +0200 | [diff] [blame^] | 78 | .vr_config_enable = 1, |
| 79 | .psi1threshold = VR_CFG_AMP(20), |
| 80 | .psi2threshold = VR_CFG_AMP(4), |
| 81 | .psi3threshold = VR_CFG_AMP(1), |
| 82 | .psi3enable = 1, |
| 83 | .psi4enable = 1, |
| 84 | .imon_slope = 0x0, |
| 85 | .imon_offset = 0x0, |
| 86 | .icc_max = VR_CFG_AMP(7), |
| 87 | .voltage_limit = 1520, |
Rizwan Qureshi | 3fc4277 | 2015-11-20 11:47:40 +0530 | [diff] [blame] | 88 | }" |
| 89 | |
| 90 | register "domain_vr_config[VR_IA_CORE]" = "{ |
Michael Niewöhner | dd32103 | 2019-10-09 21:02:36 +0200 | [diff] [blame^] | 91 | .vr_config_enable = 1, |
| 92 | .psi1threshold = VR_CFG_AMP(20), |
| 93 | .psi2threshold = VR_CFG_AMP(5), |
| 94 | .psi3threshold = VR_CFG_AMP(1), |
| 95 | .psi3enable = 1, |
| 96 | .psi4enable = 1, |
| 97 | .imon_slope = 0x0, |
| 98 | .imon_offset = 0x0, |
| 99 | .icc_max = VR_CFG_AMP(34), |
| 100 | .voltage_limit = 1520, |
Rizwan Qureshi | 3fc4277 | 2015-11-20 11:47:40 +0530 | [diff] [blame] | 101 | }" |
| 102 | |
| 103 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
Michael Niewöhner | dd32103 | 2019-10-09 21:02:36 +0200 | [diff] [blame^] | 104 | .vr_config_enable = 1, |
| 105 | .psi1threshold = VR_CFG_AMP(20), |
| 106 | .psi2threshold = VR_CFG_AMP(5), |
| 107 | .psi3threshold = VR_CFG_AMP(1), |
| 108 | .psi3enable = 1, |
| 109 | .psi4enable = 1, |
| 110 | .imon_slope = 0x0, |
| 111 | .imon_offset = 0x0, |
| 112 | .icc_max = VR_CFG_AMP(35), |
| 113 | .voltage_limit = 1520, |
Rizwan Qureshi | 3fc4277 | 2015-11-20 11:47:40 +0530 | [diff] [blame] | 114 | }" |
| 115 | |
| 116 | register "domain_vr_config[VR_GT_SLICED]" = "{ |
Michael Niewöhner | dd32103 | 2019-10-09 21:02:36 +0200 | [diff] [blame^] | 117 | .vr_config_enable = 1, |
| 118 | .psi1threshold = VR_CFG_AMP(20), |
| 119 | .psi2threshold = VR_CFG_AMP(5), |
| 120 | .psi3threshold = VR_CFG_AMP(1), |
| 121 | .psi3enable = 1, |
| 122 | .psi4enable = 1, |
| 123 | .imon_slope = 0x0, |
| 124 | .imon_offset = 0x0, |
| 125 | .icc_max = VR_CFG_AMP(35), |
| 126 | .voltage_limit = 1520, |
Rizwan Qureshi | 3fc4277 | 2015-11-20 11:47:40 +0530 | [diff] [blame] | 127 | }" |
| 128 | |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 129 | # Enable Root port 1 and 5. |
| 130 | register "PcieRpEnable[0]" = "1" |
| 131 | register "PcieRpEnable[4]" = "1" |
| 132 | # Enable CLKREQ# |
| 133 | register "PcieRpClkReqSupport[0]" = "1" |
| 134 | register "PcieRpClkReqSupport[4]" = "1" |
| 135 | # RP 1 uses SRCCLKREQ1# while RP 5 uses SRCCLKREQ2# |
| 136 | register "PcieRpClkReqNumber[0]" = "1" |
| 137 | register "PcieRpClkReqNumber[4]" = "2" |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 138 | |
Subrata Banik | 2c3054c | 2016-11-22 20:21:49 +0530 | [diff] [blame] | 139 | register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-C Port 1 |
| 140 | register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # Type-C Port 2 |
| 141 | register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth |
| 142 | register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # Type-A Port (card) |
| 143 | register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera |
| 144 | register "usb2_ports[8]" = "USB2_PORT_LONG(OC3)" # Type-A Port (board) |
Duncan Laurie | 2b9595a | 2015-08-28 17:48:11 -0700 | [diff] [blame] | 145 | |
Subrata Banik | 2c3054c | 2016-11-22 20:21:49 +0530 | [diff] [blame] | 146 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 |
| 147 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 |
| 148 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port (card) |
| 149 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port (board) |
Duncan Laurie | c8d45ac | 2016-06-06 17:21:00 -0700 | [diff] [blame] | 150 | |
Aaron Durbin | ed14a4e | 2016-11-09 17:04:15 -0600 | [diff] [blame] | 151 | register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V |
Rizwan Qureshi | 9cd8e5a | 2015-10-05 19:13:01 +0530 | [diff] [blame] | 152 | |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 153 | # Must leave UART0 enabled or SD/eMMC will not work as PCI |
| 154 | register "SerialIoDevMode" = "{ \ |
| 155 | [PchSerialIoIndexI2C0] = PchSerialIoPci, \ |
| 156 | [PchSerialIoIndexI2C1] = PchSerialIoPci, \ |
| 157 | [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ |
| 158 | [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ |
| 159 | [PchSerialIoIndexI2C4] = PchSerialIoPci, \ |
| 160 | [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ |
| 161 | [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ |
| 162 | [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ |
| 163 | [PchSerialIoIndexUart0] = PchSerialIoPci, \ |
| 164 | [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ |
Rizwan Qureshi | 9cd8e5a | 2015-10-05 19:13:01 +0530 | [diff] [blame] | 165 | [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 166 | }" |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 167 | |
pchandri | f28929d | 2016-01-19 10:49:51 -0800 | [diff] [blame] | 168 | # PL2 override 25W |
| 169 | register "tdp_pl2_override" = "25" |
| 170 | |
Subrata Banik | 9a8b67d | 2016-04-20 14:19:53 +0530 | [diff] [blame] | 171 | # Send an extra VR mailbox command for the PS4 exit issue |
| 172 | register "SendVrMbxCmd" = "2" |
| 173 | |
Duncan Laurie | 9482cf6 | 2016-06-22 11:31:51 -0700 | [diff] [blame] | 174 | # Use default SD card detect GPIO configuration |
| 175 | register "sdcard_cd_gpio_default" = "GPP_A7" |
| 176 | |
Subrata Banik | c204aaa | 2017-08-17 15:49:58 +0530 | [diff] [blame] | 177 | # Lock Down |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 178 | register "common_soc_config" = "{ |
| 179 | .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, |
| 180 | }" |
Subrata Banik | c204aaa | 2017-08-17 15:49:58 +0530 | [diff] [blame] | 181 | |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 182 | device cpu_cluster 0 on |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 183 | device lapic 0 on end |
| 184 | end |
| 185 | device domain 0 on |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 186 | device pci 00.0 on end # Host Bridge |
| 187 | device pci 02.0 on end # Integrated Graphics Device |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 188 | device pci 14.0 on end # USB xHCI |
| 189 | device pci 14.1 off end # USB xDCI (OTG) |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 190 | device pci 14.2 on end # Thermal Subsystem |
Duncan Laurie | 9482cf6 | 2016-06-22 11:31:51 -0700 | [diff] [blame] | 191 | device pci 15.0 on |
| 192 | chip drivers/i2c/generic |
| 193 | register "hid" = ""ELAN0001"" |
| 194 | register "desc" = ""ELAN Touchscreen"" |
Furquan Shaikh | 5b9b593 | 2017-02-21 13:16:30 -0800 | [diff] [blame] | 195 | register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" |
Duncan Laurie | 9482cf6 | 2016-06-22 11:31:51 -0700 | [diff] [blame] | 196 | device i2c 10 on end |
| 197 | end |
| 198 | end # I2C #0 |
| 199 | device pci 15.1 on |
| 200 | chip drivers/i2c/generic |
| 201 | register "hid" = ""ELAN0000"" |
| 202 | register "desc" = ""ELAN Touchpad"" |
Furquan Shaikh | 5b9b593 | 2017-02-21 13:16:30 -0800 | [diff] [blame] | 203 | register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" |
Duncan Laurie | 9482cf6 | 2016-06-22 11:31:51 -0700 | [diff] [blame] | 204 | register "wake" = "GPE0_DW0_05" |
| 205 | device i2c 15 on end |
| 206 | end |
| 207 | end # I2C #1 |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 208 | device pci 15.2 off end # I2C #2 |
| 209 | device pci 15.3 off end # I2C #3 |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 210 | device pci 16.0 on end # Management Engine Interface 1 |
| 211 | device pci 16.1 off end # Management Engine Interface 2 |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 212 | device pci 16.2 off end # Management Engine IDE-R |
| 213 | device pci 16.3 off end # Management Engine KT Redirection |
| 214 | device pci 16.4 off end # Management Engine Interface 3 |
| 215 | device pci 17.0 off end # SATA |
| 216 | device pci 19.0 on end # UART #2 |
| 217 | device pci 19.1 off end # I2C #5 |
Duncan Laurie | 9482cf6 | 2016-06-22 11:31:51 -0700 | [diff] [blame] | 218 | device pci 19.2 on |
| 219 | chip drivers/i2c/nau8825 |
Furquan Shaikh | 5b9b593 | 2017-02-21 13:16:30 -0800 | [diff] [blame] | 220 | register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F10_IRQ)" |
Duncan Laurie | 9482cf6 | 2016-06-22 11:31:51 -0700 | [diff] [blame] | 221 | register "jkdet_enable" = "1" |
| 222 | register "jkdet_pull_enable" = "1" |
| 223 | register "jkdet_pull_up" = "1" |
| 224 | register "jkdet_polarity" = "1" # ActiveLow |
| 225 | register "vref_impedance" = "2" # 125kOhm |
| 226 | register "micbias_voltage" = "6" # 2.754 |
| 227 | register "sar_threshold_num" = "4" |
| 228 | register "sar_threshold[0]" = "0x08" |
| 229 | register "sar_threshold[1]" = "0x12" |
| 230 | register "sar_threshold[2]" = "0x26" |
| 231 | register "sar_threshold[3]" = "0x73" |
| 232 | register "sar_hysteresis" = "0" |
| 233 | register "sar_voltage" = "6" |
| 234 | register "sar_compare_time" = "1" # 1us |
| 235 | register "sar_sampling_time" = "1" # 4us |
| 236 | register "short_key_debounce" = "3" # 30ms |
| 237 | register "jack_insert_debounce" = "7" # 512ms |
| 238 | register "jack_eject_debounce" = "0" |
| 239 | device i2c 1a on end |
| 240 | end |
| 241 | chip drivers/i2c/generic |
| 242 | register "hid" = ""INT343B"" |
| 243 | register "desc" = ""SSM4567 Left Speaker Amp"" |
| 244 | register "uid" = "0" |
| 245 | register "device_present_gpio" = "GPP_E3" |
| 246 | device i2c 34 on end |
| 247 | end |
| 248 | chip drivers/i2c/generic |
| 249 | register "hid" = ""INT343B"" |
| 250 | register "desc" = ""SSM4567 Right Speaker Amp"" |
| 251 | register "uid" = "1" |
| 252 | register "device_present_gpio" = "GPP_E3" |
| 253 | device i2c 35 on end |
| 254 | end |
| 255 | end # I2C #4 |
| 256 | device pci 1c.0 on |
| 257 | chip drivers/intel/wifi |
| 258 | register "wake" = "GPE0_DW0_16" |
| 259 | device pci 00.0 on end |
| 260 | end |
| 261 | end # PCI Express Port 1 |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 262 | device pci 1c.1 off end # PCI Express Port 2 |
| 263 | device pci 1c.2 off end # PCI Express Port 3 |
| 264 | device pci 1c.3 off end # PCI Express Port 4 |
Pratik Prajapati | f1acb9b | 2015-08-13 15:21:37 -0700 | [diff] [blame] | 265 | device pci 1c.4 on end # PCI Express Port 5 |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 266 | device pci 1c.5 off end # PCI Express Port 6 |
| 267 | device pci 1c.6 off end # PCI Express Port 7 |
| 268 | device pci 1c.7 off end # PCI Express Port 8 |
Pratik Prajapati | f1acb9b | 2015-08-13 15:21:37 -0700 | [diff] [blame] | 269 | device pci 1d.0 off end # PCI Express Port 9 |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 270 | device pci 1d.1 off end # PCI Express Port 10 |
| 271 | device pci 1d.2 off end # PCI Express Port 11 |
| 272 | device pci 1d.3 off end # PCI Express Port 12 |
| 273 | device pci 1e.0 on end # UART #0 |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 274 | device pci 1e.1 off end # UART #1 |
| 275 | device pci 1e.2 off end # GSPI #0 |
| 276 | device pci 1e.3 off end # GSPI #1 |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 277 | device pci 1e.4 on end # eMMC |
| 278 | device pci 1e.5 off end # SDIO |
| 279 | device pci 1e.6 on end # SDCard |
| 280 | device pci 1f.0 on |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 281 | chip drivers/pc80/tpm |
| 282 | device pnp 0c31.0 on end |
| 283 | end |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 284 | chip ec/google/chromeec |
| 285 | device pnp 0c09.0 on end |
| 286 | end |
| 287 | end # LPC Interface |
Archana Patni | 30f53cd | 2015-11-11 01:30:41 +0530 | [diff] [blame] | 288 | device pci 1f.1 on end # P2SB |
Naveen Krishna Chatradhi | 133dcd3 | 2015-07-10 16:00:51 +0530 | [diff] [blame] | 289 | device pci 1f.2 on end # Power Management Controller |
Duncan Laurie | 9482cf6 | 2016-06-22 11:31:51 -0700 | [diff] [blame] | 290 | device pci 1f.3 on |
| 291 | chip drivers/generic/max98357a |
Furquan Shaikh | 028200f | 2016-10-04 10:53:32 -0700 | [diff] [blame] | 292 | register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" |
Duncan Laurie | 9482cf6 | 2016-06-22 11:31:51 -0700 | [diff] [blame] | 293 | register "device_present_gpio" = "GPP_E3" |
| 294 | register "device_present_gpio_invert" = "1" |
| 295 | device generic 0 on end |
| 296 | end |
| 297 | end # Intel HDA |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 298 | device pci 1f.4 on end # SMBus |
| 299 | device pci 1f.5 on end # PCH SPI |
| 300 | device pci 1f.6 off end # GbE |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 301 | end |
| 302 | end |