Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
| 3 | # SerialIO device modes |
| 4 | register "SerialIoDevMode" = "{ \ |
| 5 | [PchSerialIoIndexI2C0] = PchSerialIoPci, \ |
| 6 | [PchSerialIoIndexI2C1] = PchSerialIoPci, \ |
| 7 | [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ |
| 8 | [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ |
| 9 | [PchSerialIoIndexI2C4] = PchSerialIoPci, \ |
| 10 | [PchSerialIoIndexI2C5] = PchSerialIoPci, \ |
| 11 | [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ |
| 12 | [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ |
| 13 | [PchSerialIoIndexUart0] = PchSerialIoPci, \ |
| 14 | [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ |
Naveen Krishna Chatradhi | 75154b8 | 2015-07-09 18:00:40 +0530 | [diff] [blame] | 15 | [PchSerialIoIndexUart2] = PchSerialIoPci, \ |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 16 | }" |
| 17 | |
Duncan Laurie | 2b9595a | 2015-08-28 17:48:11 -0700 | [diff] [blame^] | 18 | register "PortUsb20Enable[0]" = "1" /* Type-C Port 1 */ |
| 19 | register "PortUsb20Enable[1]" = "1" /* Type-C Port 2 */ |
| 20 | register "PortUsb20Enable[2]" = "1" /* Bluetooth */ |
| 21 | register "PortUsb20Enable[4]" = "1" /* Type-A Port (card) */ |
| 22 | register "PortUsb20Enable[6]" = "1" /* Camera */ |
| 23 | register "PortUsb20Enable[8]" = "1" /* Type-A Port (board) */ |
| 24 | |
| 25 | register "PortUsb30Enable[0]" = "1" /* Type-C Port 1 */ |
| 26 | register "PortUsb30Enable[1]" = "1" /* Type-C Port 2 */ |
| 27 | register "PortUsb30Enable[2]" = "1" /* Type-A Port (card) */ |
| 28 | register "PortUsb30Enable[3]" = "1" /* Type-A Port (board) */ |
| 29 | |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 30 | register "pirqa_routing" = "0x8b" |
| 31 | register "pirqb_routing" = "0x8a" |
| 32 | register "pirqc_routing" = "0x8b" |
| 33 | register "pirqd_routing" = "0x8b" |
| 34 | register "pirqe_routing" = "0x80" |
| 35 | register "pirqf_routing" = "0x80" |
| 36 | register "pirqg_routing" = "0x80" |
| 37 | register "pirqh_routing" = "0x80" |
| 38 | |
| 39 | # EC range is 0x800-0x9ff |
| 40 | register "gen1_dec" = "0x00fc0801" |
| 41 | register "gen2_dec" = "0x00fc0901" |
| 42 | |
Pravin Angolkar | e56d734 | 2015-07-22 17:27:56 +0530 | [diff] [blame] | 43 | # Pcie RootPort |
| 44 | register "PcieRpEnable[0]" = "1" |
| 45 | register "PcieRpEnable[4]" = "1" |
| 46 | register "PcieRpClkReqNumber[0]" = "1" |
| 47 | register "PcieRpClkReqNumber[4]" = "2" |
Pratik Prajapati | f1acb9b | 2015-08-13 15:21:37 -0700 | [diff] [blame] | 48 | register "PcieRpClkReqSupport[0]" = "1" |
| 49 | register "PcieRpClkReqSupport[4]" = "1" |
Pravin Angolkar | e56d734 | 2015-07-22 17:27:56 +0530 | [diff] [blame] | 50 | |
Aaron Durbin | f50b25d | 2015-08-07 22:57:42 -0500 | [diff] [blame] | 51 | # GPE configuration |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 52 | register "gpe0_en_1" = "0x00000000" |
Pravin Angolkar | e56d734 | 2015-07-22 17:27:56 +0530 | [diff] [blame] | 53 | |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 54 | # EC_SCI is GPIO36 |
| 55 | register "gpe0_en_2" = "0x00000010" |
| 56 | register "gpe0_en_3" = "0x00000000" |
| 57 | register "gpe0_en_4" = "0x00000000" |
| 58 | |
| 59 | # Memory related |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 60 | register "ProbelessTrace" = "0" |
| 61 | |
| 62 | # Lan |
| 63 | register "EnableLan" = "0" |
| 64 | |
| 65 | # SATA related |
| 66 | register "EnableSata" = "0" |
| 67 | register "SataSalpSupport" = "0" |
| 68 | register "SataMode" = "0" |
| 69 | register "SataPortsEnable[0]" = "0" |
| 70 | register "SsicPortEnable" = "0" |
| 71 | |
| 72 | # Audio related |
| 73 | register "EnableAzalia" = "1" |
| 74 | register "EnableTraceHub" = "0" |
| 75 | register "DspEnable" = "1" |
| 76 | |
| 77 | # I/O Buffer Ownership: |
| 78 | # 0: HD-A Link |
| 79 | # 1 Shared, HD-A Link and I2S Port |
| 80 | # 3: I2S Ports |
| 81 | register "IoBufferOwnership" = "3" |
| 82 | |
| 83 | # SMBUS |
| 84 | register "SmbusEnable" = "1" |
| 85 | |
| 86 | # Camera |
| 87 | register "Cio2Enable" = "0" |
| 88 | |
| 89 | # eMMC |
| 90 | register "ScsEmmcEnabled" = "1" |
| 91 | register "ScsEmmcHs400Enabled" = "1" |
| 92 | register "ScsSdCardEnabled" = "2" |
| 93 | |
| 94 | # Integrated Sensor |
| 95 | register "IshEnable" = "0" |
| 96 | |
Naveen Krishna Chatradhi | 133dcd3 | 2015-07-10 16:00:51 +0530 | [diff] [blame] | 97 | # Enable deep Sx states |
| 98 | register "deep_s3_enable" = "0" |
| 99 | register "deep_s5_enable" = "1" |
| 100 | |
| 101 | # CPU Thermal participant device |
| 102 | register "Device4Enable" = "1" |
| 103 | |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 104 | # XDCI controller |
| 105 | register "XdciEnable" = "0" |
| 106 | |
| 107 | device cpu_cluster 0 on |
| 108 | device lapic 0 on end |
| 109 | end |
| 110 | device domain 0 on |
| 111 | # Refered from SKL EDS Vol 1 : Page No: 31-32 |
| 112 | device pci 00.0 on end # Host Bridge |
| 113 | device pci 02.0 on end # Integrated Graphics Device |
| 114 | device pci 14.0 on end # USB 3.0 xHCI Controller |
| 115 | device pci 14.1 off end # USB Device Controller (OTG) |
| 116 | device pci 14.2 on end # Thermal Subsystem |
| 117 | device pci 15.0 on end # I2C Controller #0 |
| 118 | device pci 15.1 on end # I2C Controller #1 |
| 119 | device pci 15.2 on end # I2C Controller #2 |
| 120 | device pci 15.3 on end # I2C Controller #3 |
| 121 | device pci 16.0 on end # Management Engine Interface 1 |
| 122 | device pci 16.1 off end # Management Engine Interface 2 |
| 123 | device pci 16.2 off end # Management Engine IDE Redirection (IDE-R) |
| 124 | device pci 16.3 off end # Management Engine Keyboard and Text (KT) Redirection |
| 125 | device pci 16.4 off end # Management Engine Intel MEI #3 |
| 126 | device pci 17.0 off end # SATA Controller |
| 127 | device pci 19.0 on end # UART Controller #2 |
| 128 | device pci 19.1 on end # I2C Controller #5 |
| 129 | device pci 19.2 on end # I2C Controller #4 |
Pratik Prajapati | f1acb9b | 2015-08-13 15:21:37 -0700 | [diff] [blame] | 130 | device pci 1c.0 on end # PCI Express Port 1 |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 131 | device pci 1c.1 off end # PCI Express Port 2 |
| 132 | device pci 1c.2 off end # PCI Express Port 3 |
| 133 | device pci 1c.3 off end # PCI Express Port 4 |
Pratik Prajapati | f1acb9b | 2015-08-13 15:21:37 -0700 | [diff] [blame] | 134 | device pci 1c.4 on end # PCI Express Port 5 |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 135 | device pci 1c.5 off end # PCI Express Port 6 |
| 136 | device pci 1c.6 off end # PCI Express Port 7 |
| 137 | device pci 1c.7 off end # PCI Express Port 8 |
Pratik Prajapati | f1acb9b | 2015-08-13 15:21:37 -0700 | [diff] [blame] | 138 | device pci 1d.0 off end # PCI Express Port 9 |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 139 | device pci 1d.1 off end # PCI Express Port 10 |
| 140 | device pci 1d.2 off end # PCI Express Port 11 |
| 141 | device pci 1d.3 off end # PCI Express Port 12 |
| 142 | device pci 1e.0 on end # UART #0 |
| 143 | device pci 1e.1 on end # UART #1 |
| 144 | device pci 1e.2 on end # SPI #0 |
| 145 | device pci 1e.4 on end # eMMC |
| 146 | device pci 1e.5 off end # SDIO |
| 147 | device pci 1e.6 on end # SDCard |
| 148 | device pci 1f.0 on |
| 149 | chip ec/google/chromeec |
| 150 | device pnp 0c09.0 on end |
| 151 | end |
| 152 | end # LPC Interface |
Naveen Krishna Chatradhi | 133dcd3 | 2015-07-10 16:00:51 +0530 | [diff] [blame] | 153 | device pci 1f.2 on end # Power Management Controller |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 154 | device pci 1f.3 on end # Intel High Definition Audio (Intel HD Audio) (Audio, Voice, Speech) |
Naveen Krishna Chatradhi | 5eed3a5 | 2015-08-10 11:49:07 +0530 | [diff] [blame] | 155 | device pci 1f.4 on end # SMBus Controller |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 156 | device pci 1f.5 on end # SPI |
| 157 | device pci 1f.6 off end # GbE Controller |
| 158 | end |
| 159 | end |