Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 3 | # Enable deep Sx states |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 4 | register "deep_s5_enable" = "1" |
| 5 | register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" |
| 6 | |
| 7 | # GPE configuration |
| 8 | # Note that GPE events called out in ASL code rely on this |
| 9 | # route. i.e. If this route changes then the affected GPE |
| 10 | # offset bits also need to be changed. |
Duncan Laurie | d6a42f9 | 2015-09-08 16:28:21 -0700 | [diff] [blame] | 11 | register "gpe0_dw0" = "GPP_B" |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 12 | register "gpe0_dw1" = "GPP_D" |
| 13 | register "gpe0_dw2" = "GPP_E" |
| 14 | |
| 15 | # EC host command range is in 0x800-0x8ff |
| 16 | register "gen1_dec" = "0x00fc0801" |
| 17 | |
Duncan Laurie | 74b964e | 2015-09-04 10:41:02 -0700 | [diff] [blame] | 18 | # Enable DPTF |
| 19 | register "dptf_enable" = "1" |
| 20 | |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 21 | # FSP Configuration |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 22 | register "EnableAzalia" = "1" |
| 23 | register "DspEnable" = "1" |
| 24 | register "IoBufferOwnership" = "3" |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 25 | register "SmbusEnable" = "1" |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 26 | register "ScsEmmcEnabled" = "1" |
| 27 | register "ScsEmmcHs400Enabled" = "1" |
| 28 | register "ScsSdCardEnabled" = "2" |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 29 | register "InternalGfx" = "1" |
| 30 | register "SkipExtGfxScan" = "1" |
| 31 | register "Device4Enable" = "1" |
Rizwan Qureshi | fb87998 | 2015-11-19 16:06:28 +0530 | [diff] [blame] | 32 | register "WakeConfigWolEnableOverride" = "0x01" |
| 33 | |
| 34 | # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch |
| 35 | # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s |
| 36 | register "PmConfigSlpS3MinAssert" = "0x02" |
| 37 | |
| 38 | # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s |
| 39 | register "PmConfigSlpS4MinAssert" = "0x04" |
| 40 | |
| 41 | # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s |
| 42 | register "PmConfigSlpSusMinAssert" = "0x03" |
| 43 | |
| 44 | # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s |
| 45 | register "PmConfigSlpAMinAssert" = "0x03" |
| 46 | |
| 47 | # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled |
| 48 | register "SerialIrqConfigSirqEnable" = "0x01" |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 49 | |
Rizwan Qureshi | 3fc4277 | 2015-11-20 11:47:40 +0530 | [diff] [blame^] | 50 | # VR Settings Configuration for 5 Domains |
| 51 | #+----------------+-------+-------+-------------+-------------+-------+ |
| 52 | #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | |
| 53 | #+----------------+-------+-------+-------------+-------------+-------+ |
| 54 | #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | |
| 55 | #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | |
| 56 | #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | |
| 57 | #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | |
| 58 | #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | |
| 59 | #| ImonSlope | 0 | 0 | 0 | 0 | 0 | |
| 60 | #| ImonOffset | 0 | 0 | 0 | 0 | 0 | |
| 61 | #| IccMax | 7A | 34A | 34A | 35A | 35A | |
| 62 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | |
| 63 | #+----------------+-------+-------+-------------+-------------+-------+ |
| 64 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
| 65 | .vr_config_enable = 1, \ |
| 66 | .psi1threshold = 0x50, \ |
| 67 | .psi2threshold = 0x10, \ |
| 68 | .psi3threshold = 0x4, \ |
| 69 | .psi3enable = 1, \ |
| 70 | .psi4enable = 1, \ |
| 71 | .imon_slope = 0x0, \ |
| 72 | .imon_offset = 0x0, \ |
| 73 | .icc_max = 0x1C, \ |
| 74 | .voltage_limit = 0x5F0 \ |
| 75 | }" |
| 76 | |
| 77 | register "domain_vr_config[VR_IA_CORE]" = "{ |
| 78 | .vr_config_enable = 1, \ |
| 79 | .psi1threshold = 0x50, \ |
| 80 | .psi2threshold = 0x14, \ |
| 81 | .psi3threshold = 0x4, \ |
| 82 | .psi3enable = 1, \ |
| 83 | .psi4enable = 1, \ |
| 84 | .imon_slope = 0x0, \ |
| 85 | .imon_offset = 0x0, \ |
| 86 | .icc_max = 0x88, \ |
| 87 | .voltage_limit = 0x5F0 \ |
| 88 | }" |
| 89 | register "domain_vr_config[VR_RING]" = "{ |
| 90 | .vr_config_enable = 1, \ |
| 91 | .psi1threshold = 0x50, \ |
| 92 | .psi2threshold = 0x14, \ |
| 93 | .psi3threshold = 0x4, \ |
| 94 | .psi3enable = 1, \ |
| 95 | .psi4enable = 1, \ |
| 96 | .imon_slope = 0x0, \ |
| 97 | .imon_offset = 0x0, \ |
| 98 | .icc_max = 0x88, \ |
| 99 | .voltage_limit = 0x5F0, \ |
| 100 | }" |
| 101 | |
| 102 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
| 103 | .vr_config_enable = 1, \ |
| 104 | .psi1threshold = 0x50, \ |
| 105 | .psi2threshold = 0x14, \ |
| 106 | .psi3threshold = 0x4, \ |
| 107 | .psi3enable = 1, \ |
| 108 | .psi4enable = 1, \ |
| 109 | .imon_slope = 0x0, \ |
| 110 | .imon_offset = 0x0, \ |
| 111 | .icc_max = 0x8C ,\ |
| 112 | .voltage_limit = 0x5F0 \ |
| 113 | }" |
| 114 | |
| 115 | register "domain_vr_config[VR_GT_SLICED]" = "{ |
| 116 | .vr_config_enable = 1, \ |
| 117 | .psi1threshold = 0x50, \ |
| 118 | .psi2threshold = 0x14, \ |
| 119 | .psi3threshold = 0x4, \ |
| 120 | .psi3enable = 1, \ |
| 121 | .psi4enable = 1, \ |
| 122 | .imon_slope = 0x0, \ |
| 123 | .imon_offset = 0x0, \ |
| 124 | .icc_max = 0x8C, \ |
| 125 | .voltage_limit = 0x5F0 \ |
| 126 | }" |
| 127 | |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 128 | # Enable Root port 1 and 5. |
| 129 | register "PcieRpEnable[0]" = "1" |
| 130 | register "PcieRpEnable[4]" = "1" |
| 131 | # Enable CLKREQ# |
| 132 | register "PcieRpClkReqSupport[0]" = "1" |
| 133 | register "PcieRpClkReqSupport[4]" = "1" |
| 134 | # RP 1 uses SRCCLKREQ1# while RP 5 uses SRCCLKREQ2# |
| 135 | register "PcieRpClkReqNumber[0]" = "1" |
| 136 | register "PcieRpClkReqNumber[4]" = "2" |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 137 | |
Duncan Laurie | fe86666 | 2015-10-16 13:58:11 -0700 | [diff] [blame] | 138 | register "usb2_ports[0]" = "USB2_PORT_TYPE_C" # Type-C Port 1 |
| 139 | register "usb2_ports[1]" = "USB2_PORT_TYPE_C" # Type-C Port 2 |
| 140 | register "usb2_ports[2]" = "USB2_PORT_MID" # Bluetooth |
| 141 | register "usb2_ports[4]" = "USB2_PORT_MID" # Type-A Port (card) |
| 142 | register "usb2_ports[6]" = "USB2_PORT_FLEX" # Camera |
| 143 | register "usb2_ports[8]" = "USB2_PORT_LONG" # Type-A Port (board) |
Duncan Laurie | 2b9595a | 2015-08-28 17:48:11 -0700 | [diff] [blame] | 144 | |
Duncan Laurie | fe86666 | 2015-10-16 13:58:11 -0700 | [diff] [blame] | 145 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT" # Type-C Port 1 |
| 146 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # Type-C Port 2 |
| 147 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port (card) |
| 148 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # Type-A Port (board) |
Rizwan Qureshi | 9cd8e5a | 2015-10-05 19:13:01 +0530 | [diff] [blame] | 149 | |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 150 | # Must leave UART0 enabled or SD/eMMC will not work as PCI |
| 151 | register "SerialIoDevMode" = "{ \ |
| 152 | [PchSerialIoIndexI2C0] = PchSerialIoPci, \ |
| 153 | [PchSerialIoIndexI2C1] = PchSerialIoPci, \ |
| 154 | [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ |
| 155 | [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ |
| 156 | [PchSerialIoIndexI2C4] = PchSerialIoPci, \ |
| 157 | [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ |
| 158 | [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ |
| 159 | [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ |
| 160 | [PchSerialIoIndexUart0] = PchSerialIoPci, \ |
| 161 | [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ |
Rizwan Qureshi | 9cd8e5a | 2015-10-05 19:13:01 +0530 | [diff] [blame] | 162 | [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 163 | }" |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 164 | |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 165 | device cpu_cluster 0 on |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 166 | device lapic 0 on end |
| 167 | end |
| 168 | device domain 0 on |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 169 | device pci 00.0 on end # Host Bridge |
| 170 | device pci 02.0 on end # Integrated Graphics Device |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 171 | device pci 14.0 on end # USB xHCI |
| 172 | device pci 14.1 off end # USB xDCI (OTG) |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 173 | device pci 14.2 on end # Thermal Subsystem |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 174 | device pci 15.0 on end # I2C #0 |
| 175 | device pci 15.1 on end # I2C #1 |
| 176 | device pci 15.2 off end # I2C #2 |
| 177 | device pci 15.3 off end # I2C #3 |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 178 | device pci 16.0 on end # Management Engine Interface 1 |
| 179 | device pci 16.1 off end # Management Engine Interface 2 |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 180 | device pci 16.2 off end # Management Engine IDE-R |
| 181 | device pci 16.3 off end # Management Engine KT Redirection |
| 182 | device pci 16.4 off end # Management Engine Interface 3 |
| 183 | device pci 17.0 off end # SATA |
| 184 | device pci 19.0 on end # UART #2 |
| 185 | device pci 19.1 off end # I2C #5 |
| 186 | device pci 19.2 on end # I2C #4 |
Pratik Prajapati | f1acb9b | 2015-08-13 15:21:37 -0700 | [diff] [blame] | 187 | device pci 1c.0 on end # PCI Express Port 1 |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 188 | device pci 1c.1 off end # PCI Express Port 2 |
| 189 | device pci 1c.2 off end # PCI Express Port 3 |
| 190 | device pci 1c.3 off end # PCI Express Port 4 |
Pratik Prajapati | f1acb9b | 2015-08-13 15:21:37 -0700 | [diff] [blame] | 191 | device pci 1c.4 on end # PCI Express Port 5 |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 192 | device pci 1c.5 off end # PCI Express Port 6 |
| 193 | device pci 1c.6 off end # PCI Express Port 7 |
| 194 | device pci 1c.7 off end # PCI Express Port 8 |
Pratik Prajapati | f1acb9b | 2015-08-13 15:21:37 -0700 | [diff] [blame] | 195 | device pci 1d.0 off end # PCI Express Port 9 |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 196 | device pci 1d.1 off end # PCI Express Port 10 |
| 197 | device pci 1d.2 off end # PCI Express Port 11 |
| 198 | device pci 1d.3 off end # PCI Express Port 12 |
| 199 | device pci 1e.0 on end # UART #0 |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 200 | device pci 1e.1 off end # UART #1 |
| 201 | device pci 1e.2 off end # GSPI #0 |
| 202 | device pci 1e.3 off end # GSPI #1 |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 203 | device pci 1e.4 on end # eMMC |
| 204 | device pci 1e.5 off end # SDIO |
| 205 | device pci 1e.6 on end # SDCard |
| 206 | device pci 1f.0 on |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 207 | chip drivers/pc80/tpm |
| 208 | device pnp 0c31.0 on end |
| 209 | end |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 210 | chip ec/google/chromeec |
| 211 | device pnp 0c09.0 on end |
| 212 | end |
| 213 | end # LPC Interface |
Naveen Krishna Chatradhi | 133dcd3 | 2015-07-10 16:00:51 +0530 | [diff] [blame] | 214 | device pci 1f.2 on end # Power Management Controller |
Duncan Laurie | 1c2de9f | 2015-09-03 16:05:00 -0700 | [diff] [blame] | 215 | device pci 1f.3 on end # Intel HDA |
| 216 | device pci 1f.4 on end # SMBus |
| 217 | device pci 1f.5 on end # PCH SPI |
| 218 | device pci 1f.6 off end # GbE |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 219 | end |
| 220 | end |