Angel Pons | 0612b27 | 2020-04-05 15:46:56 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 2 | |
| 3 | #include <arch/io.h> |
Bill XIE | 516c0a5 | 2020-02-24 23:08:35 +0800 | [diff] [blame] | 4 | #include <bootmode.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 5 | #include <device/mmio.h> |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 6 | #include <cbmem.h> |
Arthur Heymans | 08c646c | 2020-11-19 13:56:41 +0100 | [diff] [blame^] | 7 | #include <cpu/x86/smm.h> |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 8 | #include <console/console.h> |
| 9 | #include <halt.h> |
| 10 | #include <intelblocks/pmclib.h> |
| 11 | #include <intelblocks/gpio.h> |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 12 | #include <intelblocks/tco.h> |
Kyösti Mälkki | cbf9571 | 2020-01-05 08:05:45 +0200 | [diff] [blame] | 13 | #include <option.h> |
Bill XIE | 516c0a5 | 2020-02-24 23:08:35 +0800 | [diff] [blame] | 14 | #include <security/vboot/vboot_common.h> |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 15 | #include <soc/pm.h> |
Nico Huber | 6bbabef | 2019-08-05 21:24:00 +0200 | [diff] [blame] | 16 | #include <stdint.h> |
Shaunak Saha | f073872 | 2017-10-02 15:01:33 -0700 | [diff] [blame] | 17 | #include <string.h> |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 18 | #include <timer.h> |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 19 | |
Arthur Heymans | ea6dd74 | 2019-05-25 10:32:31 +0200 | [diff] [blame] | 20 | static struct chipset_power_state power_state; |
Shaunak Saha | f073872 | 2017-10-02 15:01:33 -0700 | [diff] [blame] | 21 | |
V Sowmya | 186250f | 2020-09-02 16:40:24 +0530 | [diff] [blame] | 22 | /* List of Minimum Assertion durations in microseconds */ |
| 23 | enum min_assert_dur { |
| 24 | MinAssertDur0s = 0, |
| 25 | MinAssertDur60us = 60, |
| 26 | MinAssertDur1ms = 1000, |
| 27 | MinAssertDur50ms = 50000, |
| 28 | MinAssertDur98ms = 98000, |
| 29 | MinAssertDur500ms = 500000, |
| 30 | MinAssertDur1s = 1000000, |
| 31 | MinAssertDur2s = 2000000, |
| 32 | MinAssertDur3s = 3000000, |
| 33 | MinAssertDur4s = 4000000, |
| 34 | }; |
| 35 | |
| 36 | /* Signal Assertion duration values */ |
| 37 | struct cfg_assert_dur { |
| 38 | /* Minimum assertion duration of SLP_A signal */ |
| 39 | enum min_assert_dur slp_a; |
| 40 | |
| 41 | /* Minimum assertion duration of SLP_4 signal */ |
| 42 | enum min_assert_dur slp_s4; |
| 43 | |
| 44 | /* Minimum assertion duration of SLP_3 signal */ |
| 45 | enum min_assert_dur slp_s3; |
| 46 | |
| 47 | /* PCH PM Power Cycle duration */ |
| 48 | enum min_assert_dur pm_pwr_cyc_dur; |
| 49 | }; |
| 50 | |
| 51 | /* Default value of PchPmPwrCycDur */ |
| 52 | #define PCH_PM_PWR_CYC_DUR 0 |
| 53 | |
Shaunak Saha | f073872 | 2017-10-02 15:01:33 -0700 | [diff] [blame] | 54 | struct chipset_power_state *pmc_get_power_state(void) |
| 55 | { |
| 56 | struct chipset_power_state *ptr = NULL; |
| 57 | |
| 58 | if (cbmem_possibly_online()) |
| 59 | ptr = cbmem_find(CBMEM_ID_POWER_STATE); |
| 60 | |
| 61 | /* cbmem is online but ptr is not populated yet */ |
| 62 | if (ptr == NULL && !(ENV_RAMSTAGE || ENV_POSTCAR)) |
Arthur Heymans | ea6dd74 | 2019-05-25 10:32:31 +0200 | [diff] [blame] | 63 | return &power_state; |
Shaunak Saha | f073872 | 2017-10-02 15:01:33 -0700 | [diff] [blame] | 64 | |
| 65 | return ptr; |
| 66 | } |
| 67 | |
| 68 | static void migrate_power_state(int is_recovery) |
| 69 | { |
| 70 | struct chipset_power_state *ps_cbmem; |
Shaunak Saha | f073872 | 2017-10-02 15:01:33 -0700 | [diff] [blame] | 71 | |
Shaunak Saha | f073872 | 2017-10-02 15:01:33 -0700 | [diff] [blame] | 72 | ps_cbmem = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*ps_cbmem)); |
| 73 | |
| 74 | if (ps_cbmem == NULL) { |
| 75 | printk(BIOS_DEBUG, "Not adding power state to cbmem!\n"); |
| 76 | return; |
| 77 | } |
Arthur Heymans | ea6dd74 | 2019-05-25 10:32:31 +0200 | [diff] [blame] | 78 | memcpy(ps_cbmem, &power_state, sizeof(*ps_cbmem)); |
Shaunak Saha | f073872 | 2017-10-02 15:01:33 -0700 | [diff] [blame] | 79 | } |
| 80 | ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state) |
| 81 | |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 82 | static void print_num_status_bits(int num_bits, uint32_t status, |
| 83 | const char *const bit_names[]) |
| 84 | { |
| 85 | int i; |
| 86 | |
| 87 | if (!status) |
| 88 | return; |
| 89 | |
| 90 | for (i = num_bits - 1; i >= 0; i--) { |
| 91 | if (status & (1 << i)) { |
| 92 | if (bit_names[i]) |
| 93 | printk(BIOS_DEBUG, "%s ", bit_names[i]); |
| 94 | else |
| 95 | printk(BIOS_DEBUG, "BIT%d ", i); |
| 96 | } |
| 97 | } |
| 98 | } |
| 99 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 100 | __weak uint32_t soc_get_smi_status(uint32_t generic_sts) |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 101 | { |
| 102 | return generic_sts; |
| 103 | } |
| 104 | |
Bora Guvendik | 3cb0e27 | 2018-09-28 16:19:00 -0700 | [diff] [blame] | 105 | int acpi_get_sleep_type(void) |
| 106 | { |
| 107 | struct chipset_power_state *ps; |
John Zhao | 0ccfc0c | 2018-10-16 10:48:00 -0700 | [diff] [blame] | 108 | int prev_sleep_state = ACPI_S0; |
Bora Guvendik | 3cb0e27 | 2018-09-28 16:19:00 -0700 | [diff] [blame] | 109 | |
| 110 | ps = pmc_get_power_state(); |
John Zhao | 0ccfc0c | 2018-10-16 10:48:00 -0700 | [diff] [blame] | 111 | if (ps) |
| 112 | prev_sleep_state = ps->prev_sleep_state; |
| 113 | |
| 114 | return prev_sleep_state; |
Bora Guvendik | 3cb0e27 | 2018-09-28 16:19:00 -0700 | [diff] [blame] | 115 | } |
| 116 | |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 117 | static uint32_t pmc_reset_smi_status(void) |
| 118 | { |
| 119 | uint32_t smi_sts = inl(ACPI_BASE_ADDRESS + SMI_STS); |
| 120 | outl(smi_sts, ACPI_BASE_ADDRESS + SMI_STS); |
| 121 | |
| 122 | return soc_get_smi_status(smi_sts); |
| 123 | } |
| 124 | |
| 125 | static uint32_t print_smi_status(uint32_t smi_sts) |
| 126 | { |
| 127 | size_t array_size; |
| 128 | const char *const *smi_arr; |
| 129 | |
| 130 | if (!smi_sts) |
| 131 | return 0; |
| 132 | |
| 133 | printk(BIOS_DEBUG, "SMI_STS: "); |
| 134 | |
| 135 | smi_arr = soc_smi_sts_array(&array_size); |
| 136 | |
| 137 | print_num_status_bits(array_size, smi_sts, smi_arr); |
| 138 | printk(BIOS_DEBUG, "\n"); |
| 139 | |
| 140 | return smi_sts; |
| 141 | } |
| 142 | |
Shaunak Saha | 25cc76f | 2017-09-28 15:13:05 -0700 | [diff] [blame] | 143 | /* |
| 144 | * Update supplied events in PM1_EN register. This does not disable any already |
| 145 | * set events. |
| 146 | */ |
| 147 | void pmc_update_pm1_enable(u16 events) |
| 148 | { |
| 149 | u16 pm1_en = pmc_read_pm1_enable(); |
| 150 | pm1_en |= events; |
| 151 | pmc_enable_pm1(pm1_en); |
| 152 | } |
| 153 | |
| 154 | /* Read events set in PM1_EN register. */ |
| 155 | uint16_t pmc_read_pm1_enable(void) |
| 156 | { |
| 157 | return inw(ACPI_BASE_ADDRESS + PM1_EN); |
| 158 | } |
| 159 | |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 160 | uint32_t pmc_clear_smi_status(void) |
| 161 | { |
| 162 | uint32_t sts = pmc_reset_smi_status(); |
| 163 | |
| 164 | return print_smi_status(sts); |
| 165 | } |
| 166 | |
| 167 | uint32_t pmc_get_smi_en(void) |
| 168 | { |
| 169 | return inl(ACPI_BASE_ADDRESS + SMI_EN); |
| 170 | } |
| 171 | |
| 172 | void pmc_enable_smi(uint32_t mask) |
| 173 | { |
| 174 | uint32_t smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN); |
| 175 | smi_en |= mask; |
| 176 | outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN); |
| 177 | } |
| 178 | |
| 179 | void pmc_disable_smi(uint32_t mask) |
| 180 | { |
| 181 | uint32_t smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN); |
| 182 | smi_en &= ~mask; |
| 183 | outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN); |
| 184 | } |
| 185 | |
| 186 | /* PM1 */ |
| 187 | void pmc_enable_pm1(uint16_t events) |
| 188 | { |
| 189 | outw(events, ACPI_BASE_ADDRESS + PM1_EN); |
| 190 | } |
| 191 | |
Furquan Shaikh | ab62018 | 2017-10-16 22:19:13 -0700 | [diff] [blame] | 192 | uint32_t pmc_read_pm1_control(void) |
| 193 | { |
| 194 | return inl(ACPI_BASE_ADDRESS + PM1_CNT); |
| 195 | } |
| 196 | |
| 197 | void pmc_write_pm1_control(uint32_t pm1_cnt) |
| 198 | { |
| 199 | outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT); |
| 200 | } |
| 201 | |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 202 | void pmc_enable_pm1_control(uint32_t mask) |
| 203 | { |
Furquan Shaikh | ab62018 | 2017-10-16 22:19:13 -0700 | [diff] [blame] | 204 | uint32_t pm1_cnt = pmc_read_pm1_control(); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 205 | pm1_cnt |= mask; |
Furquan Shaikh | ab62018 | 2017-10-16 22:19:13 -0700 | [diff] [blame] | 206 | pmc_write_pm1_control(pm1_cnt); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 207 | } |
| 208 | |
| 209 | void pmc_disable_pm1_control(uint32_t mask) |
| 210 | { |
Furquan Shaikh | ab62018 | 2017-10-16 22:19:13 -0700 | [diff] [blame] | 211 | uint32_t pm1_cnt = pmc_read_pm1_control(); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 212 | pm1_cnt &= ~mask; |
Furquan Shaikh | ab62018 | 2017-10-16 22:19:13 -0700 | [diff] [blame] | 213 | pmc_write_pm1_control(pm1_cnt); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 214 | } |
| 215 | |
| 216 | static uint16_t reset_pm1_status(void) |
| 217 | { |
| 218 | uint16_t pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); |
| 219 | outw(pm1_sts, ACPI_BASE_ADDRESS + PM1_STS); |
| 220 | return pm1_sts; |
| 221 | } |
| 222 | |
| 223 | static uint16_t print_pm1_status(uint16_t pm1_sts) |
| 224 | { |
| 225 | static const char *const pm1_sts_bits[] = { |
| 226 | [0] = "TMROF", |
| 227 | [5] = "GBL", |
| 228 | [8] = "PWRBTN", |
| 229 | [10] = "RTC", |
| 230 | [11] = "PRBTNOR", |
| 231 | [13] = "USB", |
| 232 | [14] = "PCIEXPWAK", |
| 233 | [15] = "WAK", |
| 234 | }; |
| 235 | |
| 236 | if (!pm1_sts) |
| 237 | return 0; |
| 238 | |
| 239 | printk(BIOS_SPEW, "PM1_STS: "); |
| 240 | print_num_status_bits(ARRAY_SIZE(pm1_sts_bits), pm1_sts, pm1_sts_bits); |
| 241 | printk(BIOS_SPEW, "\n"); |
| 242 | |
| 243 | return pm1_sts; |
| 244 | } |
| 245 | |
| 246 | uint16_t pmc_clear_pm1_status(void) |
| 247 | { |
| 248 | return print_pm1_status(reset_pm1_status()); |
| 249 | } |
| 250 | |
| 251 | /* TCO */ |
| 252 | |
| 253 | static uint32_t print_tco_status(uint32_t tco_sts) |
| 254 | { |
| 255 | size_t array_size; |
| 256 | const char *const *tco_arr; |
| 257 | |
| 258 | if (!tco_sts) |
| 259 | return 0; |
| 260 | |
| 261 | printk(BIOS_DEBUG, "TCO_STS: "); |
| 262 | |
| 263 | tco_arr = soc_tco_sts_array(&array_size); |
| 264 | |
| 265 | print_num_status_bits(array_size, tco_sts, tco_arr); |
| 266 | printk(BIOS_DEBUG, "\n"); |
| 267 | |
| 268 | return tco_sts; |
| 269 | } |
| 270 | |
| 271 | uint32_t pmc_clear_tco_status(void) |
| 272 | { |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 273 | return print_tco_status(tco_reset_status()); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 274 | } |
| 275 | |
| 276 | /* GPE */ |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 277 | static void pmc_enable_gpe(int gpe, uint32_t mask) |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 278 | { |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 279 | uint32_t gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(gpe)); |
| 280 | gpe0_en |= mask; |
| 281 | outl(gpe0_en, ACPI_BASE_ADDRESS + GPE0_EN(gpe)); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 282 | } |
| 283 | |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 284 | static void pmc_disable_gpe(int gpe, uint32_t mask) |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 285 | { |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 286 | uint32_t gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(gpe)); |
| 287 | gpe0_en &= ~mask; |
| 288 | outl(gpe0_en, ACPI_BASE_ADDRESS + GPE0_EN(gpe)); |
| 289 | } |
| 290 | |
| 291 | void pmc_enable_std_gpe(uint32_t mask) |
| 292 | { |
| 293 | pmc_enable_gpe(GPE_STD, mask); |
| 294 | } |
| 295 | |
| 296 | void pmc_disable_std_gpe(uint32_t mask) |
| 297 | { |
| 298 | pmc_disable_gpe(GPE_STD, mask); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 299 | } |
| 300 | |
| 301 | void pmc_disable_all_gpe(void) |
| 302 | { |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 303 | int i; |
| 304 | for (i = 0; i < GPE0_REG_MAX; i++) |
| 305 | pmc_disable_gpe(i, ~0); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 306 | } |
| 307 | |
| 308 | /* Clear the gpio gpe0 status bits in ACPI registers */ |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 309 | static void pmc_clear_gpi_gpe_status(void) |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 310 | { |
| 311 | int i; |
| 312 | |
| 313 | for (i = 0; i < GPE0_REG_MAX; i++) { |
| 314 | /* This is reserved GPE block and specific to chipset */ |
| 315 | if (i == GPE_STD) |
| 316 | continue; |
| 317 | uint32_t gpe_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(i)); |
| 318 | outl(gpe_sts, ACPI_BASE_ADDRESS + GPE0_STS(i)); |
| 319 | } |
| 320 | } |
| 321 | |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 322 | static uint32_t reset_std_gpe_status(void) |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 323 | { |
| 324 | uint32_t gpe_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(GPE_STD)); |
| 325 | outl(gpe_sts, ACPI_BASE_ADDRESS + GPE0_STS(GPE_STD)); |
| 326 | return gpe_sts; |
| 327 | } |
| 328 | |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 329 | static uint32_t print_std_gpe_sts(uint32_t gpe_sts) |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 330 | { |
| 331 | size_t array_size; |
| 332 | const char *const *sts_arr; |
| 333 | |
| 334 | if (!gpe_sts) |
| 335 | return gpe_sts; |
| 336 | |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 337 | printk(BIOS_DEBUG, "GPE0 STD STS: "); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 338 | |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 339 | sts_arr = soc_std_gpe_sts_array(&array_size); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 340 | print_num_status_bits(array_size, gpe_sts, sts_arr); |
| 341 | printk(BIOS_DEBUG, "\n"); |
| 342 | |
| 343 | return gpe_sts; |
| 344 | } |
| 345 | |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 346 | static void pmc_clear_std_gpe_status(void) |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 347 | { |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 348 | print_std_gpe_sts(reset_std_gpe_status()); |
| 349 | } |
| 350 | |
| 351 | void pmc_clear_all_gpe_status(void) |
| 352 | { |
| 353 | pmc_clear_std_gpe_status(); |
| 354 | pmc_clear_gpi_gpe_status(); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 355 | } |
| 356 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 357 | __weak |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 358 | void soc_clear_pm_registers(uintptr_t pmc_bar) |
| 359 | { |
| 360 | } |
| 361 | |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 362 | void pmc_clear_prsts(void) |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 363 | { |
| 364 | uint32_t prsts; |
| 365 | uintptr_t pmc_bar; |
| 366 | |
| 367 | /* Read PMC base address from soc */ |
| 368 | pmc_bar = soc_read_pmc_base(); |
| 369 | |
| 370 | prsts = read32((void *)(pmc_bar + PRSTS)); |
| 371 | write32((void *)(pmc_bar + PRSTS), prsts); |
| 372 | |
| 373 | soc_clear_pm_registers(pmc_bar); |
| 374 | } |
| 375 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 376 | __weak |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 377 | int soc_prev_sleep_state(const struct chipset_power_state *ps, |
| 378 | int prev_sleep_state) |
| 379 | { |
| 380 | return prev_sleep_state; |
| 381 | } |
| 382 | |
| 383 | /* |
| 384 | * Returns prev_sleep_state and also prints all power management registers. |
Jonathan Neuschäfer | 5268b76 | 2018-02-12 12:24:25 +0100 | [diff] [blame] | 385 | * Calls soc_prev_sleep_state which may be implemented by SOC. |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 386 | */ |
| 387 | static int pmc_prev_sleep_state(const struct chipset_power_state *ps) |
| 388 | { |
| 389 | /* Default to S0. */ |
| 390 | int prev_sleep_state = ACPI_S0; |
| 391 | |
| 392 | if (ps->pm1_sts & WAK_STS) { |
| 393 | switch (acpi_sleep_from_pm1(ps->pm1_cnt)) { |
| 394 | case ACPI_S3: |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 395 | if (CONFIG(HAVE_ACPI_RESUME)) |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 396 | prev_sleep_state = ACPI_S3; |
| 397 | break; |
| 398 | case ACPI_S5: |
| 399 | prev_sleep_state = ACPI_S5; |
| 400 | break; |
| 401 | } |
| 402 | |
| 403 | /* Clear SLP_TYP. */ |
Furquan Shaikh | ab62018 | 2017-10-16 22:19:13 -0700 | [diff] [blame] | 404 | pmc_write_pm1_control(ps->pm1_cnt & ~(SLP_TYP)); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 405 | } |
| 406 | return soc_prev_sleep_state(ps, prev_sleep_state); |
| 407 | } |
| 408 | |
Furquan Shaikh | e48fb54 | 2017-10-17 16:00:10 -0700 | [diff] [blame] | 409 | void pmc_fill_pm_reg_info(struct chipset_power_state *ps) |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 410 | { |
| 411 | int i; |
| 412 | |
Furquan Shaikh | e48fb54 | 2017-10-17 16:00:10 -0700 | [diff] [blame] | 413 | memset(ps, 0, sizeof(*ps)); |
| 414 | |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 415 | ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); |
| 416 | ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN); |
Furquan Shaikh | ab62018 | 2017-10-16 22:19:13 -0700 | [diff] [blame] | 417 | ps->pm1_cnt = pmc_read_pm1_control(); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 418 | |
| 419 | printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n", |
| 420 | ps->pm1_sts, ps->pm1_en, ps->pm1_cnt); |
| 421 | |
| 422 | for (i = 0; i < GPE0_REG_MAX; i++) { |
| 423 | ps->gpe0_sts[i] = inl(ACPI_BASE_ADDRESS + GPE0_STS(i)); |
| 424 | ps->gpe0_en[i] = inl(ACPI_BASE_ADDRESS + GPE0_EN(i)); |
| 425 | printk(BIOS_DEBUG, "gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n", |
| 426 | i, ps->gpe0_sts[i], i, ps->gpe0_en[i]); |
| 427 | } |
| 428 | |
| 429 | soc_fill_power_state(ps); |
Furquan Shaikh | e48fb54 | 2017-10-17 16:00:10 -0700 | [diff] [blame] | 430 | } |
| 431 | |
| 432 | /* Reads and prints ACPI specific PM registers */ |
| 433 | int pmc_fill_power_state(struct chipset_power_state *ps) |
| 434 | { |
| 435 | pmc_fill_pm_reg_info(ps); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 436 | |
| 437 | ps->prev_sleep_state = pmc_prev_sleep_state(ps); |
| 438 | printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); |
| 439 | |
| 440 | return ps->prev_sleep_state; |
| 441 | } |
| 442 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 443 | #if CONFIG(PMC_GLOBAL_RESET_ENABLE_LOCK) |
Michael Niewöhner | 1c6ea92 | 2019-11-02 12:20:53 +0100 | [diff] [blame] | 444 | void pmc_global_reset_disable_and_lock(void) |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 445 | { |
Michael Niewöhner | 1c6ea92 | 2019-11-02 12:20:53 +0100 | [diff] [blame] | 446 | uint32_t *etr = soc_pmc_etr_addr(); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 447 | uint32_t reg; |
| 448 | |
Michael Niewöhner | 1c6ea92 | 2019-11-02 12:20:53 +0100 | [diff] [blame] | 449 | reg = read32(etr); |
| 450 | reg = (reg & ~CF9_GLB_RST) | CF9_LOCK; |
| 451 | write32(etr, reg); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 452 | } |
| 453 | |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 454 | void pmc_global_reset_enable(bool enable) |
| 455 | { |
Michael Niewöhner | 1c6ea92 | 2019-11-02 12:20:53 +0100 | [diff] [blame] | 456 | uint32_t *etr = soc_pmc_etr_addr(); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 457 | uint32_t reg; |
| 458 | |
Michael Niewöhner | 1c6ea92 | 2019-11-02 12:20:53 +0100 | [diff] [blame] | 459 | reg = read32(etr); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 460 | reg = enable ? reg | CF9_GLB_RST : reg & ~CF9_GLB_RST; |
Michael Niewöhner | 1c6ea92 | 2019-11-02 12:20:53 +0100 | [diff] [blame] | 461 | write32(etr, reg); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 462 | } |
Julien Viard de Galbert | 2912e8e | 2018-08-14 16:15:26 +0200 | [diff] [blame] | 463 | #endif // CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 464 | |
Bill XIE | 516c0a5 | 2020-02-24 23:08:35 +0800 | [diff] [blame] | 465 | int platform_is_resuming(void) |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 466 | { |
| 467 | if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS)) |
| 468 | return 0; |
| 469 | |
Furquan Shaikh | ab62018 | 2017-10-16 22:19:13 -0700 | [diff] [blame] | 470 | return acpi_sleep_from_pm1(pmc_read_pm1_control()) == ACPI_S3; |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 471 | } |
| 472 | |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 473 | /* Read and clear GPE status (defined in acpi/acpi.h) */ |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 474 | int acpi_get_gpe(int gpe) |
| 475 | { |
| 476 | int bank; |
| 477 | uint32_t mask, sts; |
| 478 | struct stopwatch sw; |
| 479 | int rc = 0; |
| 480 | |
| 481 | if (gpe < 0 || gpe > GPE_MAX) |
| 482 | return -1; |
| 483 | |
| 484 | bank = gpe / 32; |
| 485 | mask = 1 << (gpe % 32); |
| 486 | |
| 487 | /* Wait up to 1ms for GPE status to clear */ |
| 488 | stopwatch_init_msecs_expire(&sw, 1); |
| 489 | do { |
| 490 | if (stopwatch_expired(&sw)) |
| 491 | return rc; |
| 492 | |
| 493 | sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(bank)); |
| 494 | if (sts & mask) { |
| 495 | outl(mask, ACPI_BASE_ADDRESS + GPE0_STS(bank)); |
| 496 | rc = 1; |
| 497 | } |
| 498 | } while (sts & mask); |
| 499 | |
| 500 | return rc; |
| 501 | } |
| 502 | |
| 503 | /* |
| 504 | * The PM1 control is set to S5 when vboot requests a reboot because the power |
| 505 | * state code above may not have collected its data yet. Therefore, set it to |
| 506 | * S5 when vboot requests a reboot. That's necessary if vboot fails in the |
| 507 | * resume path and requests a reboot. This prevents a reboot loop where the |
| 508 | * error is continually hit on the failing vboot resume path. |
| 509 | */ |
| 510 | void vboot_platform_prepare_reboot(void) |
| 511 | { |
Furquan Shaikh | ab62018 | 2017-10-16 22:19:13 -0700 | [diff] [blame] | 512 | uint32_t pm1_cnt; |
| 513 | pm1_cnt = (pmc_read_pm1_control() & ~(SLP_TYP)) | |
| 514 | (SLP_TYP_S5 << SLP_TYP_SHIFT); |
| 515 | pmc_write_pm1_control(pm1_cnt); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 516 | } |
| 517 | |
| 518 | void poweroff(void) |
| 519 | { |
| 520 | pmc_enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); |
| 521 | |
| 522 | /* |
| 523 | * Setting SLP_TYP_S5 in PM1 triggers SLP_SMI, which is handled by SMM |
| 524 | * to transition to S5 state. If halt is called in SMM, then it prevents |
| 525 | * the SMI handler from being triggered and system never enters S5. |
| 526 | */ |
| 527 | if (!ENV_SMM) |
| 528 | halt(); |
| 529 | } |
| 530 | |
| 531 | void pmc_gpe_init(void) |
| 532 | { |
| 533 | uint32_t gpio_cfg = 0; |
| 534 | uint32_t gpio_cfg_reg; |
| 535 | uint8_t dw0, dw1, dw2; |
| 536 | |
| 537 | /* Read PMC base address from soc. This is implemented in soc */ |
| 538 | uintptr_t pmc_bar = soc_read_pmc_base(); |
| 539 | |
| 540 | /* |
| 541 | * Get the dwX values for pmc gpe settings. |
| 542 | */ |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 543 | soc_get_gpi_gpe_configs(&dw0, &dw1, &dw2); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 544 | |
| 545 | const uint32_t gpio_cfg_mask = |
| 546 | (GPE0_DWX_MASK << GPE0_DW_SHIFT(0)) | |
| 547 | (GPE0_DWX_MASK << GPE0_DW_SHIFT(1)) | |
| 548 | (GPE0_DWX_MASK << GPE0_DW_SHIFT(2)); |
| 549 | |
| 550 | /* Making sure that bad values don't bleed into the other fields */ |
| 551 | dw0 &= GPE0_DWX_MASK; |
| 552 | dw1 &= GPE0_DWX_MASK; |
| 553 | dw2 &= GPE0_DWX_MASK; |
| 554 | |
| 555 | /* |
| 556 | * Route the GPIOs to the GPE0 block. Determine that all values |
| 557 | * are different, and if they aren't use the reset values. |
| 558 | */ |
| 559 | if (dw0 == dw1 || dw1 == dw2) { |
| 560 | printk(BIOS_INFO, "PMC: Using default GPE route.\n"); |
| 561 | gpio_cfg = read32((void *)pmc_bar + GPIO_GPE_CFG); |
| 562 | |
| 563 | dw0 = (gpio_cfg >> GPE0_DW_SHIFT(0)) & GPE0_DWX_MASK; |
| 564 | dw1 = (gpio_cfg >> GPE0_DW_SHIFT(1)) & GPE0_DWX_MASK; |
| 565 | dw2 = (gpio_cfg >> GPE0_DW_SHIFT(2)) & GPE0_DWX_MASK; |
| 566 | } else { |
| 567 | gpio_cfg |= (uint32_t) dw0 << GPE0_DW_SHIFT(0); |
| 568 | gpio_cfg |= (uint32_t) dw1 << GPE0_DW_SHIFT(1); |
| 569 | gpio_cfg |= (uint32_t) dw2 << GPE0_DW_SHIFT(2); |
| 570 | } |
| 571 | |
| 572 | gpio_cfg_reg = read32((void *)pmc_bar + GPIO_GPE_CFG) & ~gpio_cfg_mask; |
| 573 | gpio_cfg_reg |= gpio_cfg & gpio_cfg_mask; |
| 574 | |
| 575 | write32((void *)pmc_bar + GPIO_GPE_CFG, gpio_cfg_reg); |
| 576 | |
| 577 | /* Set the routes in the GPIO communities as well. */ |
| 578 | gpio_route_gpe(dw0, dw1, dw2); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 579 | } |
Nico Huber | ef19ce5 | 2019-08-05 19:19:59 +0200 | [diff] [blame] | 580 | |
| 581 | void pmc_set_power_failure_state(const bool target_on) |
| 582 | { |
Nico Huber | ef19ce5 | 2019-08-05 19:19:59 +0200 | [diff] [blame] | 583 | bool on; |
| 584 | |
Nico Huber | 6bbabef | 2019-08-05 21:24:00 +0200 | [diff] [blame] | 585 | uint8_t state = CONFIG_MAINBOARD_POWER_FAILURE_STATE; |
| 586 | get_option(&state, "power_on_after_fail"); |
| 587 | |
Nico Huber | ef19ce5 | 2019-08-05 19:19:59 +0200 | [diff] [blame] | 588 | switch (state) { |
| 589 | case MAINBOARD_POWER_STATE_OFF: |
| 590 | printk(BIOS_INFO, "Set power off after power failure.\n"); |
| 591 | on = false; |
| 592 | break; |
| 593 | case MAINBOARD_POWER_STATE_ON: |
| 594 | printk(BIOS_INFO, "Set power on after power failure.\n"); |
| 595 | on = true; |
| 596 | break; |
| 597 | case MAINBOARD_POWER_STATE_PREVIOUS: |
| 598 | printk(BIOS_INFO, "Keep power state after power failure.\n"); |
| 599 | on = target_on; |
| 600 | break; |
| 601 | default: |
| 602 | printk(BIOS_WARNING, "WARNING: Unknown power-failure state: %d\n", state); |
| 603 | on = false; |
| 604 | break; |
| 605 | } |
| 606 | |
| 607 | pmc_soc_set_afterg3_en(on); |
| 608 | } |
V Sowmya | 186250f | 2020-09-02 16:40:24 +0530 | [diff] [blame] | 609 | |
| 610 | /* This function returns the highest assertion duration of the SLP_Sx assertion widths */ |
| 611 | static enum min_assert_dur get_high_assert_width(const struct cfg_assert_dur *cfg_assert_dur) |
| 612 | { |
| 613 | enum min_assert_dur max_assert_dur = cfg_assert_dur->slp_s4; |
| 614 | |
| 615 | if (max_assert_dur < cfg_assert_dur->slp_s3) |
| 616 | max_assert_dur = cfg_assert_dur->slp_s3; |
| 617 | |
| 618 | if (max_assert_dur < cfg_assert_dur->slp_a) |
| 619 | max_assert_dur = cfg_assert_dur->slp_a; |
| 620 | |
| 621 | return max_assert_dur; |
| 622 | } |
| 623 | |
| 624 | /* This function converts assertion durations from register-encoded to microseconds */ |
| 625 | static void get_min_assert_dur(uint8_t slp_s4_min_assert, uint8_t slp_s3_min_assert, |
| 626 | uint8_t slp_a_min_assert, uint8_t pm_pwr_cyc_dur, |
| 627 | struct cfg_assert_dur *cfg_assert_dur) |
| 628 | { |
| 629 | /* |
| 630 | * Ensure slp_x_dur_list[] elements in the devicetree config are in sync with |
| 631 | * FSP encoded values. |
| 632 | */ |
| 633 | |
| 634 | /* slp_s4_assert_dur_list : 1s, 1s(default), 2s, 3s, 4s */ |
| 635 | const enum min_assert_dur slp_s4_assert_dur_list[] = { |
| 636 | MinAssertDur1s, MinAssertDur1s, MinAssertDur2s, MinAssertDur3s, MinAssertDur4s |
| 637 | }; |
| 638 | |
| 639 | /* slp_s3_assert_dur_list: 50ms, 60us, 1ms, 50ms (Default), 2s */ |
| 640 | const enum min_assert_dur slp_s3_assert_dur_list[] = { |
| 641 | MinAssertDur50ms, MinAssertDur60us, MinAssertDur1ms, MinAssertDur50ms, |
| 642 | MinAssertDur2s |
| 643 | }; |
| 644 | |
| 645 | /* slp_a_assert_dur_list: 2s, 0s, 4s, 98ms, 2s(Default) */ |
| 646 | const enum min_assert_dur slp_a_assert_dur_list[] = { |
| 647 | MinAssertDur2s, MinAssertDur0s, MinAssertDur4s, MinAssertDur98ms, MinAssertDur2s |
| 648 | }; |
| 649 | |
| 650 | /* pm_pwr_cyc_dur_list: 4s(Default), 1s, 2s, 3s, 4s */ |
| 651 | const enum min_assert_dur pm_pwr_cyc_dur_list[] = { |
| 652 | MinAssertDur4s, MinAssertDur1s, MinAssertDur2s, MinAssertDur3s, MinAssertDur4s |
| 653 | }; |
| 654 | |
| 655 | /* Get signal assertion width */ |
| 656 | if (slp_s4_min_assert < ARRAY_SIZE(slp_s4_assert_dur_list)) |
| 657 | cfg_assert_dur->slp_s4 = slp_s4_assert_dur_list[slp_s4_min_assert]; |
| 658 | |
| 659 | if (slp_s3_min_assert < ARRAY_SIZE(slp_s3_assert_dur_list)) |
| 660 | cfg_assert_dur->slp_s3 = slp_s3_assert_dur_list[slp_s3_min_assert]; |
| 661 | |
| 662 | if (slp_a_min_assert < ARRAY_SIZE(slp_a_assert_dur_list)) |
| 663 | cfg_assert_dur->slp_a = slp_a_assert_dur_list[slp_a_min_assert]; |
| 664 | |
| 665 | if (pm_pwr_cyc_dur < ARRAY_SIZE(pm_pwr_cyc_dur_list)) |
| 666 | cfg_assert_dur->pm_pwr_cyc_dur = pm_pwr_cyc_dur_list[pm_pwr_cyc_dur]; |
| 667 | } |
| 668 | |
| 669 | /* |
| 670 | * This function ensures that the duration programmed in the PchPmPwrCycDur will never be |
| 671 | * smaller than the SLP_Sx assertion widths. |
| 672 | * If the pm_pwr_cyc_dur is less than any of the SLP_Sx assertion widths then it returns the |
| 673 | * default value PCH_PM_PWR_CYC_DUR. |
| 674 | */ |
| 675 | uint8_t get_pm_pwr_cyc_dur(uint8_t slp_s4_min_assert, uint8_t slp_s3_min_assert, |
| 676 | uint8_t slp_a_min_assert, uint8_t pm_pwr_cyc_dur) |
| 677 | { |
| 678 | /* Set default values for the minimum assertion duration */ |
| 679 | struct cfg_assert_dur cfg_assert_dur = { |
| 680 | .slp_a = MinAssertDur2s, |
| 681 | .slp_s4 = MinAssertDur1s, |
| 682 | .slp_s3 = MinAssertDur50ms, |
| 683 | .pm_pwr_cyc_dur = MinAssertDur4s |
| 684 | }; |
| 685 | |
| 686 | enum min_assert_dur high_assert_width; |
| 687 | |
| 688 | /* Convert assertion durations from register-encoded to microseconds */ |
| 689 | get_min_assert_dur(slp_s4_min_assert, slp_s3_min_assert, slp_a_min_assert, |
| 690 | pm_pwr_cyc_dur, &cfg_assert_dur); |
| 691 | |
| 692 | /* Get the highest assertion duration among PCH EDS specified signals for pwr_cyc_dur */ |
| 693 | high_assert_width = get_high_assert_width(&cfg_assert_dur); |
| 694 | |
| 695 | if (cfg_assert_dur.pm_pwr_cyc_dur >= high_assert_width) |
| 696 | return pm_pwr_cyc_dur; |
| 697 | |
| 698 | printk(BIOS_DEBUG, |
| 699 | "Set PmPwrCycDur to 4s as configured PmPwrCycDur (%d) violates PCH EDS " |
| 700 | "spec\n", pm_pwr_cyc_dur); |
| 701 | |
| 702 | return PCH_PM_PWR_CYC_DUR; |
| 703 | } |
Subrata Banik | 3e959d8 | 2020-09-28 17:50:00 +0530 | [diff] [blame] | 704 | |
| 705 | #if CONFIG(PMC_LOW_POWER_MODE_PROGRAM) |
| 706 | void pmc_disable_acpi_timer(void) |
| 707 | { |
| 708 | uint8_t *pmcbase = pmc_mmio_regs(); |
| 709 | |
| 710 | setbits8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS); |
| 711 | } |
Subrata Banik | 3e959d8 | 2020-09-28 17:50:00 +0530 | [diff] [blame] | 712 | #endif /* PMC_LOW_POWER_MODE_PROGRAM */ |
Arthur Heymans | 08c646c | 2020-11-19 13:56:41 +0100 | [diff] [blame^] | 713 | |
| 714 | void pmc_set_acpi_mode(void) |
| 715 | { |
| 716 | if (!acpi_is_wakeup_s3()) { |
| 717 | apm_control(APM_CNT_ACPI_DISABLE); |
| 718 | } |
| 719 | } |