Angel Pons | 0612b27 | 2020-04-05 15:46:56 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 2 | |
| 3 | #include <arch/io.h> |
Bill XIE | 516c0a5 | 2020-02-24 23:08:35 +0800 | [diff] [blame] | 4 | #include <bootmode.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 5 | #include <device/mmio.h> |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 6 | #include <cbmem.h> |
| 7 | #include <console/console.h> |
| 8 | #include <halt.h> |
| 9 | #include <intelblocks/pmclib.h> |
| 10 | #include <intelblocks/gpio.h> |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 11 | #include <intelblocks/tco.h> |
Kyösti Mälkki | cbf9571 | 2020-01-05 08:05:45 +0200 | [diff] [blame] | 12 | #include <option.h> |
Bill XIE | 516c0a5 | 2020-02-24 23:08:35 +0800 | [diff] [blame] | 13 | #include <security/vboot/vboot_common.h> |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 14 | #include <soc/pm.h> |
Nico Huber | 6bbabef | 2019-08-05 21:24:00 +0200 | [diff] [blame] | 15 | #include <stdint.h> |
Shaunak Saha | f073872 | 2017-10-02 15:01:33 -0700 | [diff] [blame] | 16 | #include <string.h> |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 17 | #include <timer.h> |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 18 | |
Arthur Heymans | ea6dd74 | 2019-05-25 10:32:31 +0200 | [diff] [blame] | 19 | static struct chipset_power_state power_state; |
Shaunak Saha | f073872 | 2017-10-02 15:01:33 -0700 | [diff] [blame] | 20 | |
V Sowmya | 186250f | 2020-09-02 16:40:24 +0530 | [diff] [blame^] | 21 | /* List of Minimum Assertion durations in microseconds */ |
| 22 | enum min_assert_dur { |
| 23 | MinAssertDur0s = 0, |
| 24 | MinAssertDur60us = 60, |
| 25 | MinAssertDur1ms = 1000, |
| 26 | MinAssertDur50ms = 50000, |
| 27 | MinAssertDur98ms = 98000, |
| 28 | MinAssertDur500ms = 500000, |
| 29 | MinAssertDur1s = 1000000, |
| 30 | MinAssertDur2s = 2000000, |
| 31 | MinAssertDur3s = 3000000, |
| 32 | MinAssertDur4s = 4000000, |
| 33 | }; |
| 34 | |
| 35 | /* Signal Assertion duration values */ |
| 36 | struct cfg_assert_dur { |
| 37 | /* Minimum assertion duration of SLP_A signal */ |
| 38 | enum min_assert_dur slp_a; |
| 39 | |
| 40 | /* Minimum assertion duration of SLP_4 signal */ |
| 41 | enum min_assert_dur slp_s4; |
| 42 | |
| 43 | /* Minimum assertion duration of SLP_3 signal */ |
| 44 | enum min_assert_dur slp_s3; |
| 45 | |
| 46 | /* PCH PM Power Cycle duration */ |
| 47 | enum min_assert_dur pm_pwr_cyc_dur; |
| 48 | }; |
| 49 | |
| 50 | /* Default value of PchPmPwrCycDur */ |
| 51 | #define PCH_PM_PWR_CYC_DUR 0 |
| 52 | |
Shaunak Saha | f073872 | 2017-10-02 15:01:33 -0700 | [diff] [blame] | 53 | struct chipset_power_state *pmc_get_power_state(void) |
| 54 | { |
| 55 | struct chipset_power_state *ptr = NULL; |
| 56 | |
| 57 | if (cbmem_possibly_online()) |
| 58 | ptr = cbmem_find(CBMEM_ID_POWER_STATE); |
| 59 | |
| 60 | /* cbmem is online but ptr is not populated yet */ |
| 61 | if (ptr == NULL && !(ENV_RAMSTAGE || ENV_POSTCAR)) |
Arthur Heymans | ea6dd74 | 2019-05-25 10:32:31 +0200 | [diff] [blame] | 62 | return &power_state; |
Shaunak Saha | f073872 | 2017-10-02 15:01:33 -0700 | [diff] [blame] | 63 | |
| 64 | return ptr; |
| 65 | } |
| 66 | |
| 67 | static void migrate_power_state(int is_recovery) |
| 68 | { |
| 69 | struct chipset_power_state *ps_cbmem; |
Shaunak Saha | f073872 | 2017-10-02 15:01:33 -0700 | [diff] [blame] | 70 | |
Shaunak Saha | f073872 | 2017-10-02 15:01:33 -0700 | [diff] [blame] | 71 | ps_cbmem = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*ps_cbmem)); |
| 72 | |
| 73 | if (ps_cbmem == NULL) { |
| 74 | printk(BIOS_DEBUG, "Not adding power state to cbmem!\n"); |
| 75 | return; |
| 76 | } |
Arthur Heymans | ea6dd74 | 2019-05-25 10:32:31 +0200 | [diff] [blame] | 77 | memcpy(ps_cbmem, &power_state, sizeof(*ps_cbmem)); |
Shaunak Saha | f073872 | 2017-10-02 15:01:33 -0700 | [diff] [blame] | 78 | } |
| 79 | ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state) |
| 80 | |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 81 | static void print_num_status_bits(int num_bits, uint32_t status, |
| 82 | const char *const bit_names[]) |
| 83 | { |
| 84 | int i; |
| 85 | |
| 86 | if (!status) |
| 87 | return; |
| 88 | |
| 89 | for (i = num_bits - 1; i >= 0; i--) { |
| 90 | if (status & (1 << i)) { |
| 91 | if (bit_names[i]) |
| 92 | printk(BIOS_DEBUG, "%s ", bit_names[i]); |
| 93 | else |
| 94 | printk(BIOS_DEBUG, "BIT%d ", i); |
| 95 | } |
| 96 | } |
| 97 | } |
| 98 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 99 | __weak uint32_t soc_get_smi_status(uint32_t generic_sts) |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 100 | { |
| 101 | return generic_sts; |
| 102 | } |
| 103 | |
Bora Guvendik | 3cb0e27 | 2018-09-28 16:19:00 -0700 | [diff] [blame] | 104 | int acpi_get_sleep_type(void) |
| 105 | { |
| 106 | struct chipset_power_state *ps; |
John Zhao | 0ccfc0c | 2018-10-16 10:48:00 -0700 | [diff] [blame] | 107 | int prev_sleep_state = ACPI_S0; |
Bora Guvendik | 3cb0e27 | 2018-09-28 16:19:00 -0700 | [diff] [blame] | 108 | |
| 109 | ps = pmc_get_power_state(); |
John Zhao | 0ccfc0c | 2018-10-16 10:48:00 -0700 | [diff] [blame] | 110 | if (ps) |
| 111 | prev_sleep_state = ps->prev_sleep_state; |
| 112 | |
| 113 | return prev_sleep_state; |
Bora Guvendik | 3cb0e27 | 2018-09-28 16:19:00 -0700 | [diff] [blame] | 114 | } |
| 115 | |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 116 | static uint32_t pmc_reset_smi_status(void) |
| 117 | { |
| 118 | uint32_t smi_sts = inl(ACPI_BASE_ADDRESS + SMI_STS); |
| 119 | outl(smi_sts, ACPI_BASE_ADDRESS + SMI_STS); |
| 120 | |
| 121 | return soc_get_smi_status(smi_sts); |
| 122 | } |
| 123 | |
| 124 | static uint32_t print_smi_status(uint32_t smi_sts) |
| 125 | { |
| 126 | size_t array_size; |
| 127 | const char *const *smi_arr; |
| 128 | |
| 129 | if (!smi_sts) |
| 130 | return 0; |
| 131 | |
| 132 | printk(BIOS_DEBUG, "SMI_STS: "); |
| 133 | |
| 134 | smi_arr = soc_smi_sts_array(&array_size); |
| 135 | |
| 136 | print_num_status_bits(array_size, smi_sts, smi_arr); |
| 137 | printk(BIOS_DEBUG, "\n"); |
| 138 | |
| 139 | return smi_sts; |
| 140 | } |
| 141 | |
Shaunak Saha | 25cc76f | 2017-09-28 15:13:05 -0700 | [diff] [blame] | 142 | /* |
| 143 | * Update supplied events in PM1_EN register. This does not disable any already |
| 144 | * set events. |
| 145 | */ |
| 146 | void pmc_update_pm1_enable(u16 events) |
| 147 | { |
| 148 | u16 pm1_en = pmc_read_pm1_enable(); |
| 149 | pm1_en |= events; |
| 150 | pmc_enable_pm1(pm1_en); |
| 151 | } |
| 152 | |
| 153 | /* Read events set in PM1_EN register. */ |
| 154 | uint16_t pmc_read_pm1_enable(void) |
| 155 | { |
| 156 | return inw(ACPI_BASE_ADDRESS + PM1_EN); |
| 157 | } |
| 158 | |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 159 | uint32_t pmc_clear_smi_status(void) |
| 160 | { |
| 161 | uint32_t sts = pmc_reset_smi_status(); |
| 162 | |
| 163 | return print_smi_status(sts); |
| 164 | } |
| 165 | |
| 166 | uint32_t pmc_get_smi_en(void) |
| 167 | { |
| 168 | return inl(ACPI_BASE_ADDRESS + SMI_EN); |
| 169 | } |
| 170 | |
| 171 | void pmc_enable_smi(uint32_t mask) |
| 172 | { |
| 173 | uint32_t smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN); |
| 174 | smi_en |= mask; |
| 175 | outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN); |
| 176 | } |
| 177 | |
| 178 | void pmc_disable_smi(uint32_t mask) |
| 179 | { |
| 180 | uint32_t smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN); |
| 181 | smi_en &= ~mask; |
| 182 | outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN); |
| 183 | } |
| 184 | |
| 185 | /* PM1 */ |
| 186 | void pmc_enable_pm1(uint16_t events) |
| 187 | { |
| 188 | outw(events, ACPI_BASE_ADDRESS + PM1_EN); |
| 189 | } |
| 190 | |
Furquan Shaikh | ab62018 | 2017-10-16 22:19:13 -0700 | [diff] [blame] | 191 | uint32_t pmc_read_pm1_control(void) |
| 192 | { |
| 193 | return inl(ACPI_BASE_ADDRESS + PM1_CNT); |
| 194 | } |
| 195 | |
| 196 | void pmc_write_pm1_control(uint32_t pm1_cnt) |
| 197 | { |
| 198 | outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT); |
| 199 | } |
| 200 | |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 201 | void pmc_enable_pm1_control(uint32_t mask) |
| 202 | { |
Furquan Shaikh | ab62018 | 2017-10-16 22:19:13 -0700 | [diff] [blame] | 203 | uint32_t pm1_cnt = pmc_read_pm1_control(); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 204 | pm1_cnt |= mask; |
Furquan Shaikh | ab62018 | 2017-10-16 22:19:13 -0700 | [diff] [blame] | 205 | pmc_write_pm1_control(pm1_cnt); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 206 | } |
| 207 | |
| 208 | void pmc_disable_pm1_control(uint32_t mask) |
| 209 | { |
Furquan Shaikh | ab62018 | 2017-10-16 22:19:13 -0700 | [diff] [blame] | 210 | uint32_t pm1_cnt = pmc_read_pm1_control(); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 211 | pm1_cnt &= ~mask; |
Furquan Shaikh | ab62018 | 2017-10-16 22:19:13 -0700 | [diff] [blame] | 212 | pmc_write_pm1_control(pm1_cnt); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 213 | } |
| 214 | |
| 215 | static uint16_t reset_pm1_status(void) |
| 216 | { |
| 217 | uint16_t pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); |
| 218 | outw(pm1_sts, ACPI_BASE_ADDRESS + PM1_STS); |
| 219 | return pm1_sts; |
| 220 | } |
| 221 | |
| 222 | static uint16_t print_pm1_status(uint16_t pm1_sts) |
| 223 | { |
| 224 | static const char *const pm1_sts_bits[] = { |
| 225 | [0] = "TMROF", |
| 226 | [5] = "GBL", |
| 227 | [8] = "PWRBTN", |
| 228 | [10] = "RTC", |
| 229 | [11] = "PRBTNOR", |
| 230 | [13] = "USB", |
| 231 | [14] = "PCIEXPWAK", |
| 232 | [15] = "WAK", |
| 233 | }; |
| 234 | |
| 235 | if (!pm1_sts) |
| 236 | return 0; |
| 237 | |
| 238 | printk(BIOS_SPEW, "PM1_STS: "); |
| 239 | print_num_status_bits(ARRAY_SIZE(pm1_sts_bits), pm1_sts, pm1_sts_bits); |
| 240 | printk(BIOS_SPEW, "\n"); |
| 241 | |
| 242 | return pm1_sts; |
| 243 | } |
| 244 | |
| 245 | uint16_t pmc_clear_pm1_status(void) |
| 246 | { |
| 247 | return print_pm1_status(reset_pm1_status()); |
| 248 | } |
| 249 | |
| 250 | /* TCO */ |
| 251 | |
| 252 | static uint32_t print_tco_status(uint32_t tco_sts) |
| 253 | { |
| 254 | size_t array_size; |
| 255 | const char *const *tco_arr; |
| 256 | |
| 257 | if (!tco_sts) |
| 258 | return 0; |
| 259 | |
| 260 | printk(BIOS_DEBUG, "TCO_STS: "); |
| 261 | |
| 262 | tco_arr = soc_tco_sts_array(&array_size); |
| 263 | |
| 264 | print_num_status_bits(array_size, tco_sts, tco_arr); |
| 265 | printk(BIOS_DEBUG, "\n"); |
| 266 | |
| 267 | return tco_sts; |
| 268 | } |
| 269 | |
| 270 | uint32_t pmc_clear_tco_status(void) |
| 271 | { |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 272 | return print_tco_status(tco_reset_status()); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 273 | } |
| 274 | |
| 275 | /* GPE */ |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 276 | static void pmc_enable_gpe(int gpe, uint32_t mask) |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 277 | { |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 278 | uint32_t gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(gpe)); |
| 279 | gpe0_en |= mask; |
| 280 | outl(gpe0_en, ACPI_BASE_ADDRESS + GPE0_EN(gpe)); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 281 | } |
| 282 | |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 283 | static void pmc_disable_gpe(int gpe, uint32_t mask) |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 284 | { |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 285 | uint32_t gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(gpe)); |
| 286 | gpe0_en &= ~mask; |
| 287 | outl(gpe0_en, ACPI_BASE_ADDRESS + GPE0_EN(gpe)); |
| 288 | } |
| 289 | |
| 290 | void pmc_enable_std_gpe(uint32_t mask) |
| 291 | { |
| 292 | pmc_enable_gpe(GPE_STD, mask); |
| 293 | } |
| 294 | |
| 295 | void pmc_disable_std_gpe(uint32_t mask) |
| 296 | { |
| 297 | pmc_disable_gpe(GPE_STD, mask); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 298 | } |
| 299 | |
| 300 | void pmc_disable_all_gpe(void) |
| 301 | { |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 302 | int i; |
| 303 | for (i = 0; i < GPE0_REG_MAX; i++) |
| 304 | pmc_disable_gpe(i, ~0); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 305 | } |
| 306 | |
| 307 | /* Clear the gpio gpe0 status bits in ACPI registers */ |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 308 | static void pmc_clear_gpi_gpe_status(void) |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 309 | { |
| 310 | int i; |
| 311 | |
| 312 | for (i = 0; i < GPE0_REG_MAX; i++) { |
| 313 | /* This is reserved GPE block and specific to chipset */ |
| 314 | if (i == GPE_STD) |
| 315 | continue; |
| 316 | uint32_t gpe_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(i)); |
| 317 | outl(gpe_sts, ACPI_BASE_ADDRESS + GPE0_STS(i)); |
| 318 | } |
| 319 | } |
| 320 | |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 321 | static uint32_t reset_std_gpe_status(void) |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 322 | { |
| 323 | uint32_t gpe_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(GPE_STD)); |
| 324 | outl(gpe_sts, ACPI_BASE_ADDRESS + GPE0_STS(GPE_STD)); |
| 325 | return gpe_sts; |
| 326 | } |
| 327 | |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 328 | static uint32_t print_std_gpe_sts(uint32_t gpe_sts) |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 329 | { |
| 330 | size_t array_size; |
| 331 | const char *const *sts_arr; |
| 332 | |
| 333 | if (!gpe_sts) |
| 334 | return gpe_sts; |
| 335 | |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 336 | printk(BIOS_DEBUG, "GPE0 STD STS: "); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 337 | |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 338 | sts_arr = soc_std_gpe_sts_array(&array_size); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 339 | print_num_status_bits(array_size, gpe_sts, sts_arr); |
| 340 | printk(BIOS_DEBUG, "\n"); |
| 341 | |
| 342 | return gpe_sts; |
| 343 | } |
| 344 | |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 345 | static void pmc_clear_std_gpe_status(void) |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 346 | { |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 347 | print_std_gpe_sts(reset_std_gpe_status()); |
| 348 | } |
| 349 | |
| 350 | void pmc_clear_all_gpe_status(void) |
| 351 | { |
| 352 | pmc_clear_std_gpe_status(); |
| 353 | pmc_clear_gpi_gpe_status(); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 354 | } |
| 355 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 356 | __weak |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 357 | void soc_clear_pm_registers(uintptr_t pmc_bar) |
| 358 | { |
| 359 | } |
| 360 | |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 361 | void pmc_clear_prsts(void) |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 362 | { |
| 363 | uint32_t prsts; |
| 364 | uintptr_t pmc_bar; |
| 365 | |
| 366 | /* Read PMC base address from soc */ |
| 367 | pmc_bar = soc_read_pmc_base(); |
| 368 | |
| 369 | prsts = read32((void *)(pmc_bar + PRSTS)); |
| 370 | write32((void *)(pmc_bar + PRSTS), prsts); |
| 371 | |
| 372 | soc_clear_pm_registers(pmc_bar); |
| 373 | } |
| 374 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 375 | __weak |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 376 | int soc_prev_sleep_state(const struct chipset_power_state *ps, |
| 377 | int prev_sleep_state) |
| 378 | { |
| 379 | return prev_sleep_state; |
| 380 | } |
| 381 | |
| 382 | /* |
| 383 | * Returns prev_sleep_state and also prints all power management registers. |
Jonathan Neuschäfer | 5268b76 | 2018-02-12 12:24:25 +0100 | [diff] [blame] | 384 | * Calls soc_prev_sleep_state which may be implemented by SOC. |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 385 | */ |
| 386 | static int pmc_prev_sleep_state(const struct chipset_power_state *ps) |
| 387 | { |
| 388 | /* Default to S0. */ |
| 389 | int prev_sleep_state = ACPI_S0; |
| 390 | |
| 391 | if (ps->pm1_sts & WAK_STS) { |
| 392 | switch (acpi_sleep_from_pm1(ps->pm1_cnt)) { |
| 393 | case ACPI_S3: |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 394 | if (CONFIG(HAVE_ACPI_RESUME)) |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 395 | prev_sleep_state = ACPI_S3; |
| 396 | break; |
| 397 | case ACPI_S5: |
| 398 | prev_sleep_state = ACPI_S5; |
| 399 | break; |
| 400 | } |
| 401 | |
| 402 | /* Clear SLP_TYP. */ |
Furquan Shaikh | ab62018 | 2017-10-16 22:19:13 -0700 | [diff] [blame] | 403 | pmc_write_pm1_control(ps->pm1_cnt & ~(SLP_TYP)); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 404 | } |
| 405 | return soc_prev_sleep_state(ps, prev_sleep_state); |
| 406 | } |
| 407 | |
Furquan Shaikh | e48fb54 | 2017-10-17 16:00:10 -0700 | [diff] [blame] | 408 | void pmc_fill_pm_reg_info(struct chipset_power_state *ps) |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 409 | { |
| 410 | int i; |
| 411 | |
Furquan Shaikh | e48fb54 | 2017-10-17 16:00:10 -0700 | [diff] [blame] | 412 | memset(ps, 0, sizeof(*ps)); |
| 413 | |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 414 | ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); |
| 415 | ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN); |
Furquan Shaikh | ab62018 | 2017-10-16 22:19:13 -0700 | [diff] [blame] | 416 | ps->pm1_cnt = pmc_read_pm1_control(); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 417 | |
| 418 | printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n", |
| 419 | ps->pm1_sts, ps->pm1_en, ps->pm1_cnt); |
| 420 | |
| 421 | for (i = 0; i < GPE0_REG_MAX; i++) { |
| 422 | ps->gpe0_sts[i] = inl(ACPI_BASE_ADDRESS + GPE0_STS(i)); |
| 423 | ps->gpe0_en[i] = inl(ACPI_BASE_ADDRESS + GPE0_EN(i)); |
| 424 | printk(BIOS_DEBUG, "gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n", |
| 425 | i, ps->gpe0_sts[i], i, ps->gpe0_en[i]); |
| 426 | } |
| 427 | |
| 428 | soc_fill_power_state(ps); |
Furquan Shaikh | e48fb54 | 2017-10-17 16:00:10 -0700 | [diff] [blame] | 429 | } |
| 430 | |
| 431 | /* Reads and prints ACPI specific PM registers */ |
| 432 | int pmc_fill_power_state(struct chipset_power_state *ps) |
| 433 | { |
| 434 | pmc_fill_pm_reg_info(ps); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 435 | |
| 436 | ps->prev_sleep_state = pmc_prev_sleep_state(ps); |
| 437 | printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); |
| 438 | |
| 439 | return ps->prev_sleep_state; |
| 440 | } |
| 441 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 442 | #if CONFIG(PMC_GLOBAL_RESET_ENABLE_LOCK) |
Michael Niewöhner | 1c6ea92 | 2019-11-02 12:20:53 +0100 | [diff] [blame] | 443 | void pmc_global_reset_disable_and_lock(void) |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 444 | { |
Michael Niewöhner | 1c6ea92 | 2019-11-02 12:20:53 +0100 | [diff] [blame] | 445 | uint32_t *etr = soc_pmc_etr_addr(); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 446 | uint32_t reg; |
| 447 | |
Michael Niewöhner | 1c6ea92 | 2019-11-02 12:20:53 +0100 | [diff] [blame] | 448 | reg = read32(etr); |
| 449 | reg = (reg & ~CF9_GLB_RST) | CF9_LOCK; |
| 450 | write32(etr, reg); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 451 | } |
| 452 | |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 453 | void pmc_global_reset_enable(bool enable) |
| 454 | { |
Michael Niewöhner | 1c6ea92 | 2019-11-02 12:20:53 +0100 | [diff] [blame] | 455 | uint32_t *etr = soc_pmc_etr_addr(); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 456 | uint32_t reg; |
| 457 | |
Michael Niewöhner | 1c6ea92 | 2019-11-02 12:20:53 +0100 | [diff] [blame] | 458 | reg = read32(etr); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 459 | reg = enable ? reg | CF9_GLB_RST : reg & ~CF9_GLB_RST; |
Michael Niewöhner | 1c6ea92 | 2019-11-02 12:20:53 +0100 | [diff] [blame] | 460 | write32(etr, reg); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 461 | } |
Julien Viard de Galbert | 2912e8e | 2018-08-14 16:15:26 +0200 | [diff] [blame] | 462 | #endif // CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 463 | |
Bill XIE | 516c0a5 | 2020-02-24 23:08:35 +0800 | [diff] [blame] | 464 | int platform_is_resuming(void) |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 465 | { |
| 466 | if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS)) |
| 467 | return 0; |
| 468 | |
Furquan Shaikh | ab62018 | 2017-10-16 22:19:13 -0700 | [diff] [blame] | 469 | return acpi_sleep_from_pm1(pmc_read_pm1_control()) == ACPI_S3; |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 470 | } |
| 471 | |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 472 | /* Read and clear GPE status (defined in acpi/acpi.h) */ |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 473 | int acpi_get_gpe(int gpe) |
| 474 | { |
| 475 | int bank; |
| 476 | uint32_t mask, sts; |
| 477 | struct stopwatch sw; |
| 478 | int rc = 0; |
| 479 | |
| 480 | if (gpe < 0 || gpe > GPE_MAX) |
| 481 | return -1; |
| 482 | |
| 483 | bank = gpe / 32; |
| 484 | mask = 1 << (gpe % 32); |
| 485 | |
| 486 | /* Wait up to 1ms for GPE status to clear */ |
| 487 | stopwatch_init_msecs_expire(&sw, 1); |
| 488 | do { |
| 489 | if (stopwatch_expired(&sw)) |
| 490 | return rc; |
| 491 | |
| 492 | sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(bank)); |
| 493 | if (sts & mask) { |
| 494 | outl(mask, ACPI_BASE_ADDRESS + GPE0_STS(bank)); |
| 495 | rc = 1; |
| 496 | } |
| 497 | } while (sts & mask); |
| 498 | |
| 499 | return rc; |
| 500 | } |
| 501 | |
| 502 | /* |
| 503 | * The PM1 control is set to S5 when vboot requests a reboot because the power |
| 504 | * state code above may not have collected its data yet. Therefore, set it to |
| 505 | * S5 when vboot requests a reboot. That's necessary if vboot fails in the |
| 506 | * resume path and requests a reboot. This prevents a reboot loop where the |
| 507 | * error is continually hit on the failing vboot resume path. |
| 508 | */ |
| 509 | void vboot_platform_prepare_reboot(void) |
| 510 | { |
Furquan Shaikh | ab62018 | 2017-10-16 22:19:13 -0700 | [diff] [blame] | 511 | uint32_t pm1_cnt; |
| 512 | pm1_cnt = (pmc_read_pm1_control() & ~(SLP_TYP)) | |
| 513 | (SLP_TYP_S5 << SLP_TYP_SHIFT); |
| 514 | pmc_write_pm1_control(pm1_cnt); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 515 | } |
| 516 | |
| 517 | void poweroff(void) |
| 518 | { |
| 519 | pmc_enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); |
| 520 | |
| 521 | /* |
| 522 | * Setting SLP_TYP_S5 in PM1 triggers SLP_SMI, which is handled by SMM |
| 523 | * to transition to S5 state. If halt is called in SMM, then it prevents |
| 524 | * the SMI handler from being triggered and system never enters S5. |
| 525 | */ |
| 526 | if (!ENV_SMM) |
| 527 | halt(); |
| 528 | } |
| 529 | |
| 530 | void pmc_gpe_init(void) |
| 531 | { |
| 532 | uint32_t gpio_cfg = 0; |
| 533 | uint32_t gpio_cfg_reg; |
| 534 | uint8_t dw0, dw1, dw2; |
| 535 | |
| 536 | /* Read PMC base address from soc. This is implemented in soc */ |
| 537 | uintptr_t pmc_bar = soc_read_pmc_base(); |
| 538 | |
| 539 | /* |
| 540 | * Get the dwX values for pmc gpe settings. |
| 541 | */ |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 542 | soc_get_gpi_gpe_configs(&dw0, &dw1, &dw2); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 543 | |
| 544 | const uint32_t gpio_cfg_mask = |
| 545 | (GPE0_DWX_MASK << GPE0_DW_SHIFT(0)) | |
| 546 | (GPE0_DWX_MASK << GPE0_DW_SHIFT(1)) | |
| 547 | (GPE0_DWX_MASK << GPE0_DW_SHIFT(2)); |
| 548 | |
| 549 | /* Making sure that bad values don't bleed into the other fields */ |
| 550 | dw0 &= GPE0_DWX_MASK; |
| 551 | dw1 &= GPE0_DWX_MASK; |
| 552 | dw2 &= GPE0_DWX_MASK; |
| 553 | |
| 554 | /* |
| 555 | * Route the GPIOs to the GPE0 block. Determine that all values |
| 556 | * are different, and if they aren't use the reset values. |
| 557 | */ |
| 558 | if (dw0 == dw1 || dw1 == dw2) { |
| 559 | printk(BIOS_INFO, "PMC: Using default GPE route.\n"); |
| 560 | gpio_cfg = read32((void *)pmc_bar + GPIO_GPE_CFG); |
| 561 | |
| 562 | dw0 = (gpio_cfg >> GPE0_DW_SHIFT(0)) & GPE0_DWX_MASK; |
| 563 | dw1 = (gpio_cfg >> GPE0_DW_SHIFT(1)) & GPE0_DWX_MASK; |
| 564 | dw2 = (gpio_cfg >> GPE0_DW_SHIFT(2)) & GPE0_DWX_MASK; |
| 565 | } else { |
| 566 | gpio_cfg |= (uint32_t) dw0 << GPE0_DW_SHIFT(0); |
| 567 | gpio_cfg |= (uint32_t) dw1 << GPE0_DW_SHIFT(1); |
| 568 | gpio_cfg |= (uint32_t) dw2 << GPE0_DW_SHIFT(2); |
| 569 | } |
| 570 | |
| 571 | gpio_cfg_reg = read32((void *)pmc_bar + GPIO_GPE_CFG) & ~gpio_cfg_mask; |
| 572 | gpio_cfg_reg |= gpio_cfg & gpio_cfg_mask; |
| 573 | |
| 574 | write32((void *)pmc_bar + GPIO_GPE_CFG, gpio_cfg_reg); |
| 575 | |
| 576 | /* Set the routes in the GPIO communities as well. */ |
| 577 | gpio_route_gpe(dw0, dw1, dw2); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 578 | } |
Nico Huber | ef19ce5 | 2019-08-05 19:19:59 +0200 | [diff] [blame] | 579 | |
| 580 | void pmc_set_power_failure_state(const bool target_on) |
| 581 | { |
Nico Huber | ef19ce5 | 2019-08-05 19:19:59 +0200 | [diff] [blame] | 582 | bool on; |
| 583 | |
Nico Huber | 6bbabef | 2019-08-05 21:24:00 +0200 | [diff] [blame] | 584 | uint8_t state = CONFIG_MAINBOARD_POWER_FAILURE_STATE; |
| 585 | get_option(&state, "power_on_after_fail"); |
| 586 | |
Nico Huber | ef19ce5 | 2019-08-05 19:19:59 +0200 | [diff] [blame] | 587 | switch (state) { |
| 588 | case MAINBOARD_POWER_STATE_OFF: |
| 589 | printk(BIOS_INFO, "Set power off after power failure.\n"); |
| 590 | on = false; |
| 591 | break; |
| 592 | case MAINBOARD_POWER_STATE_ON: |
| 593 | printk(BIOS_INFO, "Set power on after power failure.\n"); |
| 594 | on = true; |
| 595 | break; |
| 596 | case MAINBOARD_POWER_STATE_PREVIOUS: |
| 597 | printk(BIOS_INFO, "Keep power state after power failure.\n"); |
| 598 | on = target_on; |
| 599 | break; |
| 600 | default: |
| 601 | printk(BIOS_WARNING, "WARNING: Unknown power-failure state: %d\n", state); |
| 602 | on = false; |
| 603 | break; |
| 604 | } |
| 605 | |
| 606 | pmc_soc_set_afterg3_en(on); |
| 607 | } |
V Sowmya | 186250f | 2020-09-02 16:40:24 +0530 | [diff] [blame^] | 608 | |
| 609 | /* This function returns the highest assertion duration of the SLP_Sx assertion widths */ |
| 610 | static enum min_assert_dur get_high_assert_width(const struct cfg_assert_dur *cfg_assert_dur) |
| 611 | { |
| 612 | enum min_assert_dur max_assert_dur = cfg_assert_dur->slp_s4; |
| 613 | |
| 614 | if (max_assert_dur < cfg_assert_dur->slp_s3) |
| 615 | max_assert_dur = cfg_assert_dur->slp_s3; |
| 616 | |
| 617 | if (max_assert_dur < cfg_assert_dur->slp_a) |
| 618 | max_assert_dur = cfg_assert_dur->slp_a; |
| 619 | |
| 620 | return max_assert_dur; |
| 621 | } |
| 622 | |
| 623 | /* This function converts assertion durations from register-encoded to microseconds */ |
| 624 | static void get_min_assert_dur(uint8_t slp_s4_min_assert, uint8_t slp_s3_min_assert, |
| 625 | uint8_t slp_a_min_assert, uint8_t pm_pwr_cyc_dur, |
| 626 | struct cfg_assert_dur *cfg_assert_dur) |
| 627 | { |
| 628 | /* |
| 629 | * Ensure slp_x_dur_list[] elements in the devicetree config are in sync with |
| 630 | * FSP encoded values. |
| 631 | */ |
| 632 | |
| 633 | /* slp_s4_assert_dur_list : 1s, 1s(default), 2s, 3s, 4s */ |
| 634 | const enum min_assert_dur slp_s4_assert_dur_list[] = { |
| 635 | MinAssertDur1s, MinAssertDur1s, MinAssertDur2s, MinAssertDur3s, MinAssertDur4s |
| 636 | }; |
| 637 | |
| 638 | /* slp_s3_assert_dur_list: 50ms, 60us, 1ms, 50ms (Default), 2s */ |
| 639 | const enum min_assert_dur slp_s3_assert_dur_list[] = { |
| 640 | MinAssertDur50ms, MinAssertDur60us, MinAssertDur1ms, MinAssertDur50ms, |
| 641 | MinAssertDur2s |
| 642 | }; |
| 643 | |
| 644 | /* slp_a_assert_dur_list: 2s, 0s, 4s, 98ms, 2s(Default) */ |
| 645 | const enum min_assert_dur slp_a_assert_dur_list[] = { |
| 646 | MinAssertDur2s, MinAssertDur0s, MinAssertDur4s, MinAssertDur98ms, MinAssertDur2s |
| 647 | }; |
| 648 | |
| 649 | /* pm_pwr_cyc_dur_list: 4s(Default), 1s, 2s, 3s, 4s */ |
| 650 | const enum min_assert_dur pm_pwr_cyc_dur_list[] = { |
| 651 | MinAssertDur4s, MinAssertDur1s, MinAssertDur2s, MinAssertDur3s, MinAssertDur4s |
| 652 | }; |
| 653 | |
| 654 | /* Get signal assertion width */ |
| 655 | if (slp_s4_min_assert < ARRAY_SIZE(slp_s4_assert_dur_list)) |
| 656 | cfg_assert_dur->slp_s4 = slp_s4_assert_dur_list[slp_s4_min_assert]; |
| 657 | |
| 658 | if (slp_s3_min_assert < ARRAY_SIZE(slp_s3_assert_dur_list)) |
| 659 | cfg_assert_dur->slp_s3 = slp_s3_assert_dur_list[slp_s3_min_assert]; |
| 660 | |
| 661 | if (slp_a_min_assert < ARRAY_SIZE(slp_a_assert_dur_list)) |
| 662 | cfg_assert_dur->slp_a = slp_a_assert_dur_list[slp_a_min_assert]; |
| 663 | |
| 664 | if (pm_pwr_cyc_dur < ARRAY_SIZE(pm_pwr_cyc_dur_list)) |
| 665 | cfg_assert_dur->pm_pwr_cyc_dur = pm_pwr_cyc_dur_list[pm_pwr_cyc_dur]; |
| 666 | } |
| 667 | |
| 668 | /* |
| 669 | * This function ensures that the duration programmed in the PchPmPwrCycDur will never be |
| 670 | * smaller than the SLP_Sx assertion widths. |
| 671 | * If the pm_pwr_cyc_dur is less than any of the SLP_Sx assertion widths then it returns the |
| 672 | * default value PCH_PM_PWR_CYC_DUR. |
| 673 | */ |
| 674 | uint8_t get_pm_pwr_cyc_dur(uint8_t slp_s4_min_assert, uint8_t slp_s3_min_assert, |
| 675 | uint8_t slp_a_min_assert, uint8_t pm_pwr_cyc_dur) |
| 676 | { |
| 677 | /* Set default values for the minimum assertion duration */ |
| 678 | struct cfg_assert_dur cfg_assert_dur = { |
| 679 | .slp_a = MinAssertDur2s, |
| 680 | .slp_s4 = MinAssertDur1s, |
| 681 | .slp_s3 = MinAssertDur50ms, |
| 682 | .pm_pwr_cyc_dur = MinAssertDur4s |
| 683 | }; |
| 684 | |
| 685 | enum min_assert_dur high_assert_width; |
| 686 | |
| 687 | /* Convert assertion durations from register-encoded to microseconds */ |
| 688 | get_min_assert_dur(slp_s4_min_assert, slp_s3_min_assert, slp_a_min_assert, |
| 689 | pm_pwr_cyc_dur, &cfg_assert_dur); |
| 690 | |
| 691 | /* Get the highest assertion duration among PCH EDS specified signals for pwr_cyc_dur */ |
| 692 | high_assert_width = get_high_assert_width(&cfg_assert_dur); |
| 693 | |
| 694 | if (cfg_assert_dur.pm_pwr_cyc_dur >= high_assert_width) |
| 695 | return pm_pwr_cyc_dur; |
| 696 | |
| 697 | printk(BIOS_DEBUG, |
| 698 | "Set PmPwrCycDur to 4s as configured PmPwrCycDur (%d) violates PCH EDS " |
| 699 | "spec\n", pm_pwr_cyc_dur); |
| 700 | |
| 701 | return PCH_PM_PWR_CYC_DUR; |
| 702 | } |