Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2017 Intel Corporation. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
Shaunak Saha | f073872 | 2017-10-02 15:01:33 -0700 | [diff] [blame^] | 16 | #include <arch/early_variables.h> |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 17 | #include <arch/io.h> |
| 18 | #include <cbmem.h> |
| 19 | #include <console/console.h> |
| 20 | #include <halt.h> |
| 21 | #include <intelblocks/pmclib.h> |
| 22 | #include <intelblocks/gpio.h> |
| 23 | #include <soc/pm.h> |
Shaunak Saha | f073872 | 2017-10-02 15:01:33 -0700 | [diff] [blame^] | 24 | #include <string.h> |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 25 | #include <timer.h> |
| 26 | #include <vboot/vboot_common.h> |
| 27 | |
Shaunak Saha | f073872 | 2017-10-02 15:01:33 -0700 | [diff] [blame^] | 28 | static struct chipset_power_state power_state CAR_GLOBAL; |
| 29 | |
| 30 | struct chipset_power_state *pmc_get_power_state(void) |
| 31 | { |
| 32 | struct chipset_power_state *ptr = NULL; |
| 33 | |
| 34 | if (cbmem_possibly_online()) |
| 35 | ptr = cbmem_find(CBMEM_ID_POWER_STATE); |
| 36 | |
| 37 | /* cbmem is online but ptr is not populated yet */ |
| 38 | if (ptr == NULL && !(ENV_RAMSTAGE || ENV_POSTCAR)) |
| 39 | return car_get_var_ptr(&power_state); |
| 40 | |
| 41 | return ptr; |
| 42 | } |
| 43 | |
| 44 | static void migrate_power_state(int is_recovery) |
| 45 | { |
| 46 | struct chipset_power_state *ps_cbmem; |
| 47 | struct chipset_power_state *ps_car; |
| 48 | |
| 49 | ps_car = car_get_var_ptr(&power_state); |
| 50 | ps_cbmem = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*ps_cbmem)); |
| 51 | |
| 52 | if (ps_cbmem == NULL) { |
| 53 | printk(BIOS_DEBUG, "Not adding power state to cbmem!\n"); |
| 54 | return; |
| 55 | } |
| 56 | memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem)); |
| 57 | } |
| 58 | ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state) |
| 59 | |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 60 | static void print_num_status_bits(int num_bits, uint32_t status, |
| 61 | const char *const bit_names[]) |
| 62 | { |
| 63 | int i; |
| 64 | |
| 65 | if (!status) |
| 66 | return; |
| 67 | |
| 68 | for (i = num_bits - 1; i >= 0; i--) { |
| 69 | if (status & (1 << i)) { |
| 70 | if (bit_names[i]) |
| 71 | printk(BIOS_DEBUG, "%s ", bit_names[i]); |
| 72 | else |
| 73 | printk(BIOS_DEBUG, "BIT%d ", i); |
| 74 | } |
| 75 | } |
| 76 | } |
| 77 | |
| 78 | __attribute__ ((weak)) uint32_t soc_get_smi_status(uint32_t generic_sts) |
| 79 | { |
| 80 | return generic_sts; |
| 81 | } |
| 82 | |
| 83 | static uint32_t pmc_reset_smi_status(void) |
| 84 | { |
| 85 | uint32_t smi_sts = inl(ACPI_BASE_ADDRESS + SMI_STS); |
| 86 | outl(smi_sts, ACPI_BASE_ADDRESS + SMI_STS); |
| 87 | |
| 88 | return soc_get_smi_status(smi_sts); |
| 89 | } |
| 90 | |
| 91 | static uint32_t print_smi_status(uint32_t smi_sts) |
| 92 | { |
| 93 | size_t array_size; |
| 94 | const char *const *smi_arr; |
| 95 | |
| 96 | if (!smi_sts) |
| 97 | return 0; |
| 98 | |
| 99 | printk(BIOS_DEBUG, "SMI_STS: "); |
| 100 | |
| 101 | smi_arr = soc_smi_sts_array(&array_size); |
| 102 | |
| 103 | print_num_status_bits(array_size, smi_sts, smi_arr); |
| 104 | printk(BIOS_DEBUG, "\n"); |
| 105 | |
| 106 | return smi_sts; |
| 107 | } |
| 108 | |
Shaunak Saha | 25cc76f | 2017-09-28 15:13:05 -0700 | [diff] [blame] | 109 | /* |
| 110 | * Update supplied events in PM1_EN register. This does not disable any already |
| 111 | * set events. |
| 112 | */ |
| 113 | void pmc_update_pm1_enable(u16 events) |
| 114 | { |
| 115 | u16 pm1_en = pmc_read_pm1_enable(); |
| 116 | pm1_en |= events; |
| 117 | pmc_enable_pm1(pm1_en); |
| 118 | } |
| 119 | |
| 120 | /* Read events set in PM1_EN register. */ |
| 121 | uint16_t pmc_read_pm1_enable(void) |
| 122 | { |
| 123 | return inw(ACPI_BASE_ADDRESS + PM1_EN); |
| 124 | } |
| 125 | |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 126 | uint32_t pmc_clear_smi_status(void) |
| 127 | { |
| 128 | uint32_t sts = pmc_reset_smi_status(); |
| 129 | |
| 130 | return print_smi_status(sts); |
| 131 | } |
| 132 | |
| 133 | uint32_t pmc_get_smi_en(void) |
| 134 | { |
| 135 | return inl(ACPI_BASE_ADDRESS + SMI_EN); |
| 136 | } |
| 137 | |
| 138 | void pmc_enable_smi(uint32_t mask) |
| 139 | { |
| 140 | uint32_t smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN); |
| 141 | smi_en |= mask; |
| 142 | outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN); |
| 143 | } |
| 144 | |
| 145 | void pmc_disable_smi(uint32_t mask) |
| 146 | { |
| 147 | uint32_t smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN); |
| 148 | smi_en &= ~mask; |
| 149 | outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN); |
| 150 | } |
| 151 | |
| 152 | /* PM1 */ |
| 153 | void pmc_enable_pm1(uint16_t events) |
| 154 | { |
| 155 | outw(events, ACPI_BASE_ADDRESS + PM1_EN); |
| 156 | } |
| 157 | |
| 158 | void pmc_enable_pm1_control(uint32_t mask) |
| 159 | { |
| 160 | uint32_t pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); |
| 161 | pm1_cnt |= mask; |
| 162 | outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT); |
| 163 | } |
| 164 | |
| 165 | void pmc_disable_pm1_control(uint32_t mask) |
| 166 | { |
| 167 | uint32_t pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); |
| 168 | pm1_cnt &= ~mask; |
| 169 | outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT); |
| 170 | } |
| 171 | |
| 172 | static uint16_t reset_pm1_status(void) |
| 173 | { |
| 174 | uint16_t pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); |
| 175 | outw(pm1_sts, ACPI_BASE_ADDRESS + PM1_STS); |
| 176 | return pm1_sts; |
| 177 | } |
| 178 | |
| 179 | static uint16_t print_pm1_status(uint16_t pm1_sts) |
| 180 | { |
| 181 | static const char *const pm1_sts_bits[] = { |
| 182 | [0] = "TMROF", |
| 183 | [5] = "GBL", |
| 184 | [8] = "PWRBTN", |
| 185 | [10] = "RTC", |
| 186 | [11] = "PRBTNOR", |
| 187 | [13] = "USB", |
| 188 | [14] = "PCIEXPWAK", |
| 189 | [15] = "WAK", |
| 190 | }; |
| 191 | |
| 192 | if (!pm1_sts) |
| 193 | return 0; |
| 194 | |
| 195 | printk(BIOS_SPEW, "PM1_STS: "); |
| 196 | print_num_status_bits(ARRAY_SIZE(pm1_sts_bits), pm1_sts, pm1_sts_bits); |
| 197 | printk(BIOS_SPEW, "\n"); |
| 198 | |
| 199 | return pm1_sts; |
| 200 | } |
| 201 | |
| 202 | uint16_t pmc_clear_pm1_status(void) |
| 203 | { |
| 204 | return print_pm1_status(reset_pm1_status()); |
| 205 | } |
| 206 | |
| 207 | /* TCO */ |
| 208 | |
| 209 | static uint32_t print_tco_status(uint32_t tco_sts) |
| 210 | { |
| 211 | size_t array_size; |
| 212 | const char *const *tco_arr; |
| 213 | |
| 214 | if (!tco_sts) |
| 215 | return 0; |
| 216 | |
| 217 | printk(BIOS_DEBUG, "TCO_STS: "); |
| 218 | |
| 219 | tco_arr = soc_tco_sts_array(&array_size); |
| 220 | |
| 221 | print_num_status_bits(array_size, tco_sts, tco_arr); |
| 222 | printk(BIOS_DEBUG, "\n"); |
| 223 | |
| 224 | return tco_sts; |
| 225 | } |
| 226 | |
| 227 | uint32_t pmc_clear_tco_status(void) |
| 228 | { |
| 229 | return print_tco_status(soc_reset_tco_status()); |
| 230 | } |
| 231 | |
| 232 | /* GPE */ |
| 233 | void pmc_enable_gpe(uint32_t mask) |
| 234 | { |
| 235 | uint32_t gpe0a_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD)); |
| 236 | gpe0a_en |= mask; |
| 237 | outl(gpe0a_en, ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD)); |
| 238 | } |
| 239 | |
| 240 | void pmc_disable_gpe(uint32_t mask) |
| 241 | { |
| 242 | uint32_t gpe0a_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD)); |
| 243 | gpe0a_en &= ~mask; |
| 244 | outl(gpe0a_en, ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD)); |
| 245 | } |
| 246 | |
| 247 | void pmc_disable_all_gpe(void) |
| 248 | { |
| 249 | pmc_disable_gpe(~0); |
| 250 | } |
| 251 | |
| 252 | /* Clear the gpio gpe0 status bits in ACPI registers */ |
| 253 | void pmc_clear_gpi_gpe_sts(void) |
| 254 | { |
| 255 | int i; |
| 256 | |
| 257 | for (i = 0; i < GPE0_REG_MAX; i++) { |
| 258 | /* This is reserved GPE block and specific to chipset */ |
| 259 | if (i == GPE_STD) |
| 260 | continue; |
| 261 | uint32_t gpe_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(i)); |
| 262 | outl(gpe_sts, ACPI_BASE_ADDRESS + GPE0_STS(i)); |
| 263 | } |
| 264 | } |
| 265 | |
| 266 | static uint32_t reset_gpe_status(void) |
| 267 | { |
| 268 | uint32_t gpe_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(GPE_STD)); |
| 269 | outl(gpe_sts, ACPI_BASE_ADDRESS + GPE0_STS(GPE_STD)); |
| 270 | return gpe_sts; |
| 271 | } |
| 272 | |
| 273 | static uint32_t print_gpe_sts(uint32_t gpe_sts) |
| 274 | { |
| 275 | size_t array_size; |
| 276 | const char *const *sts_arr; |
| 277 | |
| 278 | if (!gpe_sts) |
| 279 | return gpe_sts; |
| 280 | |
| 281 | printk(BIOS_DEBUG, "GPE0a_STS: "); |
| 282 | |
| 283 | sts_arr = soc_gpe_sts_array(&array_size); |
| 284 | print_num_status_bits(array_size, gpe_sts, sts_arr); |
| 285 | printk(BIOS_DEBUG, "\n"); |
| 286 | |
| 287 | return gpe_sts; |
| 288 | } |
| 289 | |
| 290 | uint32_t pmc_clear_gpe_status(void) |
| 291 | { |
| 292 | return print_gpe_sts(reset_gpe_status()); |
| 293 | } |
| 294 | |
| 295 | __attribute__ ((weak)) |
| 296 | void soc_clear_pm_registers(uintptr_t pmc_bar) |
| 297 | { |
| 298 | } |
| 299 | |
| 300 | void pmc_clear_status(void) |
| 301 | { |
| 302 | uint32_t prsts; |
| 303 | uintptr_t pmc_bar; |
| 304 | |
| 305 | /* Read PMC base address from soc */ |
| 306 | pmc_bar = soc_read_pmc_base(); |
| 307 | |
| 308 | prsts = read32((void *)(pmc_bar + PRSTS)); |
| 309 | write32((void *)(pmc_bar + PRSTS), prsts); |
| 310 | |
| 311 | soc_clear_pm_registers(pmc_bar); |
| 312 | } |
| 313 | |
| 314 | __attribute__ ((weak)) |
| 315 | int soc_prev_sleep_state(const struct chipset_power_state *ps, |
| 316 | int prev_sleep_state) |
| 317 | { |
| 318 | return prev_sleep_state; |
| 319 | } |
| 320 | |
| 321 | /* |
| 322 | * Returns prev_sleep_state and also prints all power management registers. |
| 323 | * Calls soc_prev_sleep_state which may be impelmented by SOC. |
| 324 | */ |
| 325 | static int pmc_prev_sleep_state(const struct chipset_power_state *ps) |
| 326 | { |
| 327 | /* Default to S0. */ |
| 328 | int prev_sleep_state = ACPI_S0; |
| 329 | |
| 330 | if (ps->pm1_sts & WAK_STS) { |
| 331 | switch (acpi_sleep_from_pm1(ps->pm1_cnt)) { |
| 332 | case ACPI_S3: |
| 333 | if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) |
| 334 | prev_sleep_state = ACPI_S3; |
| 335 | break; |
| 336 | case ACPI_S5: |
| 337 | prev_sleep_state = ACPI_S5; |
| 338 | break; |
| 339 | } |
| 340 | |
| 341 | /* Clear SLP_TYP. */ |
| 342 | outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); |
| 343 | } |
| 344 | return soc_prev_sleep_state(ps, prev_sleep_state); |
| 345 | } |
| 346 | |
| 347 | /* |
| 348 | * This function re-writes the gpe0 register values in power state |
| 349 | * cbmem variable. After system wakes from sleep state internal PMC logic |
| 350 | * writes default values in GPE_CFG register which gives a wrong offset to |
| 351 | * calculate the wake reason. So we need to set it again to the routing |
| 352 | * table as per the devicetree. |
| 353 | */ |
| 354 | void pmc_fixup_power_state(void) |
| 355 | { |
| 356 | int i; |
| 357 | struct chipset_power_state *ps; |
| 358 | |
Shaunak Saha | f073872 | 2017-10-02 15:01:33 -0700 | [diff] [blame^] | 359 | ps = pmc_get_power_state(); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 360 | if (ps == NULL) |
| 361 | return; |
| 362 | |
| 363 | for (i = 0; i < GPE0_REG_MAX; i++) { |
| 364 | ps->gpe0_sts[i] = inl(ACPI_BASE_ADDRESS + GPE0_STS(i)); |
| 365 | ps->gpe0_en[i] = inl(ACPI_BASE_ADDRESS + GPE0_EN(i)); |
| 366 | printk(BIOS_DEBUG, "gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n", |
| 367 | i, ps->gpe0_sts[i], i, ps->gpe0_en[i]); |
| 368 | } |
| 369 | } |
| 370 | |
| 371 | /* Reads and prints ACPI specific PM registers */ |
| 372 | int pmc_fill_power_state(struct chipset_power_state *ps) |
| 373 | { |
| 374 | int i; |
| 375 | |
| 376 | ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); |
| 377 | ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN); |
| 378 | ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); |
| 379 | |
| 380 | printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n", |
| 381 | ps->pm1_sts, ps->pm1_en, ps->pm1_cnt); |
| 382 | |
| 383 | for (i = 0; i < GPE0_REG_MAX; i++) { |
| 384 | ps->gpe0_sts[i] = inl(ACPI_BASE_ADDRESS + GPE0_STS(i)); |
| 385 | ps->gpe0_en[i] = inl(ACPI_BASE_ADDRESS + GPE0_EN(i)); |
| 386 | printk(BIOS_DEBUG, "gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n", |
| 387 | i, ps->gpe0_sts[i], i, ps->gpe0_en[i]); |
| 388 | } |
| 389 | |
| 390 | soc_fill_power_state(ps); |
| 391 | |
| 392 | ps->prev_sleep_state = pmc_prev_sleep_state(ps); |
| 393 | printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); |
| 394 | |
| 395 | return ps->prev_sleep_state; |
| 396 | } |
| 397 | |
| 398 | /* |
| 399 | * If possible, lock 0xcf9. Once the register is locked, it can't be changed. |
| 400 | * This lock is reset on cold boot, hard reset, soft reset and Sx. |
| 401 | */ |
| 402 | void pmc_global_reset_lock(void) |
| 403 | { |
| 404 | /* Read PMC base address from soc */ |
| 405 | uintptr_t etr = soc_read_pmc_base() + ETR; |
| 406 | uint32_t reg; |
| 407 | |
| 408 | reg = read32((void *)etr); |
| 409 | if (reg & CF9_LOCK) |
| 410 | return; |
| 411 | reg |= CF9_LOCK; |
| 412 | write32((void *)etr, reg); |
| 413 | } |
| 414 | |
| 415 | /* |
| 416 | * Enable or disable global reset. If global reset is enabled, hard reset and |
| 417 | * soft reset will trigger global reset, where both host and TXE are reset. |
| 418 | * This is cleared on cold boot, hard reset, soft reset and Sx. |
| 419 | */ |
| 420 | void pmc_global_reset_enable(bool enable) |
| 421 | { |
| 422 | /* Read PMC base address from soc */ |
| 423 | uintptr_t etr = soc_read_pmc_base() + ETR; |
| 424 | uint32_t reg; |
| 425 | |
| 426 | reg = read32((void *)etr); |
| 427 | reg = enable ? reg | CF9_GLB_RST : reg & ~CF9_GLB_RST; |
| 428 | write32((void *)etr, reg); |
| 429 | } |
| 430 | |
| 431 | int vboot_platform_is_resuming(void) |
| 432 | { |
| 433 | if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS)) |
| 434 | return 0; |
| 435 | |
| 436 | return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3; |
| 437 | } |
| 438 | |
| 439 | /* Read and clear GPE status (defined in arch/acpi.h) */ |
| 440 | int acpi_get_gpe(int gpe) |
| 441 | { |
| 442 | int bank; |
| 443 | uint32_t mask, sts; |
| 444 | struct stopwatch sw; |
| 445 | int rc = 0; |
| 446 | |
| 447 | if (gpe < 0 || gpe > GPE_MAX) |
| 448 | return -1; |
| 449 | |
| 450 | bank = gpe / 32; |
| 451 | mask = 1 << (gpe % 32); |
| 452 | |
| 453 | /* Wait up to 1ms for GPE status to clear */ |
| 454 | stopwatch_init_msecs_expire(&sw, 1); |
| 455 | do { |
| 456 | if (stopwatch_expired(&sw)) |
| 457 | return rc; |
| 458 | |
| 459 | sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(bank)); |
| 460 | if (sts & mask) { |
| 461 | outl(mask, ACPI_BASE_ADDRESS + GPE0_STS(bank)); |
| 462 | rc = 1; |
| 463 | } |
| 464 | } while (sts & mask); |
| 465 | |
| 466 | return rc; |
| 467 | } |
| 468 | |
| 469 | /* |
| 470 | * The PM1 control is set to S5 when vboot requests a reboot because the power |
| 471 | * state code above may not have collected its data yet. Therefore, set it to |
| 472 | * S5 when vboot requests a reboot. That's necessary if vboot fails in the |
| 473 | * resume path and requests a reboot. This prevents a reboot loop where the |
| 474 | * error is continually hit on the failing vboot resume path. |
| 475 | */ |
| 476 | void vboot_platform_prepare_reboot(void) |
| 477 | { |
| 478 | const uint16_t port = ACPI_BASE_ADDRESS + PM1_CNT; |
| 479 | outl((inl(port) & ~(SLP_TYP)) | (SLP_TYP_S5 << SLP_TYP_SHIFT), port); |
| 480 | } |
| 481 | |
| 482 | void poweroff(void) |
| 483 | { |
| 484 | pmc_enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); |
| 485 | |
| 486 | /* |
| 487 | * Setting SLP_TYP_S5 in PM1 triggers SLP_SMI, which is handled by SMM |
| 488 | * to transition to S5 state. If halt is called in SMM, then it prevents |
| 489 | * the SMI handler from being triggered and system never enters S5. |
| 490 | */ |
| 491 | if (!ENV_SMM) |
| 492 | halt(); |
| 493 | } |
| 494 | |
| 495 | void pmc_gpe_init(void) |
| 496 | { |
| 497 | uint32_t gpio_cfg = 0; |
| 498 | uint32_t gpio_cfg_reg; |
| 499 | uint8_t dw0, dw1, dw2; |
| 500 | |
| 501 | /* Read PMC base address from soc. This is implemented in soc */ |
| 502 | uintptr_t pmc_bar = soc_read_pmc_base(); |
| 503 | |
| 504 | /* |
| 505 | * Get the dwX values for pmc gpe settings. |
| 506 | */ |
| 507 | soc_get_gpe_configs(&dw0, &dw1, &dw2); |
| 508 | |
| 509 | const uint32_t gpio_cfg_mask = |
| 510 | (GPE0_DWX_MASK << GPE0_DW_SHIFT(0)) | |
| 511 | (GPE0_DWX_MASK << GPE0_DW_SHIFT(1)) | |
| 512 | (GPE0_DWX_MASK << GPE0_DW_SHIFT(2)); |
| 513 | |
| 514 | /* Making sure that bad values don't bleed into the other fields */ |
| 515 | dw0 &= GPE0_DWX_MASK; |
| 516 | dw1 &= GPE0_DWX_MASK; |
| 517 | dw2 &= GPE0_DWX_MASK; |
| 518 | |
| 519 | /* |
| 520 | * Route the GPIOs to the GPE0 block. Determine that all values |
| 521 | * are different, and if they aren't use the reset values. |
| 522 | */ |
| 523 | if (dw0 == dw1 || dw1 == dw2) { |
| 524 | printk(BIOS_INFO, "PMC: Using default GPE route.\n"); |
| 525 | gpio_cfg = read32((void *)pmc_bar + GPIO_GPE_CFG); |
| 526 | |
| 527 | dw0 = (gpio_cfg >> GPE0_DW_SHIFT(0)) & GPE0_DWX_MASK; |
| 528 | dw1 = (gpio_cfg >> GPE0_DW_SHIFT(1)) & GPE0_DWX_MASK; |
| 529 | dw2 = (gpio_cfg >> GPE0_DW_SHIFT(2)) & GPE0_DWX_MASK; |
| 530 | } else { |
| 531 | gpio_cfg |= (uint32_t) dw0 << GPE0_DW_SHIFT(0); |
| 532 | gpio_cfg |= (uint32_t) dw1 << GPE0_DW_SHIFT(1); |
| 533 | gpio_cfg |= (uint32_t) dw2 << GPE0_DW_SHIFT(2); |
| 534 | } |
| 535 | |
| 536 | gpio_cfg_reg = read32((void *)pmc_bar + GPIO_GPE_CFG) & ~gpio_cfg_mask; |
| 537 | gpio_cfg_reg |= gpio_cfg & gpio_cfg_mask; |
| 538 | |
| 539 | write32((void *)pmc_bar + GPIO_GPE_CFG, gpio_cfg_reg); |
| 540 | |
| 541 | /* Set the routes in the GPIO communities as well. */ |
| 542 | gpio_route_gpe(dw0, dw1, dw2); |
| 543 | } |