commit ab6201835acb26c00f2975f9bad35c6024e3a0bf
author Furquan Shaikh <furquan@chromium.org> Mon Oct 16 22:19:13 2017 -0700
committer Furquan Shaikh <furquan@google.com> Thu Oct 19 00:42:58 2017 +0000
tree ff88e167168614f28042814e985d1748fa964906
parent e48fb54b161f306966a9d878ab6d103554b2264a

soc/intel/common/block/pmc: Add helper routines to read/write PM1_CNT

This change adds and uses helper routines for reading and writing
PM1_CNT register.

BUG=b:67874513

Change-Id: I69b9347ab54a392b67ba733eb00922583dc1ee5f
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22081
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

src/soc/intel/common/block/pmc/pmclib.c

diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c
index c2a6bef..82ce292 100644
--- a/src/soc/intel/common/block/pmc/pmclib.c
+++ b/src/soc/intel/common/block/pmc/pmclib.c
@@ -155,18 +155,28 @@
 	outw(events, ACPI_BASE_ADDRESS + PM1_EN);
 }
 
+uint32_t pmc_read_pm1_control(void)
+{
+	return inl(ACPI_BASE_ADDRESS + PM1_CNT);
+}
+
+void pmc_write_pm1_control(uint32_t pm1_cnt)
+{
+	outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
+}
+
 void pmc_enable_pm1_control(uint32_t mask)
 {
-	uint32_t pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
+	uint32_t pm1_cnt = pmc_read_pm1_control();
 	pm1_cnt |= mask;
-	outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
+	pmc_write_pm1_control(pm1_cnt);
 }
 
 void pmc_disable_pm1_control(uint32_t mask)
 {
-	uint32_t pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
+	uint32_t pm1_cnt = pmc_read_pm1_control();
 	pm1_cnt &= ~mask;
-	outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
+	pmc_write_pm1_control(pm1_cnt);
 }
 
 static uint16_t reset_pm1_status(void)
@@ -357,7 +367,7 @@
 		}
 
 		/* Clear SLP_TYP. */
-		outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
+		pmc_write_pm1_control(ps->pm1_cnt & ~(SLP_TYP));
 	}
 	return soc_prev_sleep_state(ps, prev_sleep_state);
 }
@@ -394,7 +404,7 @@
 
 	ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
 	ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN);
-	ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
+	ps->pm1_cnt = pmc_read_pm1_control();
 
 	printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n",
 	       ps->pm1_sts, ps->pm1_en, ps->pm1_cnt);
@@ -470,7 +480,7 @@
 	if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS))
 		return 0;
 
-	return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3;
+	return acpi_sleep_from_pm1(pmc_read_pm1_control()) == ACPI_S3;
 }
 
 /* Read and clear GPE status (defined in arch/acpi.h) */
@@ -512,8 +522,10 @@
  */
 void vboot_platform_prepare_reboot(void)
 {
-	const uint16_t port = ACPI_BASE_ADDRESS + PM1_CNT;
-	outl((inl(port) & ~(SLP_TYP)) | (SLP_TYP_S5 << SLP_TYP_SHIFT), port);
+	uint32_t pm1_cnt;
+	pm1_cnt = (pmc_read_pm1_control() & ~(SLP_TYP)) |
+		(SLP_TYP_S5 << SLP_TYP_SHIFT);
+	pmc_write_pm1_control(pm1_cnt);
 }
 
 void poweroff(void)