Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2017 Intel Corporation. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
Shaunak Saha | f073872 | 2017-10-02 15:01:33 -0700 | [diff] [blame] | 16 | #include <arch/early_variables.h> |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 17 | #include <arch/io.h> |
| 18 | #include <cbmem.h> |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame^] | 19 | #include <compiler.h> |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 20 | #include <console/console.h> |
| 21 | #include <halt.h> |
| 22 | #include <intelblocks/pmclib.h> |
| 23 | #include <intelblocks/gpio.h> |
| 24 | #include <soc/pm.h> |
Shaunak Saha | f073872 | 2017-10-02 15:01:33 -0700 | [diff] [blame] | 25 | #include <string.h> |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 26 | #include <timer.h> |
Philipp Deppenwiese | fea2429 | 2017-10-17 17:02:29 +0200 | [diff] [blame] | 27 | #include <security/vboot/vboot_common.h> |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 28 | |
Shaunak Saha | f073872 | 2017-10-02 15:01:33 -0700 | [diff] [blame] | 29 | static struct chipset_power_state power_state CAR_GLOBAL; |
| 30 | |
| 31 | struct chipset_power_state *pmc_get_power_state(void) |
| 32 | { |
| 33 | struct chipset_power_state *ptr = NULL; |
| 34 | |
| 35 | if (cbmem_possibly_online()) |
| 36 | ptr = cbmem_find(CBMEM_ID_POWER_STATE); |
| 37 | |
| 38 | /* cbmem is online but ptr is not populated yet */ |
| 39 | if (ptr == NULL && !(ENV_RAMSTAGE || ENV_POSTCAR)) |
| 40 | return car_get_var_ptr(&power_state); |
| 41 | |
| 42 | return ptr; |
| 43 | } |
| 44 | |
| 45 | static void migrate_power_state(int is_recovery) |
| 46 | { |
| 47 | struct chipset_power_state *ps_cbmem; |
| 48 | struct chipset_power_state *ps_car; |
| 49 | |
| 50 | ps_car = car_get_var_ptr(&power_state); |
| 51 | ps_cbmem = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*ps_cbmem)); |
| 52 | |
| 53 | if (ps_cbmem == NULL) { |
| 54 | printk(BIOS_DEBUG, "Not adding power state to cbmem!\n"); |
| 55 | return; |
| 56 | } |
| 57 | memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem)); |
| 58 | } |
| 59 | ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state) |
| 60 | |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 61 | static void print_num_status_bits(int num_bits, uint32_t status, |
| 62 | const char *const bit_names[]) |
| 63 | { |
| 64 | int i; |
| 65 | |
| 66 | if (!status) |
| 67 | return; |
| 68 | |
| 69 | for (i = num_bits - 1; i >= 0; i--) { |
| 70 | if (status & (1 << i)) { |
| 71 | if (bit_names[i]) |
| 72 | printk(BIOS_DEBUG, "%s ", bit_names[i]); |
| 73 | else |
| 74 | printk(BIOS_DEBUG, "BIT%d ", i); |
| 75 | } |
| 76 | } |
| 77 | } |
| 78 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame^] | 79 | __weak uint32_t soc_get_smi_status(uint32_t generic_sts) |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 80 | { |
| 81 | return generic_sts; |
| 82 | } |
| 83 | |
Subrata Banik | 9b98feb | 2017-12-13 11:02:43 +0530 | [diff] [blame] | 84 | /* |
| 85 | * Set PMC register to know which state system should be after |
| 86 | * power reapplied |
| 87 | */ |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame^] | 88 | __weak void pmc_soc_restore_power_failure(void) |
Subrata Banik | 9b98feb | 2017-12-13 11:02:43 +0530 | [diff] [blame] | 89 | { |
| 90 | /* |
| 91 | * SoC code should set PMC config register in order to set |
| 92 | * MAINBOARD_POWER_ON bit as per EDS. |
| 93 | */ |
| 94 | } |
| 95 | |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 96 | static uint32_t pmc_reset_smi_status(void) |
| 97 | { |
| 98 | uint32_t smi_sts = inl(ACPI_BASE_ADDRESS + SMI_STS); |
| 99 | outl(smi_sts, ACPI_BASE_ADDRESS + SMI_STS); |
| 100 | |
| 101 | return soc_get_smi_status(smi_sts); |
| 102 | } |
| 103 | |
| 104 | static uint32_t print_smi_status(uint32_t smi_sts) |
| 105 | { |
| 106 | size_t array_size; |
| 107 | const char *const *smi_arr; |
| 108 | |
| 109 | if (!smi_sts) |
| 110 | return 0; |
| 111 | |
| 112 | printk(BIOS_DEBUG, "SMI_STS: "); |
| 113 | |
| 114 | smi_arr = soc_smi_sts_array(&array_size); |
| 115 | |
| 116 | print_num_status_bits(array_size, smi_sts, smi_arr); |
| 117 | printk(BIOS_DEBUG, "\n"); |
| 118 | |
| 119 | return smi_sts; |
| 120 | } |
| 121 | |
Shaunak Saha | 25cc76f | 2017-09-28 15:13:05 -0700 | [diff] [blame] | 122 | /* |
| 123 | * Update supplied events in PM1_EN register. This does not disable any already |
| 124 | * set events. |
| 125 | */ |
| 126 | void pmc_update_pm1_enable(u16 events) |
| 127 | { |
| 128 | u16 pm1_en = pmc_read_pm1_enable(); |
| 129 | pm1_en |= events; |
| 130 | pmc_enable_pm1(pm1_en); |
| 131 | } |
| 132 | |
| 133 | /* Read events set in PM1_EN register. */ |
| 134 | uint16_t pmc_read_pm1_enable(void) |
| 135 | { |
| 136 | return inw(ACPI_BASE_ADDRESS + PM1_EN); |
| 137 | } |
| 138 | |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 139 | uint32_t pmc_clear_smi_status(void) |
| 140 | { |
| 141 | uint32_t sts = pmc_reset_smi_status(); |
| 142 | |
| 143 | return print_smi_status(sts); |
| 144 | } |
| 145 | |
| 146 | uint32_t pmc_get_smi_en(void) |
| 147 | { |
| 148 | return inl(ACPI_BASE_ADDRESS + SMI_EN); |
| 149 | } |
| 150 | |
| 151 | void pmc_enable_smi(uint32_t mask) |
| 152 | { |
| 153 | uint32_t smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN); |
| 154 | smi_en |= mask; |
| 155 | outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN); |
| 156 | } |
| 157 | |
| 158 | void pmc_disable_smi(uint32_t mask) |
| 159 | { |
| 160 | uint32_t smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN); |
| 161 | smi_en &= ~mask; |
| 162 | outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN); |
| 163 | } |
| 164 | |
| 165 | /* PM1 */ |
| 166 | void pmc_enable_pm1(uint16_t events) |
| 167 | { |
| 168 | outw(events, ACPI_BASE_ADDRESS + PM1_EN); |
| 169 | } |
| 170 | |
Furquan Shaikh | ab62018 | 2017-10-16 22:19:13 -0700 | [diff] [blame] | 171 | uint32_t pmc_read_pm1_control(void) |
| 172 | { |
| 173 | return inl(ACPI_BASE_ADDRESS + PM1_CNT); |
| 174 | } |
| 175 | |
| 176 | void pmc_write_pm1_control(uint32_t pm1_cnt) |
| 177 | { |
| 178 | outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT); |
| 179 | } |
| 180 | |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 181 | void pmc_enable_pm1_control(uint32_t mask) |
| 182 | { |
Furquan Shaikh | ab62018 | 2017-10-16 22:19:13 -0700 | [diff] [blame] | 183 | uint32_t pm1_cnt = pmc_read_pm1_control(); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 184 | pm1_cnt |= mask; |
Furquan Shaikh | ab62018 | 2017-10-16 22:19:13 -0700 | [diff] [blame] | 185 | pmc_write_pm1_control(pm1_cnt); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 186 | } |
| 187 | |
| 188 | void pmc_disable_pm1_control(uint32_t mask) |
| 189 | { |
Furquan Shaikh | ab62018 | 2017-10-16 22:19:13 -0700 | [diff] [blame] | 190 | uint32_t pm1_cnt = pmc_read_pm1_control(); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 191 | pm1_cnt &= ~mask; |
Furquan Shaikh | ab62018 | 2017-10-16 22:19:13 -0700 | [diff] [blame] | 192 | pmc_write_pm1_control(pm1_cnt); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 193 | } |
| 194 | |
| 195 | static uint16_t reset_pm1_status(void) |
| 196 | { |
| 197 | uint16_t pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); |
| 198 | outw(pm1_sts, ACPI_BASE_ADDRESS + PM1_STS); |
| 199 | return pm1_sts; |
| 200 | } |
| 201 | |
| 202 | static uint16_t print_pm1_status(uint16_t pm1_sts) |
| 203 | { |
| 204 | static const char *const pm1_sts_bits[] = { |
| 205 | [0] = "TMROF", |
| 206 | [5] = "GBL", |
| 207 | [8] = "PWRBTN", |
| 208 | [10] = "RTC", |
| 209 | [11] = "PRBTNOR", |
| 210 | [13] = "USB", |
| 211 | [14] = "PCIEXPWAK", |
| 212 | [15] = "WAK", |
| 213 | }; |
| 214 | |
| 215 | if (!pm1_sts) |
| 216 | return 0; |
| 217 | |
| 218 | printk(BIOS_SPEW, "PM1_STS: "); |
| 219 | print_num_status_bits(ARRAY_SIZE(pm1_sts_bits), pm1_sts, pm1_sts_bits); |
| 220 | printk(BIOS_SPEW, "\n"); |
| 221 | |
| 222 | return pm1_sts; |
| 223 | } |
| 224 | |
| 225 | uint16_t pmc_clear_pm1_status(void) |
| 226 | { |
| 227 | return print_pm1_status(reset_pm1_status()); |
| 228 | } |
| 229 | |
| 230 | /* TCO */ |
| 231 | |
| 232 | static uint32_t print_tco_status(uint32_t tco_sts) |
| 233 | { |
| 234 | size_t array_size; |
| 235 | const char *const *tco_arr; |
| 236 | |
| 237 | if (!tco_sts) |
| 238 | return 0; |
| 239 | |
| 240 | printk(BIOS_DEBUG, "TCO_STS: "); |
| 241 | |
| 242 | tco_arr = soc_tco_sts_array(&array_size); |
| 243 | |
| 244 | print_num_status_bits(array_size, tco_sts, tco_arr); |
| 245 | printk(BIOS_DEBUG, "\n"); |
| 246 | |
| 247 | return tco_sts; |
| 248 | } |
| 249 | |
| 250 | uint32_t pmc_clear_tco_status(void) |
| 251 | { |
| 252 | return print_tco_status(soc_reset_tco_status()); |
| 253 | } |
| 254 | |
| 255 | /* GPE */ |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 256 | static void pmc_enable_gpe(int gpe, uint32_t mask) |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 257 | { |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 258 | uint32_t gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(gpe)); |
| 259 | gpe0_en |= mask; |
| 260 | outl(gpe0_en, ACPI_BASE_ADDRESS + GPE0_EN(gpe)); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 261 | } |
| 262 | |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 263 | static void pmc_disable_gpe(int gpe, uint32_t mask) |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 264 | { |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 265 | uint32_t gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(gpe)); |
| 266 | gpe0_en &= ~mask; |
| 267 | outl(gpe0_en, ACPI_BASE_ADDRESS + GPE0_EN(gpe)); |
| 268 | } |
| 269 | |
| 270 | void pmc_enable_std_gpe(uint32_t mask) |
| 271 | { |
| 272 | pmc_enable_gpe(GPE_STD, mask); |
| 273 | } |
| 274 | |
| 275 | void pmc_disable_std_gpe(uint32_t mask) |
| 276 | { |
| 277 | pmc_disable_gpe(GPE_STD, mask); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 278 | } |
| 279 | |
| 280 | void pmc_disable_all_gpe(void) |
| 281 | { |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 282 | int i; |
| 283 | for (i = 0; i < GPE0_REG_MAX; i++) |
| 284 | pmc_disable_gpe(i, ~0); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 285 | } |
| 286 | |
| 287 | /* Clear the gpio gpe0 status bits in ACPI registers */ |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 288 | static void pmc_clear_gpi_gpe_status(void) |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 289 | { |
| 290 | int i; |
| 291 | |
| 292 | for (i = 0; i < GPE0_REG_MAX; i++) { |
| 293 | /* This is reserved GPE block and specific to chipset */ |
| 294 | if (i == GPE_STD) |
| 295 | continue; |
| 296 | uint32_t gpe_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(i)); |
| 297 | outl(gpe_sts, ACPI_BASE_ADDRESS + GPE0_STS(i)); |
| 298 | } |
| 299 | } |
| 300 | |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 301 | static uint32_t reset_std_gpe_status(void) |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 302 | { |
| 303 | uint32_t gpe_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(GPE_STD)); |
| 304 | outl(gpe_sts, ACPI_BASE_ADDRESS + GPE0_STS(GPE_STD)); |
| 305 | return gpe_sts; |
| 306 | } |
| 307 | |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 308 | static uint32_t print_std_gpe_sts(uint32_t gpe_sts) |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 309 | { |
| 310 | size_t array_size; |
| 311 | const char *const *sts_arr; |
| 312 | |
| 313 | if (!gpe_sts) |
| 314 | return gpe_sts; |
| 315 | |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 316 | printk(BIOS_DEBUG, "GPE0 STD STS: "); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 317 | |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 318 | sts_arr = soc_std_gpe_sts_array(&array_size); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 319 | print_num_status_bits(array_size, gpe_sts, sts_arr); |
| 320 | printk(BIOS_DEBUG, "\n"); |
| 321 | |
| 322 | return gpe_sts; |
| 323 | } |
| 324 | |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 325 | static void pmc_clear_std_gpe_status(void) |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 326 | { |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 327 | print_std_gpe_sts(reset_std_gpe_status()); |
| 328 | } |
| 329 | |
| 330 | void pmc_clear_all_gpe_status(void) |
| 331 | { |
| 332 | pmc_clear_std_gpe_status(); |
| 333 | pmc_clear_gpi_gpe_status(); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 334 | } |
| 335 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame^] | 336 | __weak |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 337 | void soc_clear_pm_registers(uintptr_t pmc_bar) |
| 338 | { |
| 339 | } |
| 340 | |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 341 | void pmc_clear_prsts(void) |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 342 | { |
| 343 | uint32_t prsts; |
| 344 | uintptr_t pmc_bar; |
| 345 | |
| 346 | /* Read PMC base address from soc */ |
| 347 | pmc_bar = soc_read_pmc_base(); |
| 348 | |
| 349 | prsts = read32((void *)(pmc_bar + PRSTS)); |
| 350 | write32((void *)(pmc_bar + PRSTS), prsts); |
| 351 | |
| 352 | soc_clear_pm_registers(pmc_bar); |
| 353 | } |
| 354 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame^] | 355 | __weak |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 356 | int soc_prev_sleep_state(const struct chipset_power_state *ps, |
| 357 | int prev_sleep_state) |
| 358 | { |
| 359 | return prev_sleep_state; |
| 360 | } |
| 361 | |
| 362 | /* |
| 363 | * Returns prev_sleep_state and also prints all power management registers. |
Jonathan Neuschäfer | 5268b76 | 2018-02-12 12:24:25 +0100 | [diff] [blame] | 364 | * Calls soc_prev_sleep_state which may be implemented by SOC. |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 365 | */ |
| 366 | static int pmc_prev_sleep_state(const struct chipset_power_state *ps) |
| 367 | { |
| 368 | /* Default to S0. */ |
| 369 | int prev_sleep_state = ACPI_S0; |
| 370 | |
| 371 | if (ps->pm1_sts & WAK_STS) { |
| 372 | switch (acpi_sleep_from_pm1(ps->pm1_cnt)) { |
| 373 | case ACPI_S3: |
| 374 | if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) |
| 375 | prev_sleep_state = ACPI_S3; |
| 376 | break; |
| 377 | case ACPI_S5: |
| 378 | prev_sleep_state = ACPI_S5; |
| 379 | break; |
| 380 | } |
| 381 | |
| 382 | /* Clear SLP_TYP. */ |
Furquan Shaikh | ab62018 | 2017-10-16 22:19:13 -0700 | [diff] [blame] | 383 | pmc_write_pm1_control(ps->pm1_cnt & ~(SLP_TYP)); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 384 | } |
| 385 | return soc_prev_sleep_state(ps, prev_sleep_state); |
| 386 | } |
| 387 | |
| 388 | /* |
| 389 | * This function re-writes the gpe0 register values in power state |
| 390 | * cbmem variable. After system wakes from sleep state internal PMC logic |
| 391 | * writes default values in GPE_CFG register which gives a wrong offset to |
| 392 | * calculate the wake reason. So we need to set it again to the routing |
| 393 | * table as per the devicetree. |
| 394 | */ |
| 395 | void pmc_fixup_power_state(void) |
| 396 | { |
| 397 | int i; |
| 398 | struct chipset_power_state *ps; |
| 399 | |
Shaunak Saha | f073872 | 2017-10-02 15:01:33 -0700 | [diff] [blame] | 400 | ps = pmc_get_power_state(); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 401 | if (ps == NULL) |
| 402 | return; |
| 403 | |
| 404 | for (i = 0; i < GPE0_REG_MAX; i++) { |
| 405 | ps->gpe0_sts[i] = inl(ACPI_BASE_ADDRESS + GPE0_STS(i)); |
| 406 | ps->gpe0_en[i] = inl(ACPI_BASE_ADDRESS + GPE0_EN(i)); |
| 407 | printk(BIOS_DEBUG, "gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n", |
| 408 | i, ps->gpe0_sts[i], i, ps->gpe0_en[i]); |
| 409 | } |
| 410 | } |
| 411 | |
Furquan Shaikh | e48fb54 | 2017-10-17 16:00:10 -0700 | [diff] [blame] | 412 | void pmc_fill_pm_reg_info(struct chipset_power_state *ps) |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 413 | { |
| 414 | int i; |
| 415 | |
Furquan Shaikh | e48fb54 | 2017-10-17 16:00:10 -0700 | [diff] [blame] | 416 | memset(ps, 0, sizeof(*ps)); |
| 417 | |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 418 | ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); |
| 419 | ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN); |
Furquan Shaikh | ab62018 | 2017-10-16 22:19:13 -0700 | [diff] [blame] | 420 | ps->pm1_cnt = pmc_read_pm1_control(); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 421 | |
| 422 | printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n", |
| 423 | ps->pm1_sts, ps->pm1_en, ps->pm1_cnt); |
| 424 | |
| 425 | for (i = 0; i < GPE0_REG_MAX; i++) { |
| 426 | ps->gpe0_sts[i] = inl(ACPI_BASE_ADDRESS + GPE0_STS(i)); |
| 427 | ps->gpe0_en[i] = inl(ACPI_BASE_ADDRESS + GPE0_EN(i)); |
| 428 | printk(BIOS_DEBUG, "gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n", |
| 429 | i, ps->gpe0_sts[i], i, ps->gpe0_en[i]); |
| 430 | } |
| 431 | |
| 432 | soc_fill_power_state(ps); |
Furquan Shaikh | e48fb54 | 2017-10-17 16:00:10 -0700 | [diff] [blame] | 433 | } |
| 434 | |
| 435 | /* Reads and prints ACPI specific PM registers */ |
| 436 | int pmc_fill_power_state(struct chipset_power_state *ps) |
| 437 | { |
| 438 | pmc_fill_pm_reg_info(ps); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 439 | |
| 440 | ps->prev_sleep_state = pmc_prev_sleep_state(ps); |
| 441 | printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); |
| 442 | |
Furquan Shaikh | efe1e2d | 2017-10-15 15:27:32 -0700 | [diff] [blame] | 443 | /* |
| 444 | * GPEs need to be disabled before enabling SMI. Otherwise, it could |
| 445 | * lead to SMIs being triggered in coreboot preventing the progress of |
| 446 | * normal boot-up. However, GPEs should not be disabled as part of |
| 447 | * pmc_gpe_init which happens in bootblock. Otherwise, |
| 448 | * pmc_fill_power_state would read GPE0_EN registers as all 0s thus |
| 449 | * losing information about the wake source. Hence, |
| 450 | * pmc_disable_all_gpe() is placed here after GPE0_EN registers are |
| 451 | * saved in chipset_power_state. |
| 452 | */ |
| 453 | pmc_disable_all_gpe(); |
| 454 | |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 455 | return ps->prev_sleep_state; |
| 456 | } |
| 457 | |
| 458 | /* |
| 459 | * If possible, lock 0xcf9. Once the register is locked, it can't be changed. |
| 460 | * This lock is reset on cold boot, hard reset, soft reset and Sx. |
| 461 | */ |
| 462 | void pmc_global_reset_lock(void) |
| 463 | { |
| 464 | /* Read PMC base address from soc */ |
| 465 | uintptr_t etr = soc_read_pmc_base() + ETR; |
| 466 | uint32_t reg; |
| 467 | |
| 468 | reg = read32((void *)etr); |
| 469 | if (reg & CF9_LOCK) |
| 470 | return; |
| 471 | reg |= CF9_LOCK; |
| 472 | write32((void *)etr, reg); |
| 473 | } |
| 474 | |
| 475 | /* |
| 476 | * Enable or disable global reset. If global reset is enabled, hard reset and |
| 477 | * soft reset will trigger global reset, where both host and TXE are reset. |
| 478 | * This is cleared on cold boot, hard reset, soft reset and Sx. |
| 479 | */ |
| 480 | void pmc_global_reset_enable(bool enable) |
| 481 | { |
| 482 | /* Read PMC base address from soc */ |
| 483 | uintptr_t etr = soc_read_pmc_base() + ETR; |
| 484 | uint32_t reg; |
| 485 | |
| 486 | reg = read32((void *)etr); |
| 487 | reg = enable ? reg | CF9_GLB_RST : reg & ~CF9_GLB_RST; |
| 488 | write32((void *)etr, reg); |
| 489 | } |
| 490 | |
| 491 | int vboot_platform_is_resuming(void) |
| 492 | { |
| 493 | if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS)) |
| 494 | return 0; |
| 495 | |
Furquan Shaikh | ab62018 | 2017-10-16 22:19:13 -0700 | [diff] [blame] | 496 | return acpi_sleep_from_pm1(pmc_read_pm1_control()) == ACPI_S3; |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 497 | } |
| 498 | |
| 499 | /* Read and clear GPE status (defined in arch/acpi.h) */ |
| 500 | int acpi_get_gpe(int gpe) |
| 501 | { |
| 502 | int bank; |
| 503 | uint32_t mask, sts; |
| 504 | struct stopwatch sw; |
| 505 | int rc = 0; |
| 506 | |
| 507 | if (gpe < 0 || gpe > GPE_MAX) |
| 508 | return -1; |
| 509 | |
| 510 | bank = gpe / 32; |
| 511 | mask = 1 << (gpe % 32); |
| 512 | |
| 513 | /* Wait up to 1ms for GPE status to clear */ |
| 514 | stopwatch_init_msecs_expire(&sw, 1); |
| 515 | do { |
| 516 | if (stopwatch_expired(&sw)) |
| 517 | return rc; |
| 518 | |
| 519 | sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(bank)); |
| 520 | if (sts & mask) { |
| 521 | outl(mask, ACPI_BASE_ADDRESS + GPE0_STS(bank)); |
| 522 | rc = 1; |
| 523 | } |
| 524 | } while (sts & mask); |
| 525 | |
| 526 | return rc; |
| 527 | } |
| 528 | |
| 529 | /* |
| 530 | * The PM1 control is set to S5 when vboot requests a reboot because the power |
| 531 | * state code above may not have collected its data yet. Therefore, set it to |
| 532 | * S5 when vboot requests a reboot. That's necessary if vboot fails in the |
| 533 | * resume path and requests a reboot. This prevents a reboot loop where the |
| 534 | * error is continually hit on the failing vboot resume path. |
| 535 | */ |
| 536 | void vboot_platform_prepare_reboot(void) |
| 537 | { |
Furquan Shaikh | ab62018 | 2017-10-16 22:19:13 -0700 | [diff] [blame] | 538 | uint32_t pm1_cnt; |
| 539 | pm1_cnt = (pmc_read_pm1_control() & ~(SLP_TYP)) | |
| 540 | (SLP_TYP_S5 << SLP_TYP_SHIFT); |
| 541 | pmc_write_pm1_control(pm1_cnt); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 542 | } |
| 543 | |
| 544 | void poweroff(void) |
| 545 | { |
| 546 | pmc_enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); |
| 547 | |
| 548 | /* |
| 549 | * Setting SLP_TYP_S5 in PM1 triggers SLP_SMI, which is handled by SMM |
| 550 | * to transition to S5 state. If halt is called in SMM, then it prevents |
| 551 | * the SMI handler from being triggered and system never enters S5. |
| 552 | */ |
| 553 | if (!ENV_SMM) |
| 554 | halt(); |
| 555 | } |
| 556 | |
| 557 | void pmc_gpe_init(void) |
| 558 | { |
| 559 | uint32_t gpio_cfg = 0; |
| 560 | uint32_t gpio_cfg_reg; |
| 561 | uint8_t dw0, dw1, dw2; |
| 562 | |
| 563 | /* Read PMC base address from soc. This is implemented in soc */ |
| 564 | uintptr_t pmc_bar = soc_read_pmc_base(); |
| 565 | |
| 566 | /* |
| 567 | * Get the dwX values for pmc gpe settings. |
| 568 | */ |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 569 | soc_get_gpi_gpe_configs(&dw0, &dw1, &dw2); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 570 | |
| 571 | const uint32_t gpio_cfg_mask = |
| 572 | (GPE0_DWX_MASK << GPE0_DW_SHIFT(0)) | |
| 573 | (GPE0_DWX_MASK << GPE0_DW_SHIFT(1)) | |
| 574 | (GPE0_DWX_MASK << GPE0_DW_SHIFT(2)); |
| 575 | |
| 576 | /* Making sure that bad values don't bleed into the other fields */ |
| 577 | dw0 &= GPE0_DWX_MASK; |
| 578 | dw1 &= GPE0_DWX_MASK; |
| 579 | dw2 &= GPE0_DWX_MASK; |
| 580 | |
| 581 | /* |
| 582 | * Route the GPIOs to the GPE0 block. Determine that all values |
| 583 | * are different, and if they aren't use the reset values. |
| 584 | */ |
| 585 | if (dw0 == dw1 || dw1 == dw2) { |
| 586 | printk(BIOS_INFO, "PMC: Using default GPE route.\n"); |
| 587 | gpio_cfg = read32((void *)pmc_bar + GPIO_GPE_CFG); |
| 588 | |
| 589 | dw0 = (gpio_cfg >> GPE0_DW_SHIFT(0)) & GPE0_DWX_MASK; |
| 590 | dw1 = (gpio_cfg >> GPE0_DW_SHIFT(1)) & GPE0_DWX_MASK; |
| 591 | dw2 = (gpio_cfg >> GPE0_DW_SHIFT(2)) & GPE0_DWX_MASK; |
| 592 | } else { |
| 593 | gpio_cfg |= (uint32_t) dw0 << GPE0_DW_SHIFT(0); |
| 594 | gpio_cfg |= (uint32_t) dw1 << GPE0_DW_SHIFT(1); |
| 595 | gpio_cfg |= (uint32_t) dw2 << GPE0_DW_SHIFT(2); |
| 596 | } |
| 597 | |
| 598 | gpio_cfg_reg = read32((void *)pmc_bar + GPIO_GPE_CFG) & ~gpio_cfg_mask; |
| 599 | gpio_cfg_reg |= gpio_cfg & gpio_cfg_mask; |
| 600 | |
| 601 | write32((void *)pmc_bar + GPIO_GPE_CFG, gpio_cfg_reg); |
| 602 | |
| 603 | /* Set the routes in the GPIO communities as well. */ |
| 604 | gpio_route_gpe(dw0, dw1, dw2); |
Shaunak Saha | 9dffbdd | 2017-03-08 19:27:17 -0800 | [diff] [blame] | 605 | } |
Subrata Banik | 9b98feb | 2017-12-13 11:02:43 +0530 | [diff] [blame] | 606 | |
| 607 | /* |
| 608 | * Determines what state to go to when power is reapplied |
| 609 | * after a power failure (G3 State) |
| 610 | */ |
| 611 | int pmc_get_mainboard_power_failure_state_choice(void) |
| 612 | { |
| 613 | if (IS_ENABLED(CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE)) |
| 614 | return MAINBOARD_POWER_STATE_PREVIOUS; |
| 615 | else if (IS_ENABLED(CONFIG_POWER_STATE_ON_AFTER_FAILURE)) |
| 616 | return MAINBOARD_POWER_STATE_ON; |
| 617 | |
| 618 | return MAINBOARD_POWER_STATE_OFF; |
| 619 | } |