Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <device/device.h> |
| 5 | #include <device/pci.h> |
| 6 | #include <device/pci_ids.h> |
Patrick Rudolph | e56189c | 2018-04-18 10:11:59 +0200 | [diff] [blame] | 7 | #include <device/pci_ops.h> |
Kyösti Mälkki | cbf9571 | 2020-01-05 08:05:45 +0200 | [diff] [blame] | 8 | #include <option.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 9 | #include <pc80/isa-dma.h> |
| 10 | #include <pc80/i8259.h> |
| 11 | #include <arch/io.h> |
| 12 | #include <arch/ioapic.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 13 | #include <acpi/acpi.h> |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 14 | #include <cpu/x86/smm.h> |
Kyösti Mälkki | 12b121c | 2019-08-18 16:33:39 +0300 | [diff] [blame] | 15 | #include "chip.h" |
Angel Pons | 2178b72 | 2020-05-31 00:55:35 +0200 | [diff] [blame] | 16 | #include "iobp.h" |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 17 | #include "pch.h" |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 18 | #include <acpi/acpigen.h> |
Tristan Corrick | f3127d4 | 2018-10-31 02:25:54 +1300 | [diff] [blame] | 19 | #include <southbridge/intel/common/acpi_pirq_gen.h> |
Tim Wawrzynczak | f62c494 | 2021-02-26 10:30:52 -0700 | [diff] [blame^] | 20 | #include <southbridge/intel/common/rcba_pirq.h> |
Patrick Rudolph | 6b93112 | 2018-11-01 17:48:37 +0100 | [diff] [blame] | 21 | #include <southbridge/intel/common/rtc.h> |
Arthur Heymans | a3121b0 | 2019-05-28 13:46:49 +0200 | [diff] [blame] | 22 | #include <southbridge/intel/common/spi.h> |
Elyes HAOUAS | 608a75c | 2021-02-12 08:09:58 +0100 | [diff] [blame] | 23 | #include <types.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 24 | |
| 25 | #define NMI_OFF 0 |
| 26 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 27 | typedef struct southbridge_intel_lynxpoint_config config_t; |
| 28 | |
Paul Menzel | 373a20c | 2013-05-03 12:17:02 +0200 | [diff] [blame] | 29 | /** |
| 30 | * Set miscellanous static southbridge features. |
| 31 | * |
| 32 | * @param dev PCI device with I/O APIC control registers |
| 33 | */ |
| 34 | static void pch_enable_ioapic(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 35 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 36 | u32 reg32; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 37 | |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 38 | /* Assign unique bus/dev/fn for I/O APIC */ |
| 39 | pci_write_config16(dev, LPC_IBDF, |
| 40 | PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3); |
| 41 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 42 | set_ioapic_id(VIO_APIC_VADDR, 0x02); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 43 | |
| 44 | /* affirm full set of redirection table entries ("write once") */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 45 | reg32 = io_apic_read(VIO_APIC_VADDR, 0x01); |
Duncan Laurie | c593999 | 2013-05-24 11:06:49 -0700 | [diff] [blame] | 46 | if (pch_is_lp()) { |
| 47 | /* PCH-LP has 39 redirection entries */ |
| 48 | reg32 &= ~0x00ff0000; |
| 49 | reg32 |= 0x00270000; |
| 50 | } |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 51 | io_apic_write(VIO_APIC_VADDR, 0x01, reg32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 52 | |
Paul Menzel | 373a20c | 2013-05-03 12:17:02 +0200 | [diff] [blame] | 53 | /* |
| 54 | * Select Boot Configuration register (0x03) and |
| 55 | * use Processor System Bus (0x01) to deliver interrupts. |
| 56 | */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 57 | io_apic_write(VIO_APIC_VADDR, 0x03, 0x01); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 58 | } |
| 59 | |
| 60 | static void pch_enable_serial_irqs(struct device *dev) |
| 61 | { |
| 62 | /* Set packet length and toggle silent mode bit for one frame. */ |
| 63 | pci_write_config8(dev, SERIRQ_CNTL, |
| 64 | (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 65 | #if !CONFIG(SERIRQ_CONTINUOUS_MODE) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 66 | pci_write_config8(dev, SERIRQ_CNTL, |
| 67 | (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); |
| 68 | #endif |
| 69 | } |
| 70 | |
Angel Pons | 1464a05 | 2020-10-30 20:21:37 +0100 | [diff] [blame] | 71 | static void enable_hpet(struct device *const dev) |
| 72 | { |
| 73 | u32 reg32; |
| 74 | size_t i; |
| 75 | |
| 76 | /* Assign unique bus/dev/fn for each HPET */ |
| 77 | for (i = 0; i < 8; ++i) |
| 78 | pci_write_config16(dev, LPC_HnBDF(i), |
| 79 | PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | i); |
| 80 | |
| 81 | /* Move HPET to default address 0xfed00000 and enable it */ |
| 82 | reg32 = RCBA32(HPTC); |
| 83 | reg32 |= (1 << 7); // HPET Address Enable |
| 84 | reg32 &= ~(3 << 0); |
| 85 | RCBA32(HPTC) = reg32; |
| 86 | /* Read it back to stick. It's affected by posted write syndrome. */ |
| 87 | RCBA32(HPTC); |
| 88 | } |
| 89 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 90 | /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control |
| 91 | * 0x00 - 0000 = Reserved |
| 92 | * 0x01 - 0001 = Reserved |
| 93 | * 0x02 - 0010 = Reserved |
| 94 | * 0x03 - 0011 = IRQ3 |
| 95 | * 0x04 - 0100 = IRQ4 |
| 96 | * 0x05 - 0101 = IRQ5 |
| 97 | * 0x06 - 0110 = IRQ6 |
| 98 | * 0x07 - 0111 = IRQ7 |
| 99 | * 0x08 - 1000 = Reserved |
| 100 | * 0x09 - 1001 = IRQ9 |
| 101 | * 0x0A - 1010 = IRQ10 |
| 102 | * 0x0B - 1011 = IRQ11 |
| 103 | * 0x0C - 1100 = IRQ12 |
| 104 | * 0x0D - 1101 = Reserved |
| 105 | * 0x0E - 1110 = IRQ14 |
| 106 | * 0x0F - 1111 = IRQ15 |
| 107 | * PIRQ[n]_ROUT[7] - PIRQ Routing Control |
| 108 | * 0x80 - The PIRQ is not routed. |
| 109 | */ |
| 110 | |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 111 | static void pch_pirq_init(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 112 | { |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 113 | struct device *irq_dev; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 114 | |
Angel Pons | 9f78127 | 2020-07-25 14:03:40 +0200 | [diff] [blame] | 115 | const uint8_t pirq = 0x80; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 116 | |
Angel Pons | 9f78127 | 2020-07-25 14:03:40 +0200 | [diff] [blame] | 117 | pci_write_config8(dev, PIRQA_ROUT, pirq); |
| 118 | pci_write_config8(dev, PIRQB_ROUT, pirq); |
| 119 | pci_write_config8(dev, PIRQC_ROUT, pirq); |
| 120 | pci_write_config8(dev, PIRQD_ROUT, pirq); |
| 121 | |
| 122 | pci_write_config8(dev, PIRQE_ROUT, pirq); |
| 123 | pci_write_config8(dev, PIRQF_ROUT, pirq); |
| 124 | pci_write_config8(dev, PIRQG_ROUT, pirq); |
| 125 | pci_write_config8(dev, PIRQH_ROUT, pirq); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 126 | |
| 127 | /* Eric Biederman once said we should let the OS do this. |
| 128 | * I am not so sure anymore he was right. |
| 129 | */ |
| 130 | |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 131 | for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { |
Angel Pons | 2aaf7c0 | 2020-09-24 18:03:18 +0200 | [diff] [blame] | 132 | u8 int_pin = 0, int_line = 0; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 133 | |
| 134 | if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) |
| 135 | continue; |
| 136 | |
| 137 | int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); |
| 138 | |
| 139 | switch (int_pin) { |
Angel Pons | 9f78127 | 2020-07-25 14:03:40 +0200 | [diff] [blame] | 140 | case 1: /* INTA# */ |
| 141 | case 2: /* INTB# */ |
| 142 | case 3: /* INTC# */ |
| 143 | case 4: /* INTD# */ |
| 144 | int_line = pirq; |
| 145 | break; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 146 | } |
| 147 | |
| 148 | if (!int_line) |
| 149 | continue; |
| 150 | |
| 151 | pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); |
| 152 | } |
| 153 | } |
| 154 | |
Angel Pons | cbcbb67 | 2020-10-23 00:11:26 +0200 | [diff] [blame] | 155 | static void pch_gpi_routing(struct device *dev, config_t *config) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 156 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 157 | u32 reg32 = 0; |
| 158 | |
| 159 | /* An array would be much nicer here, or some |
| 160 | * other method of doing this. |
| 161 | */ |
| 162 | reg32 |= (config->gpi0_routing & 0x03) << 0; |
| 163 | reg32 |= (config->gpi1_routing & 0x03) << 2; |
| 164 | reg32 |= (config->gpi2_routing & 0x03) << 4; |
| 165 | reg32 |= (config->gpi3_routing & 0x03) << 6; |
| 166 | reg32 |= (config->gpi4_routing & 0x03) << 8; |
| 167 | reg32 |= (config->gpi5_routing & 0x03) << 10; |
| 168 | reg32 |= (config->gpi6_routing & 0x03) << 12; |
| 169 | reg32 |= (config->gpi7_routing & 0x03) << 14; |
| 170 | reg32 |= (config->gpi8_routing & 0x03) << 16; |
| 171 | reg32 |= (config->gpi9_routing & 0x03) << 18; |
| 172 | reg32 |= (config->gpi10_routing & 0x03) << 20; |
| 173 | reg32 |= (config->gpi11_routing & 0x03) << 22; |
| 174 | reg32 |= (config->gpi12_routing & 0x03) << 24; |
| 175 | reg32 |= (config->gpi13_routing & 0x03) << 26; |
| 176 | reg32 |= (config->gpi14_routing & 0x03) << 28; |
| 177 | reg32 |= (config->gpi15_routing & 0x03) << 30; |
| 178 | |
Kyösti Mälkki | b85a87b | 2014-12-29 11:32:27 +0200 | [diff] [blame] | 179 | pci_write_config32(dev, GPIO_ROUT, reg32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 180 | } |
| 181 | |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 182 | static void pch_power_options(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 183 | { |
| 184 | u8 reg8; |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 185 | u16 reg16; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 186 | u32 reg32; |
| 187 | const char *state; |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 188 | u16 pmbase = get_pmbase(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 189 | |
| 190 | /* Which state do we want to goto after g3 (power restored)? |
| 191 | * 0 == S0 Full On |
| 192 | * 1 == S5 Soft Off |
| 193 | * |
| 194 | * If the option is not existent (Laptops), use Kconfig setting. |
| 195 | */ |
Angel Pons | 62719a3 | 2021-04-19 13:15:28 +0200 | [diff] [blame] | 196 | const int pwr_on = get_int_option("power_on_after_fail", |
| 197 | CONFIG_MAINBOARD_POWER_FAILURE_STATE); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 198 | |
| 199 | reg16 = pci_read_config16(dev, GEN_PMCON_3); |
| 200 | reg16 &= 0xfffe; |
| 201 | switch (pwr_on) { |
| 202 | case MAINBOARD_POWER_OFF: |
| 203 | reg16 |= 1; |
| 204 | state = "off"; |
| 205 | break; |
| 206 | case MAINBOARD_POWER_ON: |
| 207 | reg16 &= ~1; |
| 208 | state = "on"; |
| 209 | break; |
| 210 | case MAINBOARD_POWER_KEEP: |
| 211 | reg16 &= ~1; |
| 212 | state = "state keep"; |
| 213 | break; |
| 214 | default: |
| 215 | state = "undefined"; |
| 216 | } |
| 217 | |
| 218 | reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */ |
| 219 | reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */ |
| 220 | |
| 221 | reg16 &= ~(1 << 10); |
| 222 | reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */ |
| 223 | |
| 224 | reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */ |
| 225 | |
| 226 | pci_write_config16(dev, GEN_PMCON_3, reg16); |
| 227 | printk(BIOS_INFO, "Set power %s after power failure.\n", state); |
| 228 | |
| 229 | /* Set up NMI on errors. */ |
| 230 | reg8 = inb(0x61); |
| 231 | reg8 &= 0x0f; /* Higher Nibble must be 0 */ |
| 232 | reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */ |
| 233 | // reg8 &= ~(1 << 2); /* PCI SERR# Enable */ |
| 234 | reg8 |= (1 << 2); /* PCI SERR# Disable for now */ |
| 235 | outb(reg8, 0x61); |
| 236 | |
| 237 | reg8 = inb(0x70); |
Angel Pons | 62719a3 | 2021-04-19 13:15:28 +0200 | [diff] [blame] | 238 | const int nmi_option = get_int_option("nmi", NMI_OFF); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 239 | if (nmi_option) { |
| 240 | printk(BIOS_INFO, "NMI sources enabled.\n"); |
| 241 | reg8 &= ~(1 << 7); /* Set NMI. */ |
| 242 | } else { |
| 243 | printk(BIOS_INFO, "NMI sources disabled.\n"); |
Elyes HAOUAS | 9c5d463 | 2018-04-26 22:21:21 +0200 | [diff] [blame] | 244 | reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 245 | } |
| 246 | outb(reg8, 0x70); |
| 247 | |
| 248 | /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */ |
| 249 | reg16 = pci_read_config16(dev, GEN_PMCON_1); |
| 250 | reg16 &= ~(3 << 0); // SMI# rate 1 minute |
| 251 | reg16 &= ~(1 << 10); // Disable BIOS_PCI_EXP_EN for native PME |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 252 | pci_write_config16(dev, GEN_PMCON_1, reg16); |
| 253 | |
Angel Pons | cbcbb67 | 2020-10-23 00:11:26 +0200 | [diff] [blame] | 254 | if (dev->chip_info) { |
| 255 | config_t *config = dev->chip_info; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 256 | |
Angel Pons | cbcbb67 | 2020-10-23 00:11:26 +0200 | [diff] [blame] | 257 | /* |
| 258 | * Set the board's GPI routing on LynxPoint-H. |
| 259 | * This is done as part of GPIO configuration on LynxPoint-LP. |
| 260 | */ |
Angel Pons | a7174b7 | 2020-10-30 20:23:41 +0100 | [diff] [blame] | 261 | if (!pch_is_lp()) |
Angel Pons | cbcbb67 | 2020-10-23 00:11:26 +0200 | [diff] [blame] | 262 | pch_gpi_routing(dev, config); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 263 | |
Angel Pons | cbcbb67 | 2020-10-23 00:11:26 +0200 | [diff] [blame] | 264 | /* GPE setup based on device tree configuration */ |
| 265 | enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2, |
| 266 | config->gpe0_en_3, config->gpe0_en_4); |
| 267 | |
| 268 | /* SMI setup based on device tree configuration */ |
| 269 | enable_alt_smi(config->alt_gp_smi_en); |
| 270 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 271 | |
| 272 | /* Set up power management block and determine sleep mode */ |
| 273 | reg32 = inl(pmbase + 0x04); // PM1_CNT |
| 274 | reg32 &= ~(7 << 10); // SLP_TYP |
| 275 | reg32 |= (1 << 0); // SCI_EN |
| 276 | outl(reg32, pmbase + 0x04); |
| 277 | |
| 278 | /* Clear magic status bits to prevent unexpected wake */ |
| 279 | reg32 = RCBA32(0x3310); |
Angel Pons | 84fa224 | 2020-10-24 11:53:47 +0200 | [diff] [blame] | 280 | reg32 |= (1 << 4) | (1 << 5) | (1 << 0); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 281 | RCBA32(0x3310) = reg32; |
| 282 | |
Ryan Salsamendi | 889ce9c | 2017-06-30 17:45:14 -0700 | [diff] [blame] | 283 | reg16 = RCBA16(0x3f02); |
| 284 | reg16 &= ~0xf; |
| 285 | RCBA16(0x3f02) = reg16; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 286 | } |
| 287 | |
Angel Pons | 2cdf8bd | 2020-11-04 17:47:45 +0100 | [diff] [blame] | 288 | static void configure_dmi_pm(struct device *dev) |
| 289 | { |
| 290 | struct device *const pcie_dev = pcidev_on_root(0x1c, 0); |
| 291 | |
| 292 | /* Additional PCH DMI programming steps */ |
| 293 | |
| 294 | /* EL0 */ |
| 295 | u32 reg32 = 3 << 12; |
| 296 | |
| 297 | /* EL1 */ |
| 298 | if (pcie_dev && !(pci_read_config8(pcie_dev, 0xf5) & 1 << 0)) |
| 299 | reg32 |= 2 << 15; |
| 300 | else |
| 301 | reg32 |= 4 << 15; |
| 302 | |
| 303 | RCBA32_AND_OR(0x21a4, ~(7 << 15 | 7 << 12), reg32); |
| 304 | |
| 305 | RCBA32_AND_OR(0x2348, ~0xf, 0); |
| 306 | |
| 307 | /* Clear prior to enabling DMI ASPM */ |
| 308 | RCBA32_AND_OR(0x2304, ~(1 << 10), 0); |
| 309 | |
| 310 | RCBA32_OR(0x21a4, 3 << 10); |
| 311 | |
| 312 | RCBA16(0x21a8) |= 3 << 0; |
| 313 | |
| 314 | /* Set again after enabling DMI ASPM */ |
| 315 | RCBA32_OR(0x2304, 1 << 10); |
| 316 | } |
| 317 | |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 318 | /* LynxPoint PCH Power Management init */ |
| 319 | static void lpt_pm_init(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 320 | { |
Angel Pons | 2cdf8bd | 2020-11-04 17:47:45 +0100 | [diff] [blame] | 321 | struct southbridge_intel_lynxpoint_config *config = dev->chip_info; |
| 322 | |
| 323 | struct device *const pcie_dev = pcidev_on_root(0x1c, 0); |
| 324 | |
| 325 | printk(BIOS_DEBUG, "LynxPoint H PM init\n"); |
| 326 | |
| 327 | /* Configure additional PM */ |
| 328 | pci_write_config8(dev, 0xa9, 0x46); |
| 329 | |
| 330 | pci_or_config32(dev, PMIR, PMIR_CF9LOCK); |
| 331 | |
| 332 | /* Step 3 is skipped */ |
| 333 | |
| 334 | /* Program DMI Hardware Width Control (thermal throttling) */ |
| 335 | u32 reg32 = 0; |
| 336 | reg32 |= 1 << 0; /* DMI Thermal Sensor Autonomous Width Enable */ |
| 337 | reg32 |= 0 << 4; /* Thermal Sensor 0 Target Width */ |
| 338 | reg32 |= 1 << 6; /* Thermal Sensor 1 Target Width */ |
| 339 | reg32 |= 1 << 8; /* Thermal Sensor 2 Target Width */ |
| 340 | reg32 |= 2 << 10; /* Thermal Sensor 3 Target Width */ |
| 341 | RCBA32(0x2238) = reg32; |
| 342 | |
| 343 | RCBA32_OR(0x232c, 1 << 0); |
| 344 | RCBA32_OR(0x1100, 3 << 13); /* Assume trunk clock gating is to be enabled */ |
| 345 | |
| 346 | RCBA32(0x2304) = 0xc07b8400; /* DMI misc control */ |
| 347 | |
| 348 | RCBA32_OR(0x2314, 1 << 23 | 1 << 5); |
| 349 | |
| 350 | if (pcie_dev) |
| 351 | pci_update_config8(pcie_dev, 0xf5, ~0xf, 0x5); |
| 352 | |
| 353 | RCBA32_OR(0x2320, 1 << 1); |
| 354 | |
| 355 | RCBA32(0x3314) = 0x000007bf; |
| 356 | |
| 357 | /* NOTE: Preserve bit 5 */ |
| 358 | RCBA32_OR(0x3318, 0x0dcf0000); |
| 359 | |
| 360 | RCBA32(0x3324) = 0x04000000; |
| 361 | RCBA32(0x3340) = 0x020ddbff; |
| 362 | |
| 363 | RCBA32_OR(0x3344, 1 << 0); |
| 364 | |
| 365 | RCBA32(0x3368) = 0x00041000; |
| 366 | RCBA32(0x3378) = 0x3f8ddbff; |
| 367 | RCBA32(0x337c) = 0x000001e1; |
| 368 | RCBA32(0x3388) = 0x00001000; |
| 369 | RCBA32(0x33a0) = 0x00000800; |
| 370 | RCBA32(0x33ac) = 0x00001000; |
| 371 | RCBA32(0x33b0) = 0x00001000; |
| 372 | RCBA32(0x33c0) = 0x00011900; |
| 373 | RCBA32(0x33d0) = 0x06000802; |
| 374 | RCBA32(0x3a28) = 0x01010000; |
| 375 | RCBA32(0x3a2c) = 0x01010404; |
| 376 | |
| 377 | RCBA32_OR(0x33a4, 1 << 0); |
| 378 | |
| 379 | /* DMI power optimizer */ |
| 380 | RCBA32_OR(0x33d4, 1 << 27); |
| 381 | RCBA32_OR(0x33c8, 1 << 27); |
| 382 | RCBA32(0x2b14) = 0x1e0a0317; |
| 383 | RCBA32(0x2b24) = 0x4000000b; |
| 384 | RCBA32(0x2b28) = 0x00000002; |
| 385 | RCBA32(0x2b2c) = 0x00008813; |
| 386 | |
| 387 | RCBA32(0x3a80) = 0x01040000; |
| 388 | reg32 = 0x01041001; |
| 389 | /* Port 1 and 0 disabled */ |
| 390 | if (config && (config->sata_port_map & ((1 << 1) | (1 << 0))) == 0) |
| 391 | reg32 |= (1 << 20) | (1 << 18); |
| 392 | /* Port 3 and 2 disabled */ |
| 393 | if (config && (config->sata_port_map & ((1 << 3) | (1 << 2))) == 0) |
| 394 | reg32 |= (1 << 24) | (1 << 26); |
| 395 | RCBA32(0x3a84) = reg32; |
| 396 | RCBA32(0x3a88) = 0x00000001; |
| 397 | RCBA32(0x33d4) = 0xc80bc000; |
| 398 | |
| 399 | configure_dmi_pm(dev); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 400 | } |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 401 | |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 402 | /* LynxPoint LP PCH Power Management init */ |
| 403 | static void lpt_lp_pm_init(struct device *dev) |
| 404 | { |
| 405 | struct southbridge_intel_lynxpoint_config *config = dev->chip_info; |
| 406 | u32 data; |
| 407 | |
| 408 | printk(BIOS_DEBUG, "LynxPoint LP PM init\n"); |
| 409 | |
| 410 | pci_write_config8(dev, 0xa9, 0x46); |
| 411 | |
Angel Pons | 90cdf70 | 2020-10-24 23:00:34 +0200 | [diff] [blame] | 412 | RCBA32_AND_OR(0x232c, ~1, 0); |
| 413 | |
Angel Pons | 725657a | 2020-07-03 13:15:00 +0200 | [diff] [blame] | 414 | RCBA32_AND_OR(0x1100, ~0xc000, 0xc000); |
Angel Pons | 4fe4661 | 2020-10-24 22:22:04 +0200 | [diff] [blame] | 415 | RCBA32_OR(0x1100, 0x00000100); |
| 416 | RCBA32_OR(0x1100, 0x0000003f); |
Angel Pons | 90cdf70 | 2020-10-24 23:00:34 +0200 | [diff] [blame] | 417 | |
Angel Pons | 725657a | 2020-07-03 13:15:00 +0200 | [diff] [blame] | 418 | RCBA32_AND_OR(0x2320, ~0x60, 0x10); |
Angel Pons | 90cdf70 | 2020-10-24 23:00:34 +0200 | [diff] [blame] | 419 | |
Angel Pons | 4fe4661 | 2020-10-24 22:22:04 +0200 | [diff] [blame] | 420 | RCBA32(0x3314) = 0x00012fff; |
| 421 | RCBA32(0x3318) = 0x0dcf0400; |
| 422 | RCBA32(0x3324) = 0x04000000; |
| 423 | RCBA32(0x3368) = 0x00041400; |
| 424 | RCBA32(0x3388) = 0x3f8ddbff; |
| 425 | RCBA32(0x33ac) = 0x00007001; |
| 426 | RCBA32(0x33b0) = 0x00181900; |
| 427 | RCBA32(0x33c0) = 0x00060A00; |
| 428 | RCBA32(0x33d0) = 0x06200840; |
| 429 | RCBA32(0x3a28) = 0x01010101; |
| 430 | RCBA32(0x3a2c) = 0x04040404; |
| 431 | RCBA32(0x2b1c) = 0x03808033; |
| 432 | RCBA32(0x2b34) = 0x80000009; |
| 433 | RCBA32(0x3348) = 0x022ddfff; |
| 434 | RCBA32(0x334c) = 0x00000001; |
| 435 | RCBA32(0x3358) = 0x0001c000; |
| 436 | RCBA32(0x3380) = 0x3f8ddbff; |
| 437 | RCBA32(0x3384) = 0x0001c7e1; |
| 438 | RCBA32(0x338c) = 0x0001c7e1; |
| 439 | RCBA32(0x3398) = 0x0001c000; |
| 440 | RCBA32(0x33a8) = 0x00181900; |
| 441 | RCBA32(0x33dc) = 0x00080000; |
| 442 | RCBA32(0x33e0) = 0x00000001; |
| 443 | RCBA32(0x3a20) = 0x00000404; |
| 444 | RCBA32(0x3a24) = 0x01010101; |
| 445 | RCBA32(0x3a30) = 0x01010101; |
Angel Pons | 90cdf70 | 2020-10-24 23:00:34 +0200 | [diff] [blame] | 446 | |
Angel Pons | 4fe4661 | 2020-10-24 22:22:04 +0200 | [diff] [blame] | 447 | RCBA32_OR(0x0410, 0x00000003); |
| 448 | RCBA32_OR(0x2618, 0x08000000); |
| 449 | RCBA32_OR(0x2300, 0x00000002); |
| 450 | RCBA32_OR(0x2600, 0x00000008); |
Angel Pons | 90cdf70 | 2020-10-24 23:00:34 +0200 | [diff] [blame] | 451 | |
Angel Pons | 4fe4661 | 2020-10-24 22:22:04 +0200 | [diff] [blame] | 452 | RCBA32(0x33b4) = 0x00007001; |
| 453 | RCBA32(0x3350) = 0x022ddfff; |
| 454 | RCBA32(0x3354) = 0x00000001; |
Angel Pons | 90cdf70 | 2020-10-24 23:00:34 +0200 | [diff] [blame] | 455 | |
| 456 | /* Power Optimizer */ |
| 457 | RCBA32_OR(0x33d4, 0x08000000); |
| 458 | RCBA32_OR(0x33c8, 0x00000080); |
| 459 | |
| 460 | RCBA32(0x2b10) = 0x0000883c; |
| 461 | RCBA32(0x2b14) = 0x1e0a4616; |
| 462 | RCBA32(0x2b24) = 0x40000005; |
| 463 | RCBA32(0x2b20) = 0x0005db01; |
Angel Pons | 4fe4661 | 2020-10-24 22:22:04 +0200 | [diff] [blame] | 464 | RCBA32(0x3a80) = 0x05145005; |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 465 | |
Angel Pons | bf9bc50 | 2020-06-08 00:12:43 +0200 | [diff] [blame] | 466 | pci_or_config32(dev, 0xac, 1 << 21); |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 467 | |
Elyes HAOUAS | a0aea56 | 2017-07-03 21:38:53 +0200 | [diff] [blame] | 468 | pch_iobp_update(0xED00015C, ~(1 << 11), 0x00003700); |
Angel Pons | 8963f7d | 2020-10-24 12:20:28 +0200 | [diff] [blame] | 469 | pch_iobp_update(0xED000118, ~0, 0x00c00000); |
| 470 | pch_iobp_update(0xED000120, ~0, 0x00240000); |
| 471 | pch_iobp_update(0xCA000000, ~0, 0x00000009); |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 472 | |
| 473 | /* Set RCBA CIR28 0x3A84 based on SATA port enables */ |
| 474 | data = 0x00001005; |
| 475 | /* Port 3 and 2 disabled */ |
Angel Pons | cbcbb67 | 2020-10-23 00:11:26 +0200 | [diff] [blame] | 476 | if (config && (config->sata_port_map & ((1 << 3) | (1 << 2))) == 0) |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 477 | data |= (1 << 24) | (1 << 26); |
| 478 | /* Port 1 and 0 disabled */ |
Angel Pons | cbcbb67 | 2020-10-23 00:11:26 +0200 | [diff] [blame] | 479 | if (config && (config->sata_port_map & ((1 << 1) | (1 << 0))) == 0) |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 480 | data |= (1 << 20) | (1 << 18); |
| 481 | RCBA32(0x3a84) = data; |
| 482 | |
Duncan Laurie | 5cf34ce | 2013-04-26 10:41:33 -0700 | [diff] [blame] | 483 | /* Set RCBA 0x2b1c[29]=1 if DSP disabled */ |
| 484 | if (RCBA32(FD) & PCH_DISABLE_ADSPD) |
| 485 | RCBA32_OR(0x2b1c, (1 << 29)); |
| 486 | |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 487 | /* Set RCBA 0x33D4 after other setup */ |
| 488 | RCBA32_OR(0x33d4, 0x2fff2fb1); |
| 489 | |
| 490 | /* Set RCBA 0x33C8[15]=1 as last step */ |
| 491 | RCBA32_OR(0x33c8, (1 << 15)); |
| 492 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 493 | |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 494 | static void enable_clock_gating(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 495 | { |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 496 | /* LynxPoint Mobile */ |
| 497 | u32 reg32; |
| 498 | u16 reg16; |
| 499 | |
| 500 | /* DMI */ |
Angel Pons | 8963f7d | 2020-10-24 12:20:28 +0200 | [diff] [blame] | 501 | RCBA32_AND_OR(0x2234, ~0, 0xf); |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 502 | reg16 = pci_read_config16(dev, GEN_PMCON_1); |
| 503 | reg16 |= (1 << 11) | (1 << 12) | (1 << 14); |
| 504 | reg16 |= (1 << 2); // PCI CLKRUN# Enable |
| 505 | pci_write_config16(dev, GEN_PMCON_1, reg16); |
| 506 | RCBA32_OR(0x900, (1 << 14)); |
| 507 | |
| 508 | reg32 = RCBA32(CG); |
| 509 | reg32 |= (1 << 22); // HDA Dynamic |
Angel Pons | 8963f7d | 2020-10-24 12:20:28 +0200 | [diff] [blame] | 510 | reg32 |= (1 << 31); // LPC Dynamic |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 511 | reg32 |= (1 << 16); // PCIe Dynamic |
| 512 | reg32 |= (1 << 27); // HPET Dynamic |
| 513 | reg32 |= (1 << 28); // GPIO Dynamic |
| 514 | RCBA32(CG) = reg32; |
| 515 | |
| 516 | RCBA32_OR(0x38c0, 0x7); // SPI Dynamic |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 517 | } |
| 518 | |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 519 | static void enable_lp_clock_gating(struct device *dev) |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 520 | { |
| 521 | /* LynxPoint LP */ |
| 522 | u32 reg32; |
| 523 | u16 reg16; |
| 524 | |
| 525 | /* DMI */ |
Angel Pons | 8963f7d | 2020-10-24 12:20:28 +0200 | [diff] [blame] | 526 | RCBA32_AND_OR(0x2234, ~0, 0xf); |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 527 | reg16 = pci_read_config16(dev, GEN_PMCON_1); |
| 528 | reg16 &= ~((1 << 11) | (1 << 14)); |
| 529 | reg16 |= (1 << 5) | (1 << 6) | (1 << 7) | (1 << 12) | (1 << 13); |
| 530 | reg16 |= (1 << 2); // PCI CLKRUN# Enable |
| 531 | pci_write_config16(dev, GEN_PMCON_1, reg16); |
| 532 | |
Angel Pons | bf9bc50 | 2020-06-08 00:12:43 +0200 | [diff] [blame] | 533 | pci_or_config32(dev, 0x64, 1 << 6); |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 534 | |
Duncan Laurie | 4bc107b | 2013-06-24 13:14:44 -0700 | [diff] [blame] | 535 | /* |
| 536 | * RCBA + 0x2614[27:25,14:13,10,8] = 101,11,1,1 |
| 537 | * RCBA + 0x2614[23:16] = 0x20 |
| 538 | * RCBA + 0x2614[30:28] = 0x0 |
Duncan Laurie | d8c7d73 | 2013-07-16 09:01:43 -0700 | [diff] [blame] | 539 | * RCBA + 0x2614[26] = 1 (IF 0:2.0@0x08 >= 0x0b) |
Duncan Laurie | 4bc107b | 2013-06-24 13:14:44 -0700 | [diff] [blame] | 540 | */ |
Angel Pons | 90cdf70 | 2020-10-24 23:00:34 +0200 | [diff] [blame] | 541 | RCBA32_AND_OR(0x2614, ~0x74000000, 0x0a206500); |
Duncan Laurie | 4bc107b | 2013-06-24 13:14:44 -0700 | [diff] [blame] | 542 | |
| 543 | /* Check for LPT-LP B2 stepping and 0:31.0@0xFA > 4 */ |
Nico Huber | 744d6bd | 2019-01-12 14:58:20 +0100 | [diff] [blame] | 544 | struct device *const gma = pcidev_on_root(2, 0); |
| 545 | if (gma && pci_read_config8(gma, 0x8) >= 0x0b) |
Elyes HAOUAS | a0aea56 | 2017-07-03 21:38:53 +0200 | [diff] [blame] | 546 | RCBA32_OR(0x2614, (1 << 26)); |
Duncan Laurie | 4bc107b | 2013-06-24 13:14:44 -0700 | [diff] [blame] | 547 | |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 548 | RCBA32_OR(0x900, 0x0000031f); |
| 549 | |
| 550 | reg32 = RCBA32(CG); |
Duncan Laurie | a2d6a40 | 2013-03-22 11:24:45 -0700 | [diff] [blame] | 551 | if (RCBA32(0x3454) & (1 << 4)) |
| 552 | reg32 &= ~(1 << 29); // LPC Dynamic |
| 553 | else |
| 554 | reg32 |= (1 << 29); // LPC Dynamic |
Angel Pons | 2aaf7c0 | 2020-09-24 18:03:18 +0200 | [diff] [blame] | 555 | reg32 |= (1 << 31); // LP LPC |
Duncan Laurie | 5cf34ce | 2013-04-26 10:41:33 -0700 | [diff] [blame] | 556 | reg32 |= (1 << 30); // LP BLA |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 557 | reg32 |= (1 << 28); // GPIO Dynamic |
| 558 | reg32 |= (1 << 27); // HPET Dynamic |
Duncan Laurie | 5cf34ce | 2013-04-26 10:41:33 -0700 | [diff] [blame] | 559 | reg32 |= (1 << 26); // Generic Platform Event Clock |
| 560 | if (RCBA32(BUC) & PCH_DISABLE_GBE) |
| 561 | reg32 |= (1 << 23); // GbE Static |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 562 | reg32 |= (1 << 22); // HDA Dynamic |
Duncan Laurie | 5cf34ce | 2013-04-26 10:41:33 -0700 | [diff] [blame] | 563 | reg32 |= (1 << 16); // PCI Dynamic |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 564 | RCBA32(CG) = reg32; |
| 565 | |
| 566 | RCBA32_OR(0x3434, 0x7); // LP LPC |
| 567 | |
| 568 | RCBA32_AND_OR(0x333c, 0xffcfffff, 0x00c00000); // SATA |
| 569 | |
| 570 | RCBA32_OR(0x38c0, 0x3c07); // SPI Dynamic |
| 571 | |
Angel Pons | 8963f7d | 2020-10-24 12:20:28 +0200 | [diff] [blame] | 572 | pch_iobp_update(0xCF000000, ~0, 0x00007001); |
| 573 | pch_iobp_update(0xCE00C000, ~1, 0x00000000); // bit0=0 in BWG 1.4.0 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 574 | } |
| 575 | |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 576 | static void pch_set_acpi_mode(void) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 577 | { |
Kyösti Mälkki | ad882c3 | 2020-06-02 05:05:30 +0300 | [diff] [blame] | 578 | if (!acpi_is_wakeup_s3()) |
Kyösti Mälkki | b658548 | 2020-06-01 15:11:14 +0300 | [diff] [blame] | 579 | apm_control(APM_CNT_ACPI_DISABLE); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 580 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 581 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 582 | static void lpc_init(struct device *dev) |
| 583 | { |
Elyes HAOUAS | bfc255a | 2020-03-07 13:05:14 +0100 | [diff] [blame] | 584 | printk(BIOS_DEBUG, "pch: %s\n", __func__); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 585 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 586 | /* IO APIC initialization. */ |
Paul Menzel | 373a20c | 2013-05-03 12:17:02 +0200 | [diff] [blame] | 587 | pch_enable_ioapic(dev); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 588 | |
| 589 | pch_enable_serial_irqs(dev); |
| 590 | |
| 591 | /* Setup the PIRQ. */ |
| 592 | pch_pirq_init(dev); |
| 593 | |
| 594 | /* Setup power options. */ |
| 595 | pch_power_options(dev); |
| 596 | |
| 597 | /* Initialize power management */ |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 598 | if (pch_is_lp()) { |
| 599 | lpt_lp_pm_init(dev); |
| 600 | enable_lp_clock_gating(dev); |
| 601 | } else { |
| 602 | lpt_pm_init(dev); |
| 603 | enable_clock_gating(dev); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 604 | } |
| 605 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 606 | /* Initialize the real time clock. */ |
Patrick Rudolph | 6b93112 | 2018-11-01 17:48:37 +0100 | [diff] [blame] | 607 | sb_rtc_init(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 608 | |
| 609 | /* Initialize ISA DMA. */ |
| 610 | isa_dma_init(); |
| 611 | |
| 612 | /* Initialize the High Precision Event Timers, if present. */ |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 613 | enable_hpet(dev); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 614 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 615 | setup_i8259(); |
| 616 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 617 | /* Interrupt 9 should be level triggered (SCI) */ |
| 618 | i8259_configure_irq_trigger(9, 1); |
| 619 | |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 620 | pch_set_acpi_mode(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 621 | |
Angel Pons | 2cdf8bd | 2020-11-04 17:47:45 +0100 | [diff] [blame] | 622 | /* Indicate DRAM init done for MRC S3 to know it can resume */ |
| 623 | pci_or_config8(dev, GEN_PMCON_2, 1 << 7); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 624 | } |
| 625 | |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 626 | static void pch_lpc_add_mmio_resources(struct device *dev) |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 627 | { |
| 628 | u32 reg; |
| 629 | struct resource *res; |
| 630 | const u32 default_decode_base = IO_APIC_ADDR; |
| 631 | |
| 632 | /* |
| 633 | * Just report all resources from IO-APIC base to 4GiB. Don't mark |
| 634 | * them reserved as that may upset the OS if this range is marked |
| 635 | * as reserved in the e820. |
| 636 | */ |
| 637 | res = new_resource(dev, OIC); |
| 638 | res->base = default_decode_base; |
| 639 | res->size = 0 - default_decode_base; |
| 640 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 641 | |
| 642 | /* RCBA */ |
Angel Pons | 6e732d3 | 2021-01-28 13:56:18 +0100 | [diff] [blame] | 643 | if (CONFIG_FIXED_RCBA_MMIO_BASE < default_decode_base) { |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 644 | res = new_resource(dev, RCBA); |
Angel Pons | 6e732d3 | 2021-01-28 13:56:18 +0100 | [diff] [blame] | 645 | res->base = (resource_t)CONFIG_FIXED_RCBA_MMIO_BASE; |
Angel Pons | b70ff52 | 2021-01-28 14:27:46 +0100 | [diff] [blame] | 646 | res->size = CONFIG_RCBA_LENGTH; |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 647 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | |
Angel Pons | 2aaf7c0 | 2020-09-24 18:03:18 +0200 | [diff] [blame] | 648 | IORESOURCE_FIXED | IORESOURCE_RESERVE; |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 649 | } |
| 650 | |
| 651 | /* Check LPC Memory Decode register. */ |
| 652 | reg = pci_read_config32(dev, LGMR); |
| 653 | if (reg & 1) { |
| 654 | reg &= ~0xffff; |
| 655 | if (reg < default_decode_base) { |
| 656 | res = new_resource(dev, LGMR); |
| 657 | res->base = reg; |
| 658 | res->size = 16 * 1024; |
| 659 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | |
Angel Pons | 2aaf7c0 | 2020-09-24 18:03:18 +0200 | [diff] [blame] | 660 | IORESOURCE_FIXED | IORESOURCE_RESERVE; |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 661 | } |
| 662 | } |
| 663 | } |
| 664 | |
| 665 | /* Default IO range claimed by the LPC device. The upper bound is exclusive. */ |
| 666 | #define LPC_DEFAULT_IO_RANGE_LOWER 0 |
| 667 | #define LPC_DEFAULT_IO_RANGE_UPPER 0x1000 |
| 668 | |
Julius Werner | 7c712bb | 2019-05-01 16:51:20 -0700 | [diff] [blame] | 669 | static inline int pch_io_range_in_default(int base, int size) |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 670 | { |
| 671 | /* Does it start above the range? */ |
| 672 | if (base >= LPC_DEFAULT_IO_RANGE_UPPER) |
| 673 | return 0; |
| 674 | |
| 675 | /* Is it entirely contained? */ |
| 676 | if (base >= LPC_DEFAULT_IO_RANGE_LOWER && |
| 677 | (base + size) < LPC_DEFAULT_IO_RANGE_UPPER) |
| 678 | return 1; |
| 679 | |
| 680 | /* This will return not in range for partial overlaps. */ |
| 681 | return 0; |
| 682 | } |
| 683 | |
| 684 | /* |
| 685 | * Note: this function assumes there is no overlap with the default LPC device's |
| 686 | * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. |
| 687 | */ |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 688 | static void pch_lpc_add_io_resource(struct device *dev, u16 base, u16 size, |
| 689 | int index) |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 690 | { |
| 691 | struct resource *res; |
| 692 | |
| 693 | if (pch_io_range_in_default(base, size)) |
| 694 | return; |
| 695 | |
| 696 | res = new_resource(dev, index); |
| 697 | res->base = base; |
| 698 | res->size = size; |
| 699 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 700 | } |
| 701 | |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 702 | static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value, |
| 703 | int index) |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 704 | { |
| 705 | /* |
| 706 | * Check if the register is enabled. If so and the base exceeds the |
Kyösti Mälkki | b544c00 | 2019-01-06 10:41:41 +0200 | [diff] [blame] | 707 | * device's default, claim range and add the resource. |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 708 | */ |
| 709 | if (reg_value & 1) { |
| 710 | u16 base = reg_value & 0xfffc; |
| 711 | u16 size = (0x3 | ((reg_value >> 16) & 0xfc)) + 1; |
| 712 | pch_lpc_add_io_resource(dev, base, size, index); |
| 713 | } |
| 714 | } |
| 715 | |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 716 | static void pch_lpc_add_io_resources(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 717 | { |
| 718 | struct resource *res; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 719 | |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 720 | /* Add the default claimed IO range for the LPC device. */ |
| 721 | res = new_resource(dev, 0); |
| 722 | res->base = LPC_DEFAULT_IO_RANGE_LOWER; |
| 723 | res->size = LPC_DEFAULT_IO_RANGE_UPPER - LPC_DEFAULT_IO_RANGE_LOWER; |
| 724 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 725 | |
| 726 | /* GPIOBASE */ |
Angel Pons | 2aaf7c0 | 2020-09-24 18:03:18 +0200 | [diff] [blame] | 727 | pch_lpc_add_io_resource(dev, get_gpiobase(), DEFAULT_GPIOSIZE, GPIO_BASE); |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 728 | |
| 729 | /* PMBASE */ |
Duncan Laurie | 7922b46 | 2013-03-08 16:34:33 -0800 | [diff] [blame] | 730 | pch_lpc_add_io_resource(dev, get_pmbase(), 256, PMBASE); |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 731 | |
| 732 | /* LPC Generic IO Decode range. */ |
Angel Pons | cbcbb67 | 2020-10-23 00:11:26 +0200 | [diff] [blame] | 733 | if (dev->chip_info) { |
| 734 | config_t *config = dev->chip_info; |
| 735 | pch_lpc_add_gen_io_resources(dev, config->gen1_dec, LPC_GEN1_DEC); |
| 736 | pch_lpc_add_gen_io_resources(dev, config->gen2_dec, LPC_GEN2_DEC); |
| 737 | pch_lpc_add_gen_io_resources(dev, config->gen3_dec, LPC_GEN3_DEC); |
| 738 | pch_lpc_add_gen_io_resources(dev, config->gen4_dec, LPC_GEN4_DEC); |
| 739 | } |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 740 | } |
| 741 | |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 742 | static void pch_lpc_read_resources(struct device *dev) |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 743 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 744 | /* Get the normal PCI resources of this device. */ |
| 745 | pci_dev_read_resources(dev); |
| 746 | |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 747 | /* Add non-standard MMIO resources. */ |
| 748 | pch_lpc_add_mmio_resources(dev); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 749 | |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 750 | /* Add IO resources. */ |
| 751 | pch_lpc_add_io_resources(dev); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 752 | } |
| 753 | |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 754 | static void pch_lpc_enable(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 755 | { |
| 756 | /* Enable PCH Display Port */ |
| 757 | RCBA16(DISPBDF) = 0x0010; |
| 758 | RCBA32_OR(FD2, PCH_ENABLE_DBDF); |
| 759 | |
| 760 | pch_enable(dev); |
| 761 | } |
| 762 | |
Tristan Corrick | f3127d4 | 2018-10-31 02:25:54 +1300 | [diff] [blame] | 763 | static const char *lpc_acpi_name(const struct device *dev) |
| 764 | { |
| 765 | return "LPCB"; |
| 766 | } |
| 767 | |
Furquan Shaikh | 7536a39 | 2020-04-24 21:59:21 -0700 | [diff] [blame] | 768 | static void southbridge_fill_ssdt(const struct device *dev) |
Tristan Corrick | f3127d4 | 2018-10-31 02:25:54 +1300 | [diff] [blame] | 769 | { |
| 770 | intel_acpi_gen_def_acpi_pirq(dev); |
| 771 | } |
| 772 | |
Furquan Shaikh | 0f007d8 | 2020-04-24 06:41:18 -0700 | [diff] [blame] | 773 | static unsigned long southbridge_write_acpi_tables(const struct device *device, |
Alexander Couzens | 83fc32f | 2015-04-12 22:28:37 +0200 | [diff] [blame] | 774 | unsigned long start, |
| 775 | struct acpi_rsdp *rsdp) |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 776 | { |
| 777 | unsigned long current; |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 778 | |
| 779 | current = start; |
| 780 | |
| 781 | /* Align ACPI tables to 16byte */ |
Aaron Durbin | 07a1b28 | 2015-12-10 17:07:38 -0600 | [diff] [blame] | 782 | current = acpi_align_current(current); |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 783 | |
| 784 | /* |
| 785 | * We explicitly add these tables later on: |
| 786 | */ |
Angel Pons | 2d35cf8 | 2020-10-29 19:28:44 +0100 | [diff] [blame] | 787 | current = acpi_write_hpet(device, current, rsdp); |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 788 | |
Aaron Durbin | 07a1b28 | 2015-12-10 17:07:38 -0600 | [diff] [blame] | 789 | current = acpi_align_current(current); |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 790 | |
Angel Pons | 04f1de3 | 2021-02-10 13:57:01 +0100 | [diff] [blame] | 791 | if (pch_is_lp()) { |
| 792 | printk(BIOS_DEBUG, "ACPI: * SSDT2\n"); |
| 793 | acpi_header_t *ssdt = (acpi_header_t *)current; |
| 794 | acpi_create_serialio_ssdt(ssdt); |
| 795 | current += ssdt->length; |
| 796 | acpi_add_table(rsdp, ssdt); |
| 797 | current = acpi_align_current(current); |
| 798 | } |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 799 | |
| 800 | printk(BIOS_DEBUG, "current = %lx\n", current); |
| 801 | return current; |
| 802 | } |
| 803 | |
Tristan Corrick | 32ceed8 | 2018-11-30 22:53:27 +1300 | [diff] [blame] | 804 | static void lpc_final(struct device *dev) |
| 805 | { |
Arthur Heymans | a3121b0 | 2019-05-28 13:46:49 +0200 | [diff] [blame] | 806 | spi_finalize_ops(); |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame] | 807 | |
Angel Pons | 71505f5 | 2020-10-30 16:26:28 +0100 | [diff] [blame] | 808 | /* Lock */ |
| 809 | RCBA32_OR(0x3a6c, 0x00000001); |
| 810 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 811 | if (acpi_is_wakeup_s3() || CONFIG(INTEL_CHIPSET_LOCKDOWN)) |
Kyösti Mälkki | b658548 | 2020-06-01 15:11:14 +0300 | [diff] [blame] | 812 | apm_control(APM_CNT_FINALIZE); |
Tristan Corrick | 32ceed8 | 2018-11-30 22:53:27 +1300 | [diff] [blame] | 813 | } |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 814 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 815 | static struct device_operations device_ops = { |
| 816 | .read_resources = pch_lpc_read_resources, |
| 817 | .set_resources = pci_dev_set_resources, |
Duncan Laurie | 8d783b8 | 2013-05-14 11:16:34 -0700 | [diff] [blame] | 818 | .enable_resources = pci_dev_enable_resources, |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 819 | .acpi_fill_ssdt = southbridge_fill_ssdt, |
Tristan Corrick | f3127d4 | 2018-10-31 02:25:54 +1300 | [diff] [blame] | 820 | .acpi_name = lpc_acpi_name, |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 821 | .write_acpi_tables = southbridge_write_acpi_tables, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 822 | .init = lpc_init, |
Tristan Corrick | 32ceed8 | 2018-11-30 22:53:27 +1300 | [diff] [blame] | 823 | .final = lpc_final, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 824 | .enable = pch_lpc_enable, |
Nico Huber | 51b75ae | 2019-03-14 16:02:05 +0100 | [diff] [blame] | 825 | .scan_bus = scan_static_bus, |
Angel Pons | 1fc0edd | 2020-05-31 00:03:28 +0200 | [diff] [blame] | 826 | .ops_pci = &pci_dev_ops_pci, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 827 | }; |
| 828 | |
Aaron Durbin | c1989c4 | 2012-12-11 17:13:17 -0600 | [diff] [blame] | 829 | /* IDs for LPC device of Intel 8 Series Chipset (Lynx Point) */ |
| 830 | static const unsigned short pci_device_ids[] = { |
Felix Singer | 4ea08f9 | 2020-11-20 12:56:44 +0000 | [diff] [blame] | 831 | PCI_DEVICE_ID_INTEL_LPT_MOBILE_SAMPLE, |
| 832 | PCI_DEVICE_ID_INTEL_LPT_DESKTOP_SAMPLE, |
| 833 | PCI_DEVICE_ID_INTEL_LPT_Z87, |
| 834 | PCI_DEVICE_ID_INTEL_LPT_Z85, |
| 835 | PCI_DEVICE_ID_INTEL_LPT_HM86, |
| 836 | PCI_DEVICE_ID_INTEL_LPT_H87, |
| 837 | PCI_DEVICE_ID_INTEL_LPT_HM87, |
| 838 | PCI_DEVICE_ID_INTEL_LPT_Q85, |
| 839 | PCI_DEVICE_ID_INTEL_LPT_Q87, |
| 840 | PCI_DEVICE_ID_INTEL_LPT_QM87, |
| 841 | PCI_DEVICE_ID_INTEL_LPT_B85, |
| 842 | PCI_DEVICE_ID_INTEL_LPT_C222, |
| 843 | PCI_DEVICE_ID_INTEL_LPT_C224, |
| 844 | PCI_DEVICE_ID_INTEL_LPT_C226, |
| 845 | PCI_DEVICE_ID_INTEL_LPT_H81, |
| 846 | PCI_DEVICE_ID_INTEL_LPT_LP_SAMPLE, |
| 847 | PCI_DEVICE_ID_INTEL_LPT_LP_PREMIUM, |
| 848 | PCI_DEVICE_ID_INTEL_LPT_LP_MAINSTREAM, |
| 849 | PCI_DEVICE_ID_INTEL_LPT_LP_VALUE, |
| 850 | 0 |
| 851 | }; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 852 | |
| 853 | static const struct pci_driver pch_lpc __pci_driver = { |
| 854 | .ops = &device_ops, |
| 855 | .vendor = PCI_VENDOR_ID_INTEL, |
| 856 | .devices = pci_device_ids, |
| 857 | }; |