blob: 437db812af91a4f1eb278cccfccd97b5daae6ffa [file] [log] [blame]
Aaron Durbin76c37002012-10-30 09:03:43 -05001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2008-2009 coresystems GmbH
Duncan Laurie467f31d2013-03-08 17:00:37 -08005 * Copyright 2013 Google Inc.
Aaron Durbin76c37002012-10-30 09:03:43 -05006 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of
10 * the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
Aaron Durbin76c37002012-10-30 09:03:43 -050016 */
17
18#include <console/console.h>
19#include <device/device.h>
20#include <device/pci.h>
21#include <device/pci_ids.h>
Patrick Rudolphe56189c2018-04-18 10:11:59 +020022#include <device/pci_ops.h>
Aaron Durbin76c37002012-10-30 09:03:43 -050023#include <pc80/mc146818rtc.h>
24#include <pc80/isa-dma.h>
25#include <pc80/i8259.h>
26#include <arch/io.h>
27#include <arch/ioapic.h>
28#include <arch/acpi.h>
Elyes HAOUASd2b9ec12018-10-27 09:41:02 +020029#include <arch/cpu.h>
Aaron Durbin29ffa542012-12-21 21:21:48 -060030#include <cpu/x86/smm.h>
Duncan Laurie9c07c8f2013-03-22 11:08:39 -070031#include <cbmem.h>
32#include <string.h>
33#include "nvs.h"
Aaron Durbin76c37002012-10-30 09:03:43 -050034#include "pch.h"
Vladimir Serbinenkoc6e566a2014-08-31 17:43:51 +020035#include <arch/acpigen.h>
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +010036#include <drivers/intel/gma/i915.h>
Tristan Corrickf3127d42018-10-31 02:25:54 +130037#include <southbridge/intel/common/acpi_pirq_gen.h>
Patrick Rudolph6b931122018-11-01 17:48:37 +010038#include <southbridge/intel/common/rtc.h>
Aaron Durbin76c37002012-10-30 09:03:43 -050039
40#define NMI_OFF 0
41
42#define ENABLE_ACPI_MODE_IN_COREBOOT 0
Aaron Durbin76c37002012-10-30 09:03:43 -050043
44typedef struct southbridge_intel_lynxpoint_config config_t;
45
Paul Menzel373a20c2013-05-03 12:17:02 +020046/**
47 * Set miscellanous static southbridge features.
48 *
49 * @param dev PCI device with I/O APIC control registers
50 */
51static void pch_enable_ioapic(struct device *dev)
Aaron Durbin76c37002012-10-30 09:03:43 -050052{
Aaron Durbin76c37002012-10-30 09:03:43 -050053 u32 reg32;
Aaron Durbin76c37002012-10-30 09:03:43 -050054
Matt DeVilliera51e3792018-03-04 01:44:15 -060055 /* Assign unique bus/dev/fn for I/O APIC */
56 pci_write_config16(dev, LPC_IBDF,
57 PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3);
58
Paul Menzel373a20c2013-05-03 12:17:02 +020059 /* Enable ACPI I/O range decode */
60 pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
Aaron Durbin76c37002012-10-30 09:03:43 -050061
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080062 set_ioapic_id(VIO_APIC_VADDR, 0x02);
Aaron Durbin76c37002012-10-30 09:03:43 -050063
64 /* affirm full set of redirection table entries ("write once") */
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080065 reg32 = io_apic_read(VIO_APIC_VADDR, 0x01);
Duncan Lauriec5939992013-05-24 11:06:49 -070066 if (pch_is_lp()) {
67 /* PCH-LP has 39 redirection entries */
68 reg32 &= ~0x00ff0000;
69 reg32 |= 0x00270000;
70 }
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080071 io_apic_write(VIO_APIC_VADDR, 0x01, reg32);
Aaron Durbin76c37002012-10-30 09:03:43 -050072
Paul Menzel373a20c2013-05-03 12:17:02 +020073 /*
74 * Select Boot Configuration register (0x03) and
75 * use Processor System Bus (0x01) to deliver interrupts.
76 */
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080077 io_apic_write(VIO_APIC_VADDR, 0x03, 0x01);
Aaron Durbin76c37002012-10-30 09:03:43 -050078}
79
80static void pch_enable_serial_irqs(struct device *dev)
81{
82 /* Set packet length and toggle silent mode bit for one frame. */
83 pci_write_config8(dev, SERIRQ_CNTL,
84 (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
Martin Roth7a1a3ad2017-06-24 21:29:38 -060085#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)
Aaron Durbin76c37002012-10-30 09:03:43 -050086 pci_write_config8(dev, SERIRQ_CNTL,
87 (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
88#endif
89}
90
91/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
92 * 0x00 - 0000 = Reserved
93 * 0x01 - 0001 = Reserved
94 * 0x02 - 0010 = Reserved
95 * 0x03 - 0011 = IRQ3
96 * 0x04 - 0100 = IRQ4
97 * 0x05 - 0101 = IRQ5
98 * 0x06 - 0110 = IRQ6
99 * 0x07 - 0111 = IRQ7
100 * 0x08 - 1000 = Reserved
101 * 0x09 - 1001 = IRQ9
102 * 0x0A - 1010 = IRQ10
103 * 0x0B - 1011 = IRQ11
104 * 0x0C - 1100 = IRQ12
105 * 0x0D - 1101 = Reserved
106 * 0x0E - 1110 = IRQ14
107 * 0x0F - 1111 = IRQ15
108 * PIRQ[n]_ROUT[7] - PIRQ Routing Control
109 * 0x80 - The PIRQ is not routed.
110 */
111
Elyes HAOUAS7a5f7712018-06-08 17:20:38 +0200112static void pch_pirq_init(struct device *dev)
Aaron Durbin76c37002012-10-30 09:03:43 -0500113{
Elyes HAOUAS7a5f7712018-06-08 17:20:38 +0200114 struct device *irq_dev;
Aaron Durbin76c37002012-10-30 09:03:43 -0500115 /* Get the chip configuration */
116 config_t *config = dev->chip_info;
117
118 pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
119 pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
120 pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
121 pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
122
123 pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing);
124 pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing);
125 pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
126 pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
127
128 /* Eric Biederman once said we should let the OS do this.
129 * I am not so sure anymore he was right.
130 */
131
Elyes HAOUASba28e8d2016-08-31 19:22:16 +0200132 for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
Aaron Durbin76c37002012-10-30 09:03:43 -0500133 u8 int_pin=0, int_line=0;
134
135 if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
136 continue;
137
138 int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
139
140 switch (int_pin) {
141 case 1: /* INTA# */ int_line = config->pirqa_routing; break;
142 case 2: /* INTB# */ int_line = config->pirqb_routing; break;
143 case 3: /* INTC# */ int_line = config->pirqc_routing; break;
144 case 4: /* INTD# */ int_line = config->pirqd_routing; break;
145 }
146
147 if (!int_line)
148 continue;
149
150 pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
151 }
152}
153
Elyes HAOUAS7a5f7712018-06-08 17:20:38 +0200154static void pch_gpi_routing(struct device *dev)
Aaron Durbin76c37002012-10-30 09:03:43 -0500155{
156 /* Get the chip configuration */
157 config_t *config = dev->chip_info;
158 u32 reg32 = 0;
159
160 /* An array would be much nicer here, or some
161 * other method of doing this.
162 */
163 reg32 |= (config->gpi0_routing & 0x03) << 0;
164 reg32 |= (config->gpi1_routing & 0x03) << 2;
165 reg32 |= (config->gpi2_routing & 0x03) << 4;
166 reg32 |= (config->gpi3_routing & 0x03) << 6;
167 reg32 |= (config->gpi4_routing & 0x03) << 8;
168 reg32 |= (config->gpi5_routing & 0x03) << 10;
169 reg32 |= (config->gpi6_routing & 0x03) << 12;
170 reg32 |= (config->gpi7_routing & 0x03) << 14;
171 reg32 |= (config->gpi8_routing & 0x03) << 16;
172 reg32 |= (config->gpi9_routing & 0x03) << 18;
173 reg32 |= (config->gpi10_routing & 0x03) << 20;
174 reg32 |= (config->gpi11_routing & 0x03) << 22;
175 reg32 |= (config->gpi12_routing & 0x03) << 24;
176 reg32 |= (config->gpi13_routing & 0x03) << 26;
177 reg32 |= (config->gpi14_routing & 0x03) << 28;
178 reg32 |= (config->gpi15_routing & 0x03) << 30;
179
Kyösti Mälkkib85a87b2014-12-29 11:32:27 +0200180 pci_write_config32(dev, GPIO_ROUT, reg32);
Aaron Durbin76c37002012-10-30 09:03:43 -0500181}
182
Elyes HAOUAS7a5f7712018-06-08 17:20:38 +0200183static void pch_power_options(struct device *dev)
Aaron Durbin76c37002012-10-30 09:03:43 -0500184{
185 u8 reg8;
Duncan Laurie467f31d2013-03-08 17:00:37 -0800186 u16 reg16;
Aaron Durbin76c37002012-10-30 09:03:43 -0500187 u32 reg32;
188 const char *state;
189 /* Get the chip configuration */
190 config_t *config = dev->chip_info;
Duncan Laurie467f31d2013-03-08 17:00:37 -0800191 u16 pmbase = get_pmbase();
Aaron Durbin76c37002012-10-30 09:03:43 -0500192 int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
193 int nmi_option;
194
195 /* Which state do we want to goto after g3 (power restored)?
196 * 0 == S0 Full On
197 * 1 == S5 Soft Off
198 *
199 * If the option is not existent (Laptops), use Kconfig setting.
200 */
201 get_option(&pwr_on, "power_on_after_fail");
Elyes HAOUASba28e8d2016-08-31 19:22:16 +0200202 pwr_on = MAINBOARD_POWER_KEEP;
Aaron Durbin76c37002012-10-30 09:03:43 -0500203
204 reg16 = pci_read_config16(dev, GEN_PMCON_3);
205 reg16 &= 0xfffe;
206 switch (pwr_on) {
207 case MAINBOARD_POWER_OFF:
208 reg16 |= 1;
209 state = "off";
210 break;
211 case MAINBOARD_POWER_ON:
212 reg16 &= ~1;
213 state = "on";
214 break;
215 case MAINBOARD_POWER_KEEP:
216 reg16 &= ~1;
217 state = "state keep";
218 break;
219 default:
220 state = "undefined";
221 }
222
223 reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */
224 reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */
225
226 reg16 &= ~(1 << 10);
227 reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */
228
229 reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */
230
231 pci_write_config16(dev, GEN_PMCON_3, reg16);
232 printk(BIOS_INFO, "Set power %s after power failure.\n", state);
233
234 /* Set up NMI on errors. */
235 reg8 = inb(0x61);
236 reg8 &= 0x0f; /* Higher Nibble must be 0 */
237 reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */
238 // reg8 &= ~(1 << 2); /* PCI SERR# Enable */
239 reg8 |= (1 << 2); /* PCI SERR# Disable for now */
240 outb(reg8, 0x61);
241
242 reg8 = inb(0x70);
243 nmi_option = NMI_OFF;
244 get_option(&nmi_option, "nmi");
245 if (nmi_option) {
246 printk(BIOS_INFO, "NMI sources enabled.\n");
247 reg8 &= ~(1 << 7); /* Set NMI. */
248 } else {
249 printk(BIOS_INFO, "NMI sources disabled.\n");
Elyes HAOUAS9c5d4632018-04-26 22:21:21 +0200250 reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */
Aaron Durbin76c37002012-10-30 09:03:43 -0500251 }
252 outb(reg8, 0x70);
253
254 /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */
255 reg16 = pci_read_config16(dev, GEN_PMCON_1);
256 reg16 &= ~(3 << 0); // SMI# rate 1 minute
257 reg16 &= ~(1 << 10); // Disable BIOS_PCI_EXP_EN for native PME
Aaron Durbin76c37002012-10-30 09:03:43 -0500258 pci_write_config16(dev, GEN_PMCON_1, reg16);
259
Duncan Laurie467f31d2013-03-08 17:00:37 -0800260 /*
261 * Set the board's GPI routing on LynxPoint-H.
262 * This is done as part of GPIO configuration on LynxPoint-LP.
263 */
264 if (pch_is_lp())
265 pch_gpi_routing(dev);
Aaron Durbin76c37002012-10-30 09:03:43 -0500266
Duncan Laurie467f31d2013-03-08 17:00:37 -0800267 /* GPE setup based on device tree configuration */
268 enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2,
269 config->gpe0_en_3, config->gpe0_en_4);
Aaron Durbin76c37002012-10-30 09:03:43 -0500270
Duncan Laurie467f31d2013-03-08 17:00:37 -0800271 /* SMI setup based on device tree configuration */
272 enable_alt_smi(config->alt_gp_smi_en);
Aaron Durbin76c37002012-10-30 09:03:43 -0500273
274 /* Set up power management block and determine sleep mode */
275 reg32 = inl(pmbase + 0x04); // PM1_CNT
276 reg32 &= ~(7 << 10); // SLP_TYP
277 reg32 |= (1 << 0); // SCI_EN
278 outl(reg32, pmbase + 0x04);
279
280 /* Clear magic status bits to prevent unexpected wake */
281 reg32 = RCBA32(0x3310);
282 reg32 |= (1 << 4)|(1 << 5)|(1 << 0);
283 RCBA32(0x3310) = reg32;
284
Ryan Salsamendi889ce9c2017-06-30 17:45:14 -0700285 reg16 = RCBA16(0x3f02);
286 reg16 &= ~0xf;
287 RCBA16(0x3f02) = reg16;
Aaron Durbin76c37002012-10-30 09:03:43 -0500288}
289
Duncan Lauriedeb90f42013-03-08 17:22:37 -0800290/* LynxPoint PCH Power Management init */
291static void lpt_pm_init(struct device *dev)
Aaron Durbin76c37002012-10-30 09:03:43 -0500292{
Duncan Lauriedeb90f42013-03-08 17:22:37 -0800293 printk(BIOS_DEBUG, "LynxPoint PM init\n");
Aaron Durbin76c37002012-10-30 09:03:43 -0500294}
Duncan Lauriedeb90f42013-03-08 17:22:37 -0800295
296const struct rcba_config_instruction lpt_lp_pm_rcba[] = {
Duncan Laurie4bc107b2013-06-24 13:14:44 -0700297 RCBA_RMW_REG_32(0x232c, ~1, 0x00000000),
298 RCBA_RMW_REG_32(0x1100, ~0xc000, 0xc000),
299 RCBA_RMW_REG_32(0x1100, ~0, 0x00000100),
300 RCBA_RMW_REG_32(0x1100, ~0, 0x0000003f),
301 RCBA_RMW_REG_32(0x2320, ~0x60, 0x10),
302 RCBA_RMW_REG_32(0x3314, 0, 0x00012fff),
303 RCBA_RMW_REG_32(0x3318, 0, 0x0dcf0400),
304 RCBA_RMW_REG_32(0x3324, 0, 0x04000000),
305 RCBA_RMW_REG_32(0x3368, 0, 0x00041400),
306 RCBA_RMW_REG_32(0x3388, 0, 0x3f8ddbff),
307 RCBA_RMW_REG_32(0x33ac, 0, 0x00007001),
308 RCBA_RMW_REG_32(0x33b0, 0, 0x00181900),
309 RCBA_RMW_REG_32(0x33c0, 0, 0x00060A00),
310 RCBA_RMW_REG_32(0x33d0, 0, 0x06200840),
311 RCBA_RMW_REG_32(0x3a28, 0, 0x01010101),
312 RCBA_RMW_REG_32(0x3a2c, 0, 0x04040404),
313 RCBA_RMW_REG_32(0x2b1c, 0, 0x03808033),
314 RCBA_RMW_REG_32(0x2b34, 0, 0x80000009),
315 RCBA_RMW_REG_32(0x3348, 0, 0x022ddfff),
316 RCBA_RMW_REG_32(0x334c, 0, 0x00000001),
317 RCBA_RMW_REG_32(0x3358, 0, 0x0001c000),
318 RCBA_RMW_REG_32(0x3380, 0, 0x3f8ddbff),
319 RCBA_RMW_REG_32(0x3384, 0, 0x0001c7e1),
320 RCBA_RMW_REG_32(0x338c, 0, 0x0001c7e1),
321 RCBA_RMW_REG_32(0x3398, 0, 0x0001c000),
322 RCBA_RMW_REG_32(0x33a8, 0, 0x00181900),
323 RCBA_RMW_REG_32(0x33dc, 0, 0x00080000),
324 RCBA_RMW_REG_32(0x33e0, 0, 0x00000001),
325 RCBA_RMW_REG_32(0x3a20, 0, 0x00000404),
326 RCBA_RMW_REG_32(0x3a24, 0, 0x01010101),
327 RCBA_RMW_REG_32(0x3a30, 0, 0x01010101),
328 RCBA_RMW_REG_32(0x0410, ~0, 0x00000003),
329 RCBA_RMW_REG_32(0x2618, ~0, 0x08000000),
330 RCBA_RMW_REG_32(0x2300, ~0, 0x00000002),
331 RCBA_RMW_REG_32(0x2600, ~0, 0x00000008),
332 RCBA_RMW_REG_32(0x33b4, 0, 0x00007001),
333 RCBA_RMW_REG_32(0x3350, 0, 0x022ddfff),
334 RCBA_RMW_REG_32(0x3354, 0, 0x00000001),
Duncan Lauriedeb90f42013-03-08 17:22:37 -0800335 RCBA_RMW_REG_32(0x33d4, ~0, 0x08000000), /* Power Optimizer */
Matt DeVillierc97e0422017-02-16 11:36:16 -0600336 RCBA_RMW_REG_32(0x33c8, ~0, 0x00000080), /* Power Optimizer */
Duncan Lauriedeb90f42013-03-08 17:22:37 -0800337 RCBA_RMW_REG_32(0x2b10, 0, 0x0000883c), /* Power Optimizer */
Duncan Laurie5cf34ce2013-04-26 10:41:33 -0700338 RCBA_RMW_REG_32(0x2b14, 0, 0x1e0a4616), /* Power Optimizer */
Duncan Lauriedeb90f42013-03-08 17:22:37 -0800339 RCBA_RMW_REG_32(0x2b24, 0, 0x40000005), /* Power Optimizer */
340 RCBA_RMW_REG_32(0x2b20, 0, 0x0005db01), /* Power Optimizer */
Duncan Laurie4bc107b2013-06-24 13:14:44 -0700341 RCBA_RMW_REG_32(0x3a80, 0, 0x05145005),
Duncan Lauriedeb90f42013-03-08 17:22:37 -0800342 RCBA_END_CONFIG
343};
344
345/* LynxPoint LP PCH Power Management init */
346static void lpt_lp_pm_init(struct device *dev)
347{
348 struct southbridge_intel_lynxpoint_config *config = dev->chip_info;
349 u32 data;
350
351 printk(BIOS_DEBUG, "LynxPoint LP PM init\n");
352
353 pci_write_config8(dev, 0xa9, 0x46);
354
355 pch_config_rcba(lpt_lp_pm_rcba);
356
357 pci_write_config32(dev, 0xac,
358 pci_read_config32(dev, 0xac) | (1 << 21));
359
Elyes HAOUASa0aea562017-07-03 21:38:53 +0200360 pch_iobp_update(0xED00015C, ~(1 << 11), 0x00003700);
Duncan Laurie4bc107b2013-06-24 13:14:44 -0700361 pch_iobp_update(0xED000118, ~0UL, 0x00c00000);
362 pch_iobp_update(0xED000120, ~0UL, 0x00240000);
Duncan Lauriedeb90f42013-03-08 17:22:37 -0800363 pch_iobp_update(0xCA000000, ~0UL, 0x00000009);
364
365 /* Set RCBA CIR28 0x3A84 based on SATA port enables */
366 data = 0x00001005;
367 /* Port 3 and 2 disabled */
368 if ((config->sata_port_map & ((1 << 3)|(1 << 2))) == 0)
369 data |= (1 << 24) | (1 << 26);
370 /* Port 1 and 0 disabled */
371 if ((config->sata_port_map & ((1 << 1)|(1 << 0))) == 0)
372 data |= (1 << 20) | (1 << 18);
373 RCBA32(0x3a84) = data;
374
Duncan Laurie5cf34ce2013-04-26 10:41:33 -0700375 /* Set RCBA 0x2b1c[29]=1 if DSP disabled */
376 if (RCBA32(FD) & PCH_DISABLE_ADSPD)
377 RCBA32_OR(0x2b1c, (1 << 29));
378
Duncan Lauriedeb90f42013-03-08 17:22:37 -0800379 /* Lock */
380 RCBA32_OR(0x3a6c, 0x00000001);
381
382 /* Set RCBA 0x33D4 after other setup */
383 RCBA32_OR(0x33d4, 0x2fff2fb1);
384
385 /* Set RCBA 0x33C8[15]=1 as last step */
386 RCBA32_OR(0x33c8, (1 << 15));
387}
Aaron Durbin76c37002012-10-30 09:03:43 -0500388
Matt DeVilliera51e3792018-03-04 01:44:15 -0600389static void enable_hpet(struct device *const dev)
Aaron Durbin76c37002012-10-30 09:03:43 -0500390{
391 u32 reg32;
Matt DeVilliera51e3792018-03-04 01:44:15 -0600392 size_t i;
393
394 /* Assign unique bus/dev/fn for each HPET */
395 for (i = 0; i < 8; ++i)
396 pci_write_config16(dev, LPC_HnBDF(i),
397 PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | i);
Aaron Durbin76c37002012-10-30 09:03:43 -0500398
399 /* Move HPET to default address 0xfed00000 and enable it */
400 reg32 = RCBA32(HPTC);
401 reg32 |= (1 << 7); // HPET Address Enable
402 reg32 &= ~(3 << 0);
403 RCBA32(HPTC) = reg32;
404 /* Read it back to stick. It's affected by posted write syndrome. */
405 reg32 = RCBA32(HPTC);
406}
407
Elyes HAOUAS7a5f7712018-06-08 17:20:38 +0200408static void enable_clock_gating(struct device *dev)
Aaron Durbin76c37002012-10-30 09:03:43 -0500409{
Duncan Laurie74c0d052012-12-17 11:31:40 -0800410 /* LynxPoint Mobile */
411 u32 reg32;
412 u16 reg16;
413
414 /* DMI */
415 RCBA32_AND_OR(0x2234, ~0UL, 0xf);
416 reg16 = pci_read_config16(dev, GEN_PMCON_1);
417 reg16 |= (1 << 11) | (1 << 12) | (1 << 14);
418 reg16 |= (1 << 2); // PCI CLKRUN# Enable
419 pci_write_config16(dev, GEN_PMCON_1, reg16);
420 RCBA32_OR(0x900, (1 << 14));
421
422 reg32 = RCBA32(CG);
423 reg32 |= (1 << 22); // HDA Dynamic
Ryan Salsamendi0d9b3602017-06-30 17:15:57 -0700424 reg32 |= (1UL << 31); // LPC Dynamic
Duncan Laurie74c0d052012-12-17 11:31:40 -0800425 reg32 |= (1 << 16); // PCIe Dynamic
426 reg32 |= (1 << 27); // HPET Dynamic
427 reg32 |= (1 << 28); // GPIO Dynamic
428 RCBA32(CG) = reg32;
429
430 RCBA32_OR(0x38c0, 0x7); // SPI Dynamic
Duncan Lauriedeb90f42013-03-08 17:22:37 -0800431}
432
Elyes HAOUAS7a5f7712018-06-08 17:20:38 +0200433static void enable_lp_clock_gating(struct device *dev)
Duncan Lauriedeb90f42013-03-08 17:22:37 -0800434{
435 /* LynxPoint LP */
436 u32 reg32;
437 u16 reg16;
438
439 /* DMI */
440 RCBA32_AND_OR(0x2234, ~0UL, 0xf);
441 reg16 = pci_read_config16(dev, GEN_PMCON_1);
442 reg16 &= ~((1 << 11) | (1 << 14));
443 reg16 |= (1 << 5) | (1 << 6) | (1 << 7) | (1 << 12) | (1 << 13);
444 reg16 |= (1 << 2); // PCI CLKRUN# Enable
445 pci_write_config16(dev, GEN_PMCON_1, reg16);
446
447 reg32 = pci_read_config32(dev, 0x64);
448 reg32 |= (1 << 6);
449 pci_write_config32(dev, 0x64, reg32);
450
Duncan Laurie4bc107b2013-06-24 13:14:44 -0700451 /*
452 * RCBA + 0x2614[27:25,14:13,10,8] = 101,11,1,1
453 * RCBA + 0x2614[23:16] = 0x20
454 * RCBA + 0x2614[30:28] = 0x0
Duncan Lauried8c7d732013-07-16 09:01:43 -0700455 * RCBA + 0x2614[26] = 1 (IF 0:2.0@0x08 >= 0x0b)
Duncan Laurie4bc107b2013-06-24 13:14:44 -0700456 */
Duncan Lauriedeb90f42013-03-08 17:22:37 -0800457 RCBA32_AND_OR(0x2614, 0x8bffffff, 0x0a206500);
Duncan Laurie4bc107b2013-06-24 13:14:44 -0700458
459 /* Check for LPT-LP B2 stepping and 0:31.0@0xFA > 4 */
Duncan Lauried8c7d732013-07-16 09:01:43 -0700460 if (pci_read_config8(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x8) >= 0x0b)
Elyes HAOUASa0aea562017-07-03 21:38:53 +0200461 RCBA32_OR(0x2614, (1 << 26));
Duncan Laurie4bc107b2013-06-24 13:14:44 -0700462
Duncan Lauriedeb90f42013-03-08 17:22:37 -0800463 RCBA32_OR(0x900, 0x0000031f);
464
465 reg32 = RCBA32(CG);
Duncan Lauriea2d6a402013-03-22 11:24:45 -0700466 if (RCBA32(0x3454) & (1 << 4))
467 reg32 &= ~(1 << 29); // LPC Dynamic
468 else
469 reg32 |= (1 << 29); // LPC Dynamic
Ryan Salsamendi3f2fe182017-07-04 13:14:16 -0700470 reg32 |= (1UL << 31); // LP LPC
Duncan Laurie5cf34ce2013-04-26 10:41:33 -0700471 reg32 |= (1 << 30); // LP BLA
Duncan Lauriedeb90f42013-03-08 17:22:37 -0800472 reg32 |= (1 << 28); // GPIO Dynamic
473 reg32 |= (1 << 27); // HPET Dynamic
Duncan Laurie5cf34ce2013-04-26 10:41:33 -0700474 reg32 |= (1 << 26); // Generic Platform Event Clock
475 if (RCBA32(BUC) & PCH_DISABLE_GBE)
476 reg32 |= (1 << 23); // GbE Static
Duncan Lauriedeb90f42013-03-08 17:22:37 -0800477 reg32 |= (1 << 22); // HDA Dynamic
Duncan Laurie5cf34ce2013-04-26 10:41:33 -0700478 reg32 |= (1 << 16); // PCI Dynamic
Duncan Lauriedeb90f42013-03-08 17:22:37 -0800479 RCBA32(CG) = reg32;
480
481 RCBA32_OR(0x3434, 0x7); // LP LPC
482
483 RCBA32_AND_OR(0x333c, 0xffcfffff, 0x00c00000); // SATA
484
485 RCBA32_OR(0x38c0, 0x3c07); // SPI Dynamic
486
487 pch_iobp_update(0xCF000000, ~0UL, 0x00007001);
Duncan Laurie5cf34ce2013-04-26 10:41:33 -0700488 pch_iobp_update(0xCE00C000, ~1UL, 0x00000000); // bit0=0 in BWG 1.4.0
Aaron Durbin76c37002012-10-30 09:03:43 -0500489}
490
Aaron Durbin29ffa542012-12-21 21:21:48 -0600491static void pch_set_acpi_mode(void)
Aaron Durbin76c37002012-10-30 09:03:43 -0500492{
Martin Roth7a1a3ad2017-06-24 21:29:38 -0600493#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
Kyösti Mälkkic3ed8862014-06-19 19:50:51 +0300494 if (!acpi_is_wakeup_s3()) {
Aaron Durbin76c37002012-10-30 09:03:43 -0500495#if ENABLE_ACPI_MODE_IN_COREBOOT
496 printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
Aaron Durbin29ffa542012-12-21 21:21:48 -0600497 outb(APM_CNT_ACPI_ENABLE, APM_CNT);
Aaron Durbin76c37002012-10-30 09:03:43 -0500498 printk(BIOS_DEBUG, "done.\n");
499#else
500 printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
Aaron Durbin29ffa542012-12-21 21:21:48 -0600501 outb(APM_CNT_ACPI_DISABLE, APM_CNT);
Aaron Durbin76c37002012-10-30 09:03:43 -0500502 printk(BIOS_DEBUG, "done.\n");
503#endif
504 }
Aaron Durbin29ffa542012-12-21 21:21:48 -0600505#endif /* CONFIG_HAVE_SMI_HANDLER */
Aaron Durbin76c37002012-10-30 09:03:43 -0500506}
Aaron Durbin76c37002012-10-30 09:03:43 -0500507
508static void pch_disable_smm_only_flashing(struct device *dev)
509{
510 u8 reg8;
511
512 printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... ");
513 reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
514 reg8 &= ~(1 << 5);
515 pci_write_config8(dev, 0xdc, reg8);
516}
517
518static void pch_fixups(struct device *dev)
519{
520 u8 gen_pmcon_2;
521
522 /* Indicate DRAM init done for MRC S3 to know it can resume */
523 gen_pmcon_2 = pci_read_config8(dev, GEN_PMCON_2);
524 gen_pmcon_2 |= (1 << 7);
525 pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2);
526
527 /*
528 * Enable DMI ASPM in the PCH
529 */
530 RCBA32_AND_OR(0x2304, ~(1 << 10), 0);
531 RCBA32_OR(0x21a4, (1 << 11)|(1 << 10));
532 RCBA32_OR(0x21a8, 0x3);
533}
534
Aaron Durbin76c37002012-10-30 09:03:43 -0500535static void lpc_init(struct device *dev)
536{
537 printk(BIOS_DEBUG, "pch: lpc_init\n");
538
539 /* Set the value for PCI command register. */
540 pci_write_config16(dev, PCI_COMMAND, 0x000f);
541
542 /* IO APIC initialization. */
Paul Menzel373a20c2013-05-03 12:17:02 +0200543 pch_enable_ioapic(dev);
Aaron Durbin76c37002012-10-30 09:03:43 -0500544
545 pch_enable_serial_irqs(dev);
546
547 /* Setup the PIRQ. */
548 pch_pirq_init(dev);
549
550 /* Setup power options. */
551 pch_power_options(dev);
552
553 /* Initialize power management */
Duncan Lauriedeb90f42013-03-08 17:22:37 -0800554 if (pch_is_lp()) {
555 lpt_lp_pm_init(dev);
556 enable_lp_clock_gating(dev);
557 } else {
558 lpt_pm_init(dev);
559 enable_clock_gating(dev);
Aaron Durbin76c37002012-10-30 09:03:43 -0500560 }
561
Aaron Durbin76c37002012-10-30 09:03:43 -0500562 /* Initialize the real time clock. */
Patrick Rudolph6b931122018-11-01 17:48:37 +0100563 sb_rtc_init();
Aaron Durbin76c37002012-10-30 09:03:43 -0500564
565 /* Initialize ISA DMA. */
566 isa_dma_init();
567
568 /* Initialize the High Precision Event Timers, if present. */
Matt DeVilliera51e3792018-03-04 01:44:15 -0600569 enable_hpet(dev);
Aaron Durbin76c37002012-10-30 09:03:43 -0500570
Aaron Durbin76c37002012-10-30 09:03:43 -0500571 setup_i8259();
572
Aaron Durbin76c37002012-10-30 09:03:43 -0500573 /* Interrupt 9 should be level triggered (SCI) */
574 i8259_configure_irq_trigger(9, 1);
575
576 pch_disable_smm_only_flashing(dev);
577
Aaron Durbin29ffa542012-12-21 21:21:48 -0600578 pch_set_acpi_mode();
Aaron Durbin76c37002012-10-30 09:03:43 -0500579
580 pch_fixups(dev);
581}
582
Elyes HAOUAS7a5f7712018-06-08 17:20:38 +0200583static void pch_lpc_add_mmio_resources(struct device *dev)
Aaron Durbin6f561af2012-12-19 14:38:01 -0600584{
585 u32 reg;
586 struct resource *res;
587 const u32 default_decode_base = IO_APIC_ADDR;
588
589 /*
590 * Just report all resources from IO-APIC base to 4GiB. Don't mark
591 * them reserved as that may upset the OS if this range is marked
592 * as reserved in the e820.
593 */
594 res = new_resource(dev, OIC);
595 res->base = default_decode_base;
596 res->size = 0 - default_decode_base;
597 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
598
599 /* RCBA */
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800600 if ((uintptr_t)DEFAULT_RCBA < default_decode_base) {
Aaron Durbin6f561af2012-12-19 14:38:01 -0600601 res = new_resource(dev, RCBA);
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800602 res->base = (resource_t)(uintptr_t)DEFAULT_RCBA;
Aaron Durbin6f561af2012-12-19 14:38:01 -0600603 res->size = 16 * 1024;
604 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
605 IORESOURCE_FIXED | IORESOURCE_RESERVE;
606 }
607
608 /* Check LPC Memory Decode register. */
609 reg = pci_read_config32(dev, LGMR);
610 if (reg & 1) {
611 reg &= ~0xffff;
612 if (reg < default_decode_base) {
613 res = new_resource(dev, LGMR);
614 res->base = reg;
615 res->size = 16 * 1024;
616 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
617 IORESOURCE_FIXED | IORESOURCE_RESERVE;
618 }
619 }
620}
621
622/* Default IO range claimed by the LPC device. The upper bound is exclusive. */
623#define LPC_DEFAULT_IO_RANGE_LOWER 0
624#define LPC_DEFAULT_IO_RANGE_UPPER 0x1000
625
626static inline int pch_io_range_in_default(u16 base, u16 size)
627{
628 /* Does it start above the range? */
629 if (base >= LPC_DEFAULT_IO_RANGE_UPPER)
630 return 0;
631
632 /* Is it entirely contained? */
633 if (base >= LPC_DEFAULT_IO_RANGE_LOWER &&
634 (base + size) < LPC_DEFAULT_IO_RANGE_UPPER)
635 return 1;
636
637 /* This will return not in range for partial overlaps. */
638 return 0;
639}
640
641/*
642 * Note: this function assumes there is no overlap with the default LPC device's
643 * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER.
644 */
Elyes HAOUAS7a5f7712018-06-08 17:20:38 +0200645static void pch_lpc_add_io_resource(struct device *dev, u16 base, u16 size,
646 int index)
Aaron Durbin6f561af2012-12-19 14:38:01 -0600647{
648 struct resource *res;
649
650 if (pch_io_range_in_default(base, size))
651 return;
652
653 res = new_resource(dev, index);
654 res->base = base;
655 res->size = size;
656 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
657}
658
Elyes HAOUAS7a5f7712018-06-08 17:20:38 +0200659static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value,
660 int index)
Aaron Durbin6f561af2012-12-19 14:38:01 -0600661{
662 /*
663 * Check if the register is enabled. If so and the base exceeds the
664 * device's deafult claim range add the resoure.
665 */
666 if (reg_value & 1) {
667 u16 base = reg_value & 0xfffc;
668 u16 size = (0x3 | ((reg_value >> 16) & 0xfc)) + 1;
669 pch_lpc_add_io_resource(dev, base, size, index);
670 }
671}
672
Elyes HAOUAS7a5f7712018-06-08 17:20:38 +0200673static void pch_lpc_add_io_resources(struct device *dev)
Aaron Durbin76c37002012-10-30 09:03:43 -0500674{
675 struct resource *res;
676 config_t *config = dev->chip_info;
Aaron Durbin76c37002012-10-30 09:03:43 -0500677
Aaron Durbin6f561af2012-12-19 14:38:01 -0600678 /* Add the default claimed IO range for the LPC device. */
679 res = new_resource(dev, 0);
680 res->base = LPC_DEFAULT_IO_RANGE_LOWER;
681 res->size = LPC_DEFAULT_IO_RANGE_UPPER - LPC_DEFAULT_IO_RANGE_LOWER;
682 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
683
684 /* GPIOBASE */
Duncan Laurie7922b462013-03-08 16:34:33 -0800685 pch_lpc_add_io_resource(dev, get_gpiobase(), DEFAULT_GPIOSIZE,
Aaron Durbin6f561af2012-12-19 14:38:01 -0600686 GPIO_BASE);
687
688 /* PMBASE */
Duncan Laurie7922b462013-03-08 16:34:33 -0800689 pch_lpc_add_io_resource(dev, get_pmbase(), 256, PMBASE);
Aaron Durbin6f561af2012-12-19 14:38:01 -0600690
691 /* LPC Generic IO Decode range. */
692 pch_lpc_add_gen_io_resources(dev, config->gen1_dec, LPC_GEN1_DEC);
693 pch_lpc_add_gen_io_resources(dev, config->gen2_dec, LPC_GEN2_DEC);
694 pch_lpc_add_gen_io_resources(dev, config->gen3_dec, LPC_GEN3_DEC);
695 pch_lpc_add_gen_io_resources(dev, config->gen4_dec, LPC_GEN4_DEC);
696}
697
Elyes HAOUAS7a5f7712018-06-08 17:20:38 +0200698static void pch_lpc_read_resources(struct device *dev)
Aaron Durbin6f561af2012-12-19 14:38:01 -0600699{
Duncan Laurie9c07c8f2013-03-22 11:08:39 -0700700 global_nvs_t *gnvs;
701
Aaron Durbin76c37002012-10-30 09:03:43 -0500702 /* Get the normal PCI resources of this device. */
703 pci_dev_read_resources(dev);
704
Aaron Durbin6f561af2012-12-19 14:38:01 -0600705 /* Add non-standard MMIO resources. */
706 pch_lpc_add_mmio_resources(dev);
Aaron Durbin76c37002012-10-30 09:03:43 -0500707
Aaron Durbin6f561af2012-12-19 14:38:01 -0600708 /* Add IO resources. */
709 pch_lpc_add_io_resources(dev);
Duncan Laurie9c07c8f2013-03-22 11:08:39 -0700710
711 /* Allocate ACPI NVS in CBMEM */
712 gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t));
Kyösti Mälkkic3ed8862014-06-19 19:50:51 +0300713 if (!acpi_is_wakeup_s3() && gnvs)
Duncan Laurie9c07c8f2013-03-22 11:08:39 -0700714 memset(gnvs, 0, sizeof(global_nvs_t));
Aaron Durbin76c37002012-10-30 09:03:43 -0500715}
716
Elyes HAOUAS7a5f7712018-06-08 17:20:38 +0200717static void pch_lpc_enable(struct device *dev)
Aaron Durbin76c37002012-10-30 09:03:43 -0500718{
719 /* Enable PCH Display Port */
720 RCBA16(DISPBDF) = 0x0010;
721 RCBA32_OR(FD2, PCH_ENABLE_DBDF);
722
723 pch_enable(dev);
724}
725
Elyes HAOUAS7a5f7712018-06-08 17:20:38 +0200726static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)
Aaron Durbin76c37002012-10-30 09:03:43 -0500727{
728 if (!vendor || !device) {
729 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
730 pci_read_config32(dev, PCI_VENDOR_ID));
731 } else {
732 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
733 ((device & 0xffff) << 16) | (vendor & 0xffff));
734 }
735}
736
Elyes HAOUAS7a5f7712018-06-08 17:20:38 +0200737static void southbridge_inject_dsdt(struct device *dev)
Vladimir Serbinenkoc6e566a2014-08-31 17:43:51 +0200738{
Vladimir Serbinenko7309c642014-10-05 11:07:33 +0200739 global_nvs_t *gnvs;
740
741 gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
742 if (!gnvs) {
Elyes HAOUAS035df002016-10-03 21:54:16 +0200743 gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
Vladimir Serbinenko7309c642014-10-05 11:07:33 +0200744 if (gnvs)
745 memset(gnvs, 0, sizeof(*gnvs));
746 }
Vladimir Serbinenkoc6e566a2014-08-31 17:43:51 +0200747
748 if (gnvs) {
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +0100749 const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
750
Vladimir Serbinenkoc6e566a2014-08-31 17:43:51 +0200751 acpi_create_gnvs(gnvs);
Vladimir Serbinenko1b409fd2014-10-12 00:26:21 +0200752
753 gnvs->apic = 1;
754 gnvs->mpen = 1; /* Enable Multi Processing */
755 gnvs->pcnt = dev_count_cpu();
756
Martin Roth7a1a3ad2017-06-24 21:29:38 -0600757#if IS_ENABLED(CONFIG_CHROMEOS)
Joel Kitching6fbd8742018-08-23 14:56:25 +0800758 chromeos_init_chromeos_acpi(&(gnvs->chromeos));
Vladimir Serbinenko1b409fd2014-10-12 00:26:21 +0200759#endif
760
761 /* Update the mem console pointer. */
762 gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
763
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +0100764 gnvs->ndid = gfx->ndid;
765 memcpy(gnvs->did, gfx->did, sizeof(gnvs->did));
766
Vladimir Serbinenkoc6e566a2014-08-31 17:43:51 +0200767 /* And tell SMI about it */
768 smm_setup_structures(gnvs, NULL, NULL);
769
Vladimir Serbinenko334fd8e2014-10-05 11:10:35 +0200770 /* Add it to DSDT. */
Vladimir Serbinenkobe0fd0a2014-11-04 21:10:59 +0100771 acpigen_write_scope("\\");
772 acpigen_write_name_dword("NVSA", (u32) gnvs);
773 acpigen_pop_len();
Vladimir Serbinenkoc6e566a2014-08-31 17:43:51 +0200774 }
Vladimir Serbinenkoc6e566a2014-08-31 17:43:51 +0200775}
776
Tristan Corrickb2632ce2018-10-31 02:28:13 +1300777void acpi_fill_fadt(acpi_fadt_t *fadt)
778{
779 struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
780 struct southbridge_intel_lynxpoint_config *cfg = dev->chip_info;
781 u16 pmbase = get_pmbase();
782
783 fadt->sci_int = 0x9;
784 fadt->smi_cmd = APM_CNT;
785 fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
786 fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
787 fadt->s4bios_req = 0x0;
788 fadt->pstate_cnt = 0;
789
790 fadt->pm1a_evt_blk = pmbase + PM1_STS;
791 fadt->pm1b_evt_blk = 0x0;
792 fadt->pm1a_cnt_blk = pmbase + PM1_CNT;
793 fadt->pm1b_cnt_blk = 0x0;
794 fadt->pm2_cnt_blk = pmbase + PM2_CNT;
795 fadt->pm_tmr_blk = pmbase + PM1_TMR;
796 if (pch_is_lp())
797 fadt->gpe0_blk = pmbase + LP_GPE0_STS_1;
798 else
799 fadt->gpe0_blk = pmbase + GPE0_STS;
800 fadt->gpe1_blk = 0;
801
802 /*
803 * Some of the lengths here are doubled. This is because they describe
804 * blocks containing two registers, where the size of each register
805 * is found by halving the block length. See Table 5-34 and section
806 * 4.8.3 of the ACPI specification for details.
807 */
808 fadt->pm1_evt_len = 2 * 2;
809 fadt->pm1_cnt_len = 2;
810 fadt->pm2_cnt_len = 1;
811 fadt->pm_tmr_len = 4;
812 if (pch_is_lp())
813 fadt->gpe0_blk_len = 2 * 16;
814 else
815 fadt->gpe0_blk_len = 2 * 8;
816 fadt->gpe1_blk_len = 0;
817 fadt->gpe1_base = 0;
818
819 fadt->cst_cnt = 0;
820 fadt->p_lvl2_lat = 1;
821 fadt->p_lvl3_lat = 87;
822 fadt->flush_size = 0;
823 fadt->flush_stride = 0;
824 fadt->duty_offset = 0;
825 fadt->duty_width = 0;
826 fadt->day_alrm = 0xd;
827 fadt->mon_alrm = 0x00;
828 fadt->century = 0x00;
829 fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
830
831 fadt->flags = ACPI_FADT_WBINVD |
832 ACPI_FADT_C1_SUPPORTED |
833 ACPI_FADT_C2_MP_SUPPORTED |
834 ACPI_FADT_SLEEP_BUTTON |
835 ACPI_FADT_RESET_REGISTER |
836 ACPI_FADT_SEALED_CASE |
837 ACPI_FADT_S4_RTC_WAKE |
838 ACPI_FADT_PLATFORM_CLOCK;
839
840 if (cfg->docking_supported)
841 fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED;
842
843 fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
844 fadt->reset_reg.bit_width = 8;
845 fadt->reset_reg.bit_offset = 0;
846 fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
847 fadt->reset_reg.addrl = 0xcf9;
848 fadt->reset_reg.addrh = 0;
849
850 fadt->reset_value = 6;
851
852 fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
853 fadt->x_pm1a_evt_blk.bit_width = 2 * 16;
854 fadt->x_pm1a_evt_blk.bit_offset = 0;
855 fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
856 fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS;
857 fadt->x_pm1a_evt_blk.addrh = 0x0;
858
859 fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
860 fadt->x_pm1b_evt_blk.bit_width = 0;
861 fadt->x_pm1b_evt_blk.bit_offset = 0;
862 fadt->x_pm1b_evt_blk.access_size = 0;
863 fadt->x_pm1b_evt_blk.addrl = 0x0;
864 fadt->x_pm1b_evt_blk.addrh = 0x0;
865
866 fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
867 fadt->x_pm1a_cnt_blk.bit_width = 16;
868 fadt->x_pm1a_cnt_blk.bit_offset = 0;
869 fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
870 fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT;
871 fadt->x_pm1a_cnt_blk.addrh = 0x0;
872
873 fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
874 fadt->x_pm1b_cnt_blk.bit_width = 0;
875 fadt->x_pm1b_cnt_blk.bit_offset = 0;
876 fadt->x_pm1b_cnt_blk.access_size = 0;
877 fadt->x_pm1b_cnt_blk.addrl = 0x0;
878 fadt->x_pm1b_cnt_blk.addrh = 0x0;
879
880 fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
881 fadt->x_pm2_cnt_blk.bit_width = 8;
882 fadt->x_pm2_cnt_blk.bit_offset = 0;
883 fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
884 fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT;
885 fadt->x_pm2_cnt_blk.addrh = 0x0;
886
887 fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
888 fadt->x_pm_tmr_blk.bit_width = 32;
889 fadt->x_pm_tmr_blk.bit_offset = 0;
890 fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
891 fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
892 fadt->x_pm_tmr_blk.addrh = 0x0;
893
894 /*
895 * We don't set `fadt->x_gpe0_blk` for Lynx Point LP since the correct
896 * bit width is 128 * 2, which is too large for an 8 bit unsigned int.
897 * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`.
898 */
899 if (!pch_is_lp()) {
900 fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
901 fadt->x_gpe0_blk.bit_width = 2 * 64;
902 fadt->x_gpe0_blk.bit_offset = 0;
903 fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
904 fadt->x_gpe0_blk.addrl = pmbase + GPE0_STS;
905 fadt->x_gpe0_blk.addrh = 0x0;
906 } else {
907 fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
908 fadt->x_gpe0_blk.bit_width = 0;
909 fadt->x_gpe0_blk.bit_offset = 0;
910 fadt->x_gpe0_blk.access_size = 0;
911 fadt->x_gpe0_blk.addrl = 0x0;
912 fadt->x_gpe0_blk.addrh = 0x0;
913 }
914
915 fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
916 fadt->x_gpe1_blk.bit_width = 0;
917 fadt->x_gpe1_blk.bit_offset = 0;
918 fadt->x_gpe1_blk.access_size = 0;
919 fadt->x_gpe1_blk.addrl = 0x0;
920 fadt->x_gpe1_blk.addrh = 0x0;
921}
922
Tristan Corrickf3127d42018-10-31 02:25:54 +1300923static const char *lpc_acpi_name(const struct device *dev)
924{
925 return "LPCB";
926}
927
928static void southbridge_fill_ssdt(struct device *dev)
929{
930 intel_acpi_gen_def_acpi_pirq(dev);
931}
932
Elyes HAOUAS7a5f7712018-06-08 17:20:38 +0200933static unsigned long southbridge_write_acpi_tables(struct device *device,
Alexander Couzens83fc32f2015-04-12 22:28:37 +0200934 unsigned long start,
935 struct acpi_rsdp *rsdp)
Vladimir Serbinenkoc6e566a2014-08-31 17:43:51 +0200936{
937 unsigned long current;
938 acpi_hpet_t *hpet;
939 acpi_header_t *ssdt;
940
941 current = start;
942
943 /* Align ACPI tables to 16byte */
Aaron Durbin07a1b282015-12-10 17:07:38 -0600944 current = acpi_align_current(current);
Vladimir Serbinenkoc6e566a2014-08-31 17:43:51 +0200945
946 /*
947 * We explicitly add these tables later on:
948 */
949 printk(BIOS_DEBUG, "ACPI: * HPET\n");
950
951 hpet = (acpi_hpet_t *) current;
952 current += sizeof(acpi_hpet_t);
Aaron Durbin07a1b282015-12-10 17:07:38 -0600953 current = acpi_align_current(current);
Vladimir Serbinenkoc6e566a2014-08-31 17:43:51 +0200954 acpi_create_intel_hpet(hpet);
955 acpi_add_table(rsdp, hpet);
956
Aaron Durbin07a1b282015-12-10 17:07:38 -0600957 current = acpi_align_current(current);
Vladimir Serbinenkoc6e566a2014-08-31 17:43:51 +0200958
959 printk(BIOS_DEBUG, "ACPI: * SSDT2\n");
960 ssdt = (acpi_header_t *)current;
961 acpi_create_serialio_ssdt(ssdt);
962 current += ssdt->length;
963 acpi_add_table(rsdp, ssdt);
Aaron Durbin07a1b282015-12-10 17:07:38 -0600964 current = acpi_align_current(current);
Vladimir Serbinenkoc6e566a2014-08-31 17:43:51 +0200965
966 printk(BIOS_DEBUG, "current = %lx\n", current);
967 return current;
968}
969
Tristan Corrick32ceed82018-11-30 22:53:27 +1300970static void lpc_final(struct device *dev)
971{
972 if (acpi_is_wakeup_s3() || IS_ENABLED(CONFIG_INTEL_CHIPSET_LOCKDOWN))
973 outb(APM_CNT_FINALIZE, APM_CNT);
974}
Vladimir Serbinenkoc6e566a2014-08-31 17:43:51 +0200975
Aaron Durbin76c37002012-10-30 09:03:43 -0500976static struct pci_operations pci_ops = {
977 .set_subsystem = set_subsystem,
978};
979
980static struct device_operations device_ops = {
981 .read_resources = pch_lpc_read_resources,
982 .set_resources = pci_dev_set_resources,
Duncan Laurie8d783b82013-05-14 11:16:34 -0700983 .enable_resources = pci_dev_enable_resources,
Tristan Corrickf3127d42018-10-31 02:25:54 +1300984 .acpi_fill_ssdt_generator = southbridge_fill_ssdt,
Vladimir Serbinenko334fd8e2014-10-05 11:10:35 +0200985 .acpi_inject_dsdt_generator = southbridge_inject_dsdt,
Tristan Corrickf3127d42018-10-31 02:25:54 +1300986 .acpi_name = lpc_acpi_name,
Vladimir Serbinenkoc6e566a2014-08-31 17:43:51 +0200987 .write_acpi_tables = southbridge_write_acpi_tables,
Aaron Durbin76c37002012-10-30 09:03:43 -0500988 .init = lpc_init,
Tristan Corrick32ceed82018-11-30 22:53:27 +1300989 .final = lpc_final,
Aaron Durbin76c37002012-10-30 09:03:43 -0500990 .enable = pch_lpc_enable,
Kyösti Mälkkid0e212c2015-02-26 20:47:47 +0200991 .scan_bus = scan_lpc_bus,
Aaron Durbin76c37002012-10-30 09:03:43 -0500992 .ops_pci = &pci_ops,
993};
994
995
Aaron Durbinc1989c42012-12-11 17:13:17 -0600996/* IDs for LPC device of Intel 8 Series Chipset (Lynx Point) */
997static const unsigned short pci_device_ids[] = {
998 0x8c41, /* Mobile Full Featured Engineering Sample. */
999 0x8c42, /* Desktop Full Featured Engineering Sample. */
1000 0x8c44, /* Z87 SKU */
1001 0x8c46, /* Z85 SKU */
1002 0x8c49, /* HM86 SKU */
1003 0x8c4a, /* H87 SKU */
1004 0x8c4b, /* HM87 SKU */
1005 0x8c4c, /* Q85 SKU */
1006 0x8c4e, /* Q87 SKU */
1007 0x8c4f, /* QM87 SKU */
Tristan Corrick9a085742018-10-31 02:20:28 +13001008 0x8c50, /* B85 SKU */
1009 0x8c52, /* C222 SKU */
1010 0x8c54, /* C224 SKU */
1011 0x8c56, /* C226 SKU */
1012 0x8c5c, /* H81 SKU */
Duncan Laurie74c0d052012-12-17 11:31:40 -08001013 0x9c41, /* LP Full Featured Engineering Sample */
1014 0x9c43, /* LP Premium SKU */
1015 0x9c45, /* LP Mainstream SKU */
1016 0x9c47, /* LP Value SKU */
Aaron Durbinc1989c42012-12-11 17:13:17 -06001017 0 };
Aaron Durbin76c37002012-10-30 09:03:43 -05001018
1019static const struct pci_driver pch_lpc __pci_driver = {
1020 .ops = &device_ops,
1021 .vendor = PCI_VENDOR_ID_INTEL,
1022 .devices = pci_device_ids,
1023};