Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 5 | * Copyright 2013 Google Inc. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of |
| 10 | * the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #include <console/console.h> |
| 19 | #include <device/device.h> |
| 20 | #include <device/pci.h> |
| 21 | #include <device/pci_ids.h> |
Patrick Rudolph | e56189c | 2018-04-18 10:11:59 +0200 | [diff] [blame] | 22 | #include <device/pci_ops.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 23 | #include <pc80/mc146818rtc.h> |
| 24 | #include <pc80/isa-dma.h> |
| 25 | #include <pc80/i8259.h> |
| 26 | #include <arch/io.h> |
| 27 | #include <arch/ioapic.h> |
| 28 | #include <arch/acpi.h> |
Elyes HAOUAS | d2b9ec1 | 2018-10-27 09:41:02 +0200 | [diff] [blame] | 29 | #include <arch/cpu.h> |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 30 | #include <cpu/x86/smm.h> |
Duncan Laurie | 9c07c8f | 2013-03-22 11:08:39 -0700 | [diff] [blame] | 31 | #include <cbmem.h> |
| 32 | #include <string.h> |
| 33 | #include "nvs.h" |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 34 | #include "pch.h" |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 35 | #include <arch/acpigen.h> |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 36 | #include <drivers/intel/gma/i915.h> |
Tristan Corrick | f3127d4 | 2018-10-31 02:25:54 +1300 | [diff] [blame] | 37 | #include <southbridge/intel/common/acpi_pirq_gen.h> |
Patrick Rudolph | 6b93112 | 2018-11-01 17:48:37 +0100 | [diff] [blame] | 38 | #include <southbridge/intel/common/rtc.h> |
Arthur Heymans | a3121b0 | 2019-05-28 13:46:49 +0200 | [diff] [blame^] | 39 | #include <southbridge/intel/common/spi.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 40 | |
| 41 | #define NMI_OFF 0 |
| 42 | |
| 43 | #define ENABLE_ACPI_MODE_IN_COREBOOT 0 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 44 | |
| 45 | typedef struct southbridge_intel_lynxpoint_config config_t; |
| 46 | |
Paul Menzel | 373a20c | 2013-05-03 12:17:02 +0200 | [diff] [blame] | 47 | /** |
| 48 | * Set miscellanous static southbridge features. |
| 49 | * |
| 50 | * @param dev PCI device with I/O APIC control registers |
| 51 | */ |
| 52 | static void pch_enable_ioapic(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 53 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 54 | u32 reg32; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 55 | |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 56 | /* Assign unique bus/dev/fn for I/O APIC */ |
| 57 | pci_write_config16(dev, LPC_IBDF, |
| 58 | PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3); |
| 59 | |
Paul Menzel | 373a20c | 2013-05-03 12:17:02 +0200 | [diff] [blame] | 60 | /* Enable ACPI I/O range decode */ |
| 61 | pci_write_config8(dev, ACPI_CNTL, ACPI_EN); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 62 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 63 | set_ioapic_id(VIO_APIC_VADDR, 0x02); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 64 | |
| 65 | /* affirm full set of redirection table entries ("write once") */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 66 | reg32 = io_apic_read(VIO_APIC_VADDR, 0x01); |
Duncan Laurie | c593999 | 2013-05-24 11:06:49 -0700 | [diff] [blame] | 67 | if (pch_is_lp()) { |
| 68 | /* PCH-LP has 39 redirection entries */ |
| 69 | reg32 &= ~0x00ff0000; |
| 70 | reg32 |= 0x00270000; |
| 71 | } |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 72 | io_apic_write(VIO_APIC_VADDR, 0x01, reg32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 73 | |
Paul Menzel | 373a20c | 2013-05-03 12:17:02 +0200 | [diff] [blame] | 74 | /* |
| 75 | * Select Boot Configuration register (0x03) and |
| 76 | * use Processor System Bus (0x01) to deliver interrupts. |
| 77 | */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 78 | io_apic_write(VIO_APIC_VADDR, 0x03, 0x01); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 79 | } |
| 80 | |
| 81 | static void pch_enable_serial_irqs(struct device *dev) |
| 82 | { |
| 83 | /* Set packet length and toggle silent mode bit for one frame. */ |
| 84 | pci_write_config8(dev, SERIRQ_CNTL, |
| 85 | (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 86 | #if !CONFIG(SERIRQ_CONTINUOUS_MODE) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 87 | pci_write_config8(dev, SERIRQ_CNTL, |
| 88 | (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); |
| 89 | #endif |
| 90 | } |
| 91 | |
| 92 | /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control |
| 93 | * 0x00 - 0000 = Reserved |
| 94 | * 0x01 - 0001 = Reserved |
| 95 | * 0x02 - 0010 = Reserved |
| 96 | * 0x03 - 0011 = IRQ3 |
| 97 | * 0x04 - 0100 = IRQ4 |
| 98 | * 0x05 - 0101 = IRQ5 |
| 99 | * 0x06 - 0110 = IRQ6 |
| 100 | * 0x07 - 0111 = IRQ7 |
| 101 | * 0x08 - 1000 = Reserved |
| 102 | * 0x09 - 1001 = IRQ9 |
| 103 | * 0x0A - 1010 = IRQ10 |
| 104 | * 0x0B - 1011 = IRQ11 |
| 105 | * 0x0C - 1100 = IRQ12 |
| 106 | * 0x0D - 1101 = Reserved |
| 107 | * 0x0E - 1110 = IRQ14 |
| 108 | * 0x0F - 1111 = IRQ15 |
| 109 | * PIRQ[n]_ROUT[7] - PIRQ Routing Control |
| 110 | * 0x80 - The PIRQ is not routed. |
| 111 | */ |
| 112 | |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 113 | static void pch_pirq_init(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 114 | { |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 115 | struct device *irq_dev; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 116 | /* Get the chip configuration */ |
| 117 | config_t *config = dev->chip_info; |
| 118 | |
| 119 | pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing); |
| 120 | pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing); |
| 121 | pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing); |
| 122 | pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing); |
| 123 | |
| 124 | pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing); |
| 125 | pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing); |
| 126 | pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing); |
| 127 | pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing); |
| 128 | |
| 129 | /* Eric Biederman once said we should let the OS do this. |
| 130 | * I am not so sure anymore he was right. |
| 131 | */ |
| 132 | |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 133 | for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 134 | u8 int_pin=0, int_line=0; |
| 135 | |
| 136 | if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) |
| 137 | continue; |
| 138 | |
| 139 | int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); |
| 140 | |
| 141 | switch (int_pin) { |
| 142 | case 1: /* INTA# */ int_line = config->pirqa_routing; break; |
| 143 | case 2: /* INTB# */ int_line = config->pirqb_routing; break; |
| 144 | case 3: /* INTC# */ int_line = config->pirqc_routing; break; |
| 145 | case 4: /* INTD# */ int_line = config->pirqd_routing; break; |
| 146 | } |
| 147 | |
| 148 | if (!int_line) |
| 149 | continue; |
| 150 | |
| 151 | pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); |
| 152 | } |
| 153 | } |
| 154 | |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 155 | static void pch_gpi_routing(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 156 | { |
| 157 | /* Get the chip configuration */ |
| 158 | config_t *config = dev->chip_info; |
| 159 | u32 reg32 = 0; |
| 160 | |
| 161 | /* An array would be much nicer here, or some |
| 162 | * other method of doing this. |
| 163 | */ |
| 164 | reg32 |= (config->gpi0_routing & 0x03) << 0; |
| 165 | reg32 |= (config->gpi1_routing & 0x03) << 2; |
| 166 | reg32 |= (config->gpi2_routing & 0x03) << 4; |
| 167 | reg32 |= (config->gpi3_routing & 0x03) << 6; |
| 168 | reg32 |= (config->gpi4_routing & 0x03) << 8; |
| 169 | reg32 |= (config->gpi5_routing & 0x03) << 10; |
| 170 | reg32 |= (config->gpi6_routing & 0x03) << 12; |
| 171 | reg32 |= (config->gpi7_routing & 0x03) << 14; |
| 172 | reg32 |= (config->gpi8_routing & 0x03) << 16; |
| 173 | reg32 |= (config->gpi9_routing & 0x03) << 18; |
| 174 | reg32 |= (config->gpi10_routing & 0x03) << 20; |
| 175 | reg32 |= (config->gpi11_routing & 0x03) << 22; |
| 176 | reg32 |= (config->gpi12_routing & 0x03) << 24; |
| 177 | reg32 |= (config->gpi13_routing & 0x03) << 26; |
| 178 | reg32 |= (config->gpi14_routing & 0x03) << 28; |
| 179 | reg32 |= (config->gpi15_routing & 0x03) << 30; |
| 180 | |
Kyösti Mälkki | b85a87b | 2014-12-29 11:32:27 +0200 | [diff] [blame] | 181 | pci_write_config32(dev, GPIO_ROUT, reg32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 182 | } |
| 183 | |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 184 | static void pch_power_options(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 185 | { |
| 186 | u8 reg8; |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 187 | u16 reg16; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 188 | u32 reg32; |
| 189 | const char *state; |
| 190 | /* Get the chip configuration */ |
| 191 | config_t *config = dev->chip_info; |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 192 | u16 pmbase = get_pmbase(); |
Nico Huber | 9faae2b | 2018-11-14 00:00:35 +0100 | [diff] [blame] | 193 | int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 194 | int nmi_option; |
| 195 | |
| 196 | /* Which state do we want to goto after g3 (power restored)? |
| 197 | * 0 == S0 Full On |
| 198 | * 1 == S5 Soft Off |
| 199 | * |
| 200 | * If the option is not existent (Laptops), use Kconfig setting. |
| 201 | */ |
| 202 | get_option(&pwr_on, "power_on_after_fail"); |
| 203 | |
| 204 | reg16 = pci_read_config16(dev, GEN_PMCON_3); |
| 205 | reg16 &= 0xfffe; |
| 206 | switch (pwr_on) { |
| 207 | case MAINBOARD_POWER_OFF: |
| 208 | reg16 |= 1; |
| 209 | state = "off"; |
| 210 | break; |
| 211 | case MAINBOARD_POWER_ON: |
| 212 | reg16 &= ~1; |
| 213 | state = "on"; |
| 214 | break; |
| 215 | case MAINBOARD_POWER_KEEP: |
| 216 | reg16 &= ~1; |
| 217 | state = "state keep"; |
| 218 | break; |
| 219 | default: |
| 220 | state = "undefined"; |
| 221 | } |
| 222 | |
| 223 | reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */ |
| 224 | reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */ |
| 225 | |
| 226 | reg16 &= ~(1 << 10); |
| 227 | reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */ |
| 228 | |
| 229 | reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */ |
| 230 | |
| 231 | pci_write_config16(dev, GEN_PMCON_3, reg16); |
| 232 | printk(BIOS_INFO, "Set power %s after power failure.\n", state); |
| 233 | |
| 234 | /* Set up NMI on errors. */ |
| 235 | reg8 = inb(0x61); |
| 236 | reg8 &= 0x0f; /* Higher Nibble must be 0 */ |
| 237 | reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */ |
| 238 | // reg8 &= ~(1 << 2); /* PCI SERR# Enable */ |
| 239 | reg8 |= (1 << 2); /* PCI SERR# Disable for now */ |
| 240 | outb(reg8, 0x61); |
| 241 | |
| 242 | reg8 = inb(0x70); |
| 243 | nmi_option = NMI_OFF; |
| 244 | get_option(&nmi_option, "nmi"); |
| 245 | if (nmi_option) { |
| 246 | printk(BIOS_INFO, "NMI sources enabled.\n"); |
| 247 | reg8 &= ~(1 << 7); /* Set NMI. */ |
| 248 | } else { |
| 249 | printk(BIOS_INFO, "NMI sources disabled.\n"); |
Elyes HAOUAS | 9c5d463 | 2018-04-26 22:21:21 +0200 | [diff] [blame] | 250 | reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 251 | } |
| 252 | outb(reg8, 0x70); |
| 253 | |
| 254 | /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */ |
| 255 | reg16 = pci_read_config16(dev, GEN_PMCON_1); |
| 256 | reg16 &= ~(3 << 0); // SMI# rate 1 minute |
| 257 | reg16 &= ~(1 << 10); // Disable BIOS_PCI_EXP_EN for native PME |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 258 | pci_write_config16(dev, GEN_PMCON_1, reg16); |
| 259 | |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 260 | /* |
| 261 | * Set the board's GPI routing on LynxPoint-H. |
| 262 | * This is done as part of GPIO configuration on LynxPoint-LP. |
| 263 | */ |
| 264 | if (pch_is_lp()) |
| 265 | pch_gpi_routing(dev); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 266 | |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 267 | /* GPE setup based on device tree configuration */ |
| 268 | enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2, |
| 269 | config->gpe0_en_3, config->gpe0_en_4); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 270 | |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 271 | /* SMI setup based on device tree configuration */ |
| 272 | enable_alt_smi(config->alt_gp_smi_en); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 273 | |
| 274 | /* Set up power management block and determine sleep mode */ |
| 275 | reg32 = inl(pmbase + 0x04); // PM1_CNT |
| 276 | reg32 &= ~(7 << 10); // SLP_TYP |
| 277 | reg32 |= (1 << 0); // SCI_EN |
| 278 | outl(reg32, pmbase + 0x04); |
| 279 | |
| 280 | /* Clear magic status bits to prevent unexpected wake */ |
| 281 | reg32 = RCBA32(0x3310); |
| 282 | reg32 |= (1 << 4)|(1 << 5)|(1 << 0); |
| 283 | RCBA32(0x3310) = reg32; |
| 284 | |
Ryan Salsamendi | 889ce9c | 2017-06-30 17:45:14 -0700 | [diff] [blame] | 285 | reg16 = RCBA16(0x3f02); |
| 286 | reg16 &= ~0xf; |
| 287 | RCBA16(0x3f02) = reg16; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 288 | } |
| 289 | |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 290 | /* LynxPoint PCH Power Management init */ |
| 291 | static void lpt_pm_init(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 292 | { |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 293 | printk(BIOS_DEBUG, "LynxPoint PM init\n"); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 294 | } |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 295 | |
| 296 | const struct rcba_config_instruction lpt_lp_pm_rcba[] = { |
Duncan Laurie | 4bc107b | 2013-06-24 13:14:44 -0700 | [diff] [blame] | 297 | RCBA_RMW_REG_32(0x232c, ~1, 0x00000000), |
| 298 | RCBA_RMW_REG_32(0x1100, ~0xc000, 0xc000), |
| 299 | RCBA_RMW_REG_32(0x1100, ~0, 0x00000100), |
| 300 | RCBA_RMW_REG_32(0x1100, ~0, 0x0000003f), |
| 301 | RCBA_RMW_REG_32(0x2320, ~0x60, 0x10), |
| 302 | RCBA_RMW_REG_32(0x3314, 0, 0x00012fff), |
| 303 | RCBA_RMW_REG_32(0x3318, 0, 0x0dcf0400), |
| 304 | RCBA_RMW_REG_32(0x3324, 0, 0x04000000), |
| 305 | RCBA_RMW_REG_32(0x3368, 0, 0x00041400), |
| 306 | RCBA_RMW_REG_32(0x3388, 0, 0x3f8ddbff), |
| 307 | RCBA_RMW_REG_32(0x33ac, 0, 0x00007001), |
| 308 | RCBA_RMW_REG_32(0x33b0, 0, 0x00181900), |
| 309 | RCBA_RMW_REG_32(0x33c0, 0, 0x00060A00), |
| 310 | RCBA_RMW_REG_32(0x33d0, 0, 0x06200840), |
| 311 | RCBA_RMW_REG_32(0x3a28, 0, 0x01010101), |
| 312 | RCBA_RMW_REG_32(0x3a2c, 0, 0x04040404), |
| 313 | RCBA_RMW_REG_32(0x2b1c, 0, 0x03808033), |
| 314 | RCBA_RMW_REG_32(0x2b34, 0, 0x80000009), |
| 315 | RCBA_RMW_REG_32(0x3348, 0, 0x022ddfff), |
| 316 | RCBA_RMW_REG_32(0x334c, 0, 0x00000001), |
| 317 | RCBA_RMW_REG_32(0x3358, 0, 0x0001c000), |
| 318 | RCBA_RMW_REG_32(0x3380, 0, 0x3f8ddbff), |
| 319 | RCBA_RMW_REG_32(0x3384, 0, 0x0001c7e1), |
| 320 | RCBA_RMW_REG_32(0x338c, 0, 0x0001c7e1), |
| 321 | RCBA_RMW_REG_32(0x3398, 0, 0x0001c000), |
| 322 | RCBA_RMW_REG_32(0x33a8, 0, 0x00181900), |
| 323 | RCBA_RMW_REG_32(0x33dc, 0, 0x00080000), |
| 324 | RCBA_RMW_REG_32(0x33e0, 0, 0x00000001), |
| 325 | RCBA_RMW_REG_32(0x3a20, 0, 0x00000404), |
| 326 | RCBA_RMW_REG_32(0x3a24, 0, 0x01010101), |
| 327 | RCBA_RMW_REG_32(0x3a30, 0, 0x01010101), |
| 328 | RCBA_RMW_REG_32(0x0410, ~0, 0x00000003), |
| 329 | RCBA_RMW_REG_32(0x2618, ~0, 0x08000000), |
| 330 | RCBA_RMW_REG_32(0x2300, ~0, 0x00000002), |
| 331 | RCBA_RMW_REG_32(0x2600, ~0, 0x00000008), |
| 332 | RCBA_RMW_REG_32(0x33b4, 0, 0x00007001), |
| 333 | RCBA_RMW_REG_32(0x3350, 0, 0x022ddfff), |
| 334 | RCBA_RMW_REG_32(0x3354, 0, 0x00000001), |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 335 | RCBA_RMW_REG_32(0x33d4, ~0, 0x08000000), /* Power Optimizer */ |
Matt DeVillier | c97e042 | 2017-02-16 11:36:16 -0600 | [diff] [blame] | 336 | RCBA_RMW_REG_32(0x33c8, ~0, 0x00000080), /* Power Optimizer */ |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 337 | RCBA_RMW_REG_32(0x2b10, 0, 0x0000883c), /* Power Optimizer */ |
Duncan Laurie | 5cf34ce | 2013-04-26 10:41:33 -0700 | [diff] [blame] | 338 | RCBA_RMW_REG_32(0x2b14, 0, 0x1e0a4616), /* Power Optimizer */ |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 339 | RCBA_RMW_REG_32(0x2b24, 0, 0x40000005), /* Power Optimizer */ |
| 340 | RCBA_RMW_REG_32(0x2b20, 0, 0x0005db01), /* Power Optimizer */ |
Duncan Laurie | 4bc107b | 2013-06-24 13:14:44 -0700 | [diff] [blame] | 341 | RCBA_RMW_REG_32(0x3a80, 0, 0x05145005), |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 342 | RCBA_END_CONFIG |
| 343 | }; |
| 344 | |
| 345 | /* LynxPoint LP PCH Power Management init */ |
| 346 | static void lpt_lp_pm_init(struct device *dev) |
| 347 | { |
| 348 | struct southbridge_intel_lynxpoint_config *config = dev->chip_info; |
| 349 | u32 data; |
| 350 | |
| 351 | printk(BIOS_DEBUG, "LynxPoint LP PM init\n"); |
| 352 | |
| 353 | pci_write_config8(dev, 0xa9, 0x46); |
| 354 | |
| 355 | pch_config_rcba(lpt_lp_pm_rcba); |
| 356 | |
| 357 | pci_write_config32(dev, 0xac, |
| 358 | pci_read_config32(dev, 0xac) | (1 << 21)); |
| 359 | |
Elyes HAOUAS | a0aea56 | 2017-07-03 21:38:53 +0200 | [diff] [blame] | 360 | pch_iobp_update(0xED00015C, ~(1 << 11), 0x00003700); |
Duncan Laurie | 4bc107b | 2013-06-24 13:14:44 -0700 | [diff] [blame] | 361 | pch_iobp_update(0xED000118, ~0UL, 0x00c00000); |
| 362 | pch_iobp_update(0xED000120, ~0UL, 0x00240000); |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 363 | pch_iobp_update(0xCA000000, ~0UL, 0x00000009); |
| 364 | |
| 365 | /* Set RCBA CIR28 0x3A84 based on SATA port enables */ |
| 366 | data = 0x00001005; |
| 367 | /* Port 3 and 2 disabled */ |
| 368 | if ((config->sata_port_map & ((1 << 3)|(1 << 2))) == 0) |
| 369 | data |= (1 << 24) | (1 << 26); |
| 370 | /* Port 1 and 0 disabled */ |
| 371 | if ((config->sata_port_map & ((1 << 1)|(1 << 0))) == 0) |
| 372 | data |= (1 << 20) | (1 << 18); |
| 373 | RCBA32(0x3a84) = data; |
| 374 | |
Duncan Laurie | 5cf34ce | 2013-04-26 10:41:33 -0700 | [diff] [blame] | 375 | /* Set RCBA 0x2b1c[29]=1 if DSP disabled */ |
| 376 | if (RCBA32(FD) & PCH_DISABLE_ADSPD) |
| 377 | RCBA32_OR(0x2b1c, (1 << 29)); |
| 378 | |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 379 | /* Lock */ |
| 380 | RCBA32_OR(0x3a6c, 0x00000001); |
| 381 | |
| 382 | /* Set RCBA 0x33D4 after other setup */ |
| 383 | RCBA32_OR(0x33d4, 0x2fff2fb1); |
| 384 | |
| 385 | /* Set RCBA 0x33C8[15]=1 as last step */ |
| 386 | RCBA32_OR(0x33c8, (1 << 15)); |
| 387 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 388 | |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 389 | static void enable_hpet(struct device *const dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 390 | { |
| 391 | u32 reg32; |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 392 | size_t i; |
| 393 | |
| 394 | /* Assign unique bus/dev/fn for each HPET */ |
| 395 | for (i = 0; i < 8; ++i) |
| 396 | pci_write_config16(dev, LPC_HnBDF(i), |
| 397 | PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | i); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 398 | |
| 399 | /* Move HPET to default address 0xfed00000 and enable it */ |
| 400 | reg32 = RCBA32(HPTC); |
| 401 | reg32 |= (1 << 7); // HPET Address Enable |
| 402 | reg32 &= ~(3 << 0); |
| 403 | RCBA32(HPTC) = reg32; |
| 404 | /* Read it back to stick. It's affected by posted write syndrome. */ |
| 405 | reg32 = RCBA32(HPTC); |
| 406 | } |
| 407 | |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 408 | static void enable_clock_gating(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 409 | { |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 410 | /* LynxPoint Mobile */ |
| 411 | u32 reg32; |
| 412 | u16 reg16; |
| 413 | |
| 414 | /* DMI */ |
| 415 | RCBA32_AND_OR(0x2234, ~0UL, 0xf); |
| 416 | reg16 = pci_read_config16(dev, GEN_PMCON_1); |
| 417 | reg16 |= (1 << 11) | (1 << 12) | (1 << 14); |
| 418 | reg16 |= (1 << 2); // PCI CLKRUN# Enable |
| 419 | pci_write_config16(dev, GEN_PMCON_1, reg16); |
| 420 | RCBA32_OR(0x900, (1 << 14)); |
| 421 | |
| 422 | reg32 = RCBA32(CG); |
| 423 | reg32 |= (1 << 22); // HDA Dynamic |
Ryan Salsamendi | 0d9b360 | 2017-06-30 17:15:57 -0700 | [diff] [blame] | 424 | reg32 |= (1UL << 31); // LPC Dynamic |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 425 | reg32 |= (1 << 16); // PCIe Dynamic |
| 426 | reg32 |= (1 << 27); // HPET Dynamic |
| 427 | reg32 |= (1 << 28); // GPIO Dynamic |
| 428 | RCBA32(CG) = reg32; |
| 429 | |
| 430 | RCBA32_OR(0x38c0, 0x7); // SPI Dynamic |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 431 | } |
| 432 | |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 433 | static void enable_lp_clock_gating(struct device *dev) |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 434 | { |
| 435 | /* LynxPoint LP */ |
| 436 | u32 reg32; |
| 437 | u16 reg16; |
| 438 | |
| 439 | /* DMI */ |
| 440 | RCBA32_AND_OR(0x2234, ~0UL, 0xf); |
| 441 | reg16 = pci_read_config16(dev, GEN_PMCON_1); |
| 442 | reg16 &= ~((1 << 11) | (1 << 14)); |
| 443 | reg16 |= (1 << 5) | (1 << 6) | (1 << 7) | (1 << 12) | (1 << 13); |
| 444 | reg16 |= (1 << 2); // PCI CLKRUN# Enable |
| 445 | pci_write_config16(dev, GEN_PMCON_1, reg16); |
| 446 | |
| 447 | reg32 = pci_read_config32(dev, 0x64); |
| 448 | reg32 |= (1 << 6); |
| 449 | pci_write_config32(dev, 0x64, reg32); |
| 450 | |
Duncan Laurie | 4bc107b | 2013-06-24 13:14:44 -0700 | [diff] [blame] | 451 | /* |
| 452 | * RCBA + 0x2614[27:25,14:13,10,8] = 101,11,1,1 |
| 453 | * RCBA + 0x2614[23:16] = 0x20 |
| 454 | * RCBA + 0x2614[30:28] = 0x0 |
Duncan Laurie | d8c7d73 | 2013-07-16 09:01:43 -0700 | [diff] [blame] | 455 | * RCBA + 0x2614[26] = 1 (IF 0:2.0@0x08 >= 0x0b) |
Duncan Laurie | 4bc107b | 2013-06-24 13:14:44 -0700 | [diff] [blame] | 456 | */ |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 457 | RCBA32_AND_OR(0x2614, 0x8bffffff, 0x0a206500); |
Duncan Laurie | 4bc107b | 2013-06-24 13:14:44 -0700 | [diff] [blame] | 458 | |
| 459 | /* Check for LPT-LP B2 stepping and 0:31.0@0xFA > 4 */ |
Nico Huber | 744d6bd | 2019-01-12 14:58:20 +0100 | [diff] [blame] | 460 | struct device *const gma = pcidev_on_root(2, 0); |
| 461 | if (gma && pci_read_config8(gma, 0x8) >= 0x0b) |
Elyes HAOUAS | a0aea56 | 2017-07-03 21:38:53 +0200 | [diff] [blame] | 462 | RCBA32_OR(0x2614, (1 << 26)); |
Duncan Laurie | 4bc107b | 2013-06-24 13:14:44 -0700 | [diff] [blame] | 463 | |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 464 | RCBA32_OR(0x900, 0x0000031f); |
| 465 | |
| 466 | reg32 = RCBA32(CG); |
Duncan Laurie | a2d6a40 | 2013-03-22 11:24:45 -0700 | [diff] [blame] | 467 | if (RCBA32(0x3454) & (1 << 4)) |
| 468 | reg32 &= ~(1 << 29); // LPC Dynamic |
| 469 | else |
| 470 | reg32 |= (1 << 29); // LPC Dynamic |
Ryan Salsamendi | 3f2fe18 | 2017-07-04 13:14:16 -0700 | [diff] [blame] | 471 | reg32 |= (1UL << 31); // LP LPC |
Duncan Laurie | 5cf34ce | 2013-04-26 10:41:33 -0700 | [diff] [blame] | 472 | reg32 |= (1 << 30); // LP BLA |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 473 | reg32 |= (1 << 28); // GPIO Dynamic |
| 474 | reg32 |= (1 << 27); // HPET Dynamic |
Duncan Laurie | 5cf34ce | 2013-04-26 10:41:33 -0700 | [diff] [blame] | 475 | reg32 |= (1 << 26); // Generic Platform Event Clock |
| 476 | if (RCBA32(BUC) & PCH_DISABLE_GBE) |
| 477 | reg32 |= (1 << 23); // GbE Static |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 478 | reg32 |= (1 << 22); // HDA Dynamic |
Duncan Laurie | 5cf34ce | 2013-04-26 10:41:33 -0700 | [diff] [blame] | 479 | reg32 |= (1 << 16); // PCI Dynamic |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 480 | RCBA32(CG) = reg32; |
| 481 | |
| 482 | RCBA32_OR(0x3434, 0x7); // LP LPC |
| 483 | |
| 484 | RCBA32_AND_OR(0x333c, 0xffcfffff, 0x00c00000); // SATA |
| 485 | |
| 486 | RCBA32_OR(0x38c0, 0x3c07); // SPI Dynamic |
| 487 | |
| 488 | pch_iobp_update(0xCF000000, ~0UL, 0x00007001); |
Duncan Laurie | 5cf34ce | 2013-04-26 10:41:33 -0700 | [diff] [blame] | 489 | pch_iobp_update(0xCE00C000, ~1UL, 0x00000000); // bit0=0 in BWG 1.4.0 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 490 | } |
| 491 | |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 492 | static void pch_set_acpi_mode(void) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 493 | { |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 494 | #if CONFIG(HAVE_SMI_HANDLER) |
Kyösti Mälkki | c3ed886 | 2014-06-19 19:50:51 +0300 | [diff] [blame] | 495 | if (!acpi_is_wakeup_s3()) { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 496 | #if ENABLE_ACPI_MODE_IN_COREBOOT |
| 497 | printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 498 | outb(APM_CNT_ACPI_ENABLE, APM_CNT); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 499 | printk(BIOS_DEBUG, "done.\n"); |
| 500 | #else |
| 501 | printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 502 | outb(APM_CNT_ACPI_DISABLE, APM_CNT); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 503 | printk(BIOS_DEBUG, "done.\n"); |
| 504 | #endif |
| 505 | } |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 506 | #endif /* CONFIG_HAVE_SMI_HANDLER */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 507 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 508 | |
| 509 | static void pch_disable_smm_only_flashing(struct device *dev) |
| 510 | { |
| 511 | u8 reg8; |
| 512 | |
| 513 | printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); |
Elyes HAOUAS | 0c22d2f | 2018-12-01 12:19:52 +0100 | [diff] [blame] | 514 | reg8 = pci_read_config8(dev, BIOS_CNTL); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 515 | reg8 &= ~(1 << 5); |
Elyes HAOUAS | 0c22d2f | 2018-12-01 12:19:52 +0100 | [diff] [blame] | 516 | pci_write_config8(dev, BIOS_CNTL, reg8); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 517 | } |
| 518 | |
| 519 | static void pch_fixups(struct device *dev) |
| 520 | { |
| 521 | u8 gen_pmcon_2; |
| 522 | |
| 523 | /* Indicate DRAM init done for MRC S3 to know it can resume */ |
| 524 | gen_pmcon_2 = pci_read_config8(dev, GEN_PMCON_2); |
| 525 | gen_pmcon_2 |= (1 << 7); |
| 526 | pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2); |
| 527 | |
| 528 | /* |
| 529 | * Enable DMI ASPM in the PCH |
| 530 | */ |
| 531 | RCBA32_AND_OR(0x2304, ~(1 << 10), 0); |
| 532 | RCBA32_OR(0x21a4, (1 << 11)|(1 << 10)); |
| 533 | RCBA32_OR(0x21a8, 0x3); |
| 534 | } |
| 535 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 536 | static void lpc_init(struct device *dev) |
| 537 | { |
| 538 | printk(BIOS_DEBUG, "pch: lpc_init\n"); |
| 539 | |
| 540 | /* Set the value for PCI command register. */ |
| 541 | pci_write_config16(dev, PCI_COMMAND, 0x000f); |
| 542 | |
| 543 | /* IO APIC initialization. */ |
Paul Menzel | 373a20c | 2013-05-03 12:17:02 +0200 | [diff] [blame] | 544 | pch_enable_ioapic(dev); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 545 | |
| 546 | pch_enable_serial_irqs(dev); |
| 547 | |
| 548 | /* Setup the PIRQ. */ |
| 549 | pch_pirq_init(dev); |
| 550 | |
| 551 | /* Setup power options. */ |
| 552 | pch_power_options(dev); |
| 553 | |
| 554 | /* Initialize power management */ |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 555 | if (pch_is_lp()) { |
| 556 | lpt_lp_pm_init(dev); |
| 557 | enable_lp_clock_gating(dev); |
| 558 | } else { |
| 559 | lpt_pm_init(dev); |
| 560 | enable_clock_gating(dev); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 561 | } |
| 562 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 563 | /* Initialize the real time clock. */ |
Patrick Rudolph | 6b93112 | 2018-11-01 17:48:37 +0100 | [diff] [blame] | 564 | sb_rtc_init(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 565 | |
| 566 | /* Initialize ISA DMA. */ |
| 567 | isa_dma_init(); |
| 568 | |
| 569 | /* Initialize the High Precision Event Timers, if present. */ |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 570 | enable_hpet(dev); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 571 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 572 | setup_i8259(); |
| 573 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 574 | /* Interrupt 9 should be level triggered (SCI) */ |
| 575 | i8259_configure_irq_trigger(9, 1); |
| 576 | |
| 577 | pch_disable_smm_only_flashing(dev); |
| 578 | |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 579 | pch_set_acpi_mode(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 580 | |
| 581 | pch_fixups(dev); |
| 582 | } |
| 583 | |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 584 | static void pch_lpc_add_mmio_resources(struct device *dev) |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 585 | { |
| 586 | u32 reg; |
| 587 | struct resource *res; |
| 588 | const u32 default_decode_base = IO_APIC_ADDR; |
| 589 | |
| 590 | /* |
| 591 | * Just report all resources from IO-APIC base to 4GiB. Don't mark |
| 592 | * them reserved as that may upset the OS if this range is marked |
| 593 | * as reserved in the e820. |
| 594 | */ |
| 595 | res = new_resource(dev, OIC); |
| 596 | res->base = default_decode_base; |
| 597 | res->size = 0 - default_decode_base; |
| 598 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 599 | |
| 600 | /* RCBA */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 601 | if ((uintptr_t)DEFAULT_RCBA < default_decode_base) { |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 602 | res = new_resource(dev, RCBA); |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 603 | res->base = (resource_t)(uintptr_t)DEFAULT_RCBA; |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 604 | res->size = 16 * 1024; |
| 605 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | |
| 606 | IORESOURCE_FIXED | IORESOURCE_RESERVE; |
| 607 | } |
| 608 | |
| 609 | /* Check LPC Memory Decode register. */ |
| 610 | reg = pci_read_config32(dev, LGMR); |
| 611 | if (reg & 1) { |
| 612 | reg &= ~0xffff; |
| 613 | if (reg < default_decode_base) { |
| 614 | res = new_resource(dev, LGMR); |
| 615 | res->base = reg; |
| 616 | res->size = 16 * 1024; |
| 617 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | |
| 618 | IORESOURCE_FIXED | IORESOURCE_RESERVE; |
| 619 | } |
| 620 | } |
| 621 | } |
| 622 | |
| 623 | /* Default IO range claimed by the LPC device. The upper bound is exclusive. */ |
| 624 | #define LPC_DEFAULT_IO_RANGE_LOWER 0 |
| 625 | #define LPC_DEFAULT_IO_RANGE_UPPER 0x1000 |
| 626 | |
Julius Werner | 7c712bb | 2019-05-01 16:51:20 -0700 | [diff] [blame] | 627 | static inline int pch_io_range_in_default(int base, int size) |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 628 | { |
| 629 | /* Does it start above the range? */ |
| 630 | if (base >= LPC_DEFAULT_IO_RANGE_UPPER) |
| 631 | return 0; |
| 632 | |
| 633 | /* Is it entirely contained? */ |
| 634 | if (base >= LPC_DEFAULT_IO_RANGE_LOWER && |
| 635 | (base + size) < LPC_DEFAULT_IO_RANGE_UPPER) |
| 636 | return 1; |
| 637 | |
| 638 | /* This will return not in range for partial overlaps. */ |
| 639 | return 0; |
| 640 | } |
| 641 | |
| 642 | /* |
| 643 | * Note: this function assumes there is no overlap with the default LPC device's |
| 644 | * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. |
| 645 | */ |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 646 | static void pch_lpc_add_io_resource(struct device *dev, u16 base, u16 size, |
| 647 | int index) |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 648 | { |
| 649 | struct resource *res; |
| 650 | |
| 651 | if (pch_io_range_in_default(base, size)) |
| 652 | return; |
| 653 | |
| 654 | res = new_resource(dev, index); |
| 655 | res->base = base; |
| 656 | res->size = size; |
| 657 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 658 | } |
| 659 | |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 660 | static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value, |
| 661 | int index) |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 662 | { |
| 663 | /* |
| 664 | * Check if the register is enabled. If so and the base exceeds the |
Kyösti Mälkki | b544c00 | 2019-01-06 10:41:41 +0200 | [diff] [blame] | 665 | * device's default, claim range and add the resource. |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 666 | */ |
| 667 | if (reg_value & 1) { |
| 668 | u16 base = reg_value & 0xfffc; |
| 669 | u16 size = (0x3 | ((reg_value >> 16) & 0xfc)) + 1; |
| 670 | pch_lpc_add_io_resource(dev, base, size, index); |
| 671 | } |
| 672 | } |
| 673 | |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 674 | static void pch_lpc_add_io_resources(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 675 | { |
| 676 | struct resource *res; |
| 677 | config_t *config = dev->chip_info; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 678 | |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 679 | /* Add the default claimed IO range for the LPC device. */ |
| 680 | res = new_resource(dev, 0); |
| 681 | res->base = LPC_DEFAULT_IO_RANGE_LOWER; |
| 682 | res->size = LPC_DEFAULT_IO_RANGE_UPPER - LPC_DEFAULT_IO_RANGE_LOWER; |
| 683 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 684 | |
| 685 | /* GPIOBASE */ |
Duncan Laurie | 7922b46 | 2013-03-08 16:34:33 -0800 | [diff] [blame] | 686 | pch_lpc_add_io_resource(dev, get_gpiobase(), DEFAULT_GPIOSIZE, |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 687 | GPIO_BASE); |
| 688 | |
| 689 | /* PMBASE */ |
Duncan Laurie | 7922b46 | 2013-03-08 16:34:33 -0800 | [diff] [blame] | 690 | pch_lpc_add_io_resource(dev, get_pmbase(), 256, PMBASE); |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 691 | |
| 692 | /* LPC Generic IO Decode range. */ |
| 693 | pch_lpc_add_gen_io_resources(dev, config->gen1_dec, LPC_GEN1_DEC); |
| 694 | pch_lpc_add_gen_io_resources(dev, config->gen2_dec, LPC_GEN2_DEC); |
| 695 | pch_lpc_add_gen_io_resources(dev, config->gen3_dec, LPC_GEN3_DEC); |
| 696 | pch_lpc_add_gen_io_resources(dev, config->gen4_dec, LPC_GEN4_DEC); |
| 697 | } |
| 698 | |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 699 | static void pch_lpc_read_resources(struct device *dev) |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 700 | { |
Duncan Laurie | 9c07c8f | 2013-03-22 11:08:39 -0700 | [diff] [blame] | 701 | global_nvs_t *gnvs; |
| 702 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 703 | /* Get the normal PCI resources of this device. */ |
| 704 | pci_dev_read_resources(dev); |
| 705 | |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 706 | /* Add non-standard MMIO resources. */ |
| 707 | pch_lpc_add_mmio_resources(dev); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 708 | |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 709 | /* Add IO resources. */ |
| 710 | pch_lpc_add_io_resources(dev); |
Duncan Laurie | 9c07c8f | 2013-03-22 11:08:39 -0700 | [diff] [blame] | 711 | |
| 712 | /* Allocate ACPI NVS in CBMEM */ |
| 713 | gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); |
Kyösti Mälkki | c3ed886 | 2014-06-19 19:50:51 +0300 | [diff] [blame] | 714 | if (!acpi_is_wakeup_s3() && gnvs) |
Duncan Laurie | 9c07c8f | 2013-03-22 11:08:39 -0700 | [diff] [blame] | 715 | memset(gnvs, 0, sizeof(global_nvs_t)); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 716 | } |
| 717 | |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 718 | static void pch_lpc_enable(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 719 | { |
| 720 | /* Enable PCH Display Port */ |
| 721 | RCBA16(DISPBDF) = 0x0010; |
| 722 | RCBA32_OR(FD2, PCH_ENABLE_DBDF); |
| 723 | |
| 724 | pch_enable(dev); |
| 725 | } |
| 726 | |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 727 | static void southbridge_inject_dsdt(struct device *dev) |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 728 | { |
Vladimir Serbinenko | 7309c64 | 2014-10-05 11:07:33 +0200 | [diff] [blame] | 729 | global_nvs_t *gnvs; |
| 730 | |
| 731 | gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 732 | if (!gnvs) { |
Elyes HAOUAS | 035df00 | 2016-10-03 21:54:16 +0200 | [diff] [blame] | 733 | gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); |
Vladimir Serbinenko | 7309c64 | 2014-10-05 11:07:33 +0200 | [diff] [blame] | 734 | if (gnvs) |
| 735 | memset(gnvs, 0, sizeof(*gnvs)); |
| 736 | } |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 737 | |
| 738 | if (gnvs) { |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 739 | const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); |
| 740 | |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 741 | acpi_create_gnvs(gnvs); |
Vladimir Serbinenko | 1b409fd | 2014-10-12 00:26:21 +0200 | [diff] [blame] | 742 | |
| 743 | gnvs->apic = 1; |
| 744 | gnvs->mpen = 1; /* Enable Multi Processing */ |
| 745 | gnvs->pcnt = dev_count_cpu(); |
| 746 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 747 | #if CONFIG(CHROMEOS) |
Joel Kitching | 6fbd874 | 2018-08-23 14:56:25 +0800 | [diff] [blame] | 748 | chromeos_init_chromeos_acpi(&(gnvs->chromeos)); |
Vladimir Serbinenko | 1b409fd | 2014-10-12 00:26:21 +0200 | [diff] [blame] | 749 | #endif |
| 750 | |
| 751 | /* Update the mem console pointer. */ |
| 752 | gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); |
| 753 | |
Nico Huber | 744d6bd | 2019-01-12 14:58:20 +0100 | [diff] [blame] | 754 | if (gfx) { |
| 755 | gnvs->ndid = gfx->ndid; |
| 756 | memcpy(gnvs->did, gfx->did, sizeof(gnvs->did)); |
| 757 | } |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 758 | |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 759 | /* And tell SMI about it */ |
| 760 | smm_setup_structures(gnvs, NULL, NULL); |
| 761 | |
Vladimir Serbinenko | 334fd8e | 2014-10-05 11:10:35 +0200 | [diff] [blame] | 762 | /* Add it to DSDT. */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 763 | acpigen_write_scope("\\"); |
| 764 | acpigen_write_name_dword("NVSA", (u32) gnvs); |
| 765 | acpigen_pop_len(); |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 766 | } |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 767 | } |
| 768 | |
Tristan Corrick | b2632ce | 2018-10-31 02:28:13 +1300 | [diff] [blame] | 769 | void acpi_fill_fadt(acpi_fadt_t *fadt) |
| 770 | { |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 771 | struct device *dev = pcidev_on_root(0x1f, 0); |
Tristan Corrick | b2632ce | 2018-10-31 02:28:13 +1300 | [diff] [blame] | 772 | struct southbridge_intel_lynxpoint_config *cfg = dev->chip_info; |
| 773 | u16 pmbase = get_pmbase(); |
| 774 | |
| 775 | fadt->sci_int = 0x9; |
| 776 | fadt->smi_cmd = APM_CNT; |
| 777 | fadt->acpi_enable = APM_CNT_ACPI_ENABLE; |
| 778 | fadt->acpi_disable = APM_CNT_ACPI_DISABLE; |
| 779 | fadt->s4bios_req = 0x0; |
| 780 | fadt->pstate_cnt = 0; |
| 781 | |
| 782 | fadt->pm1a_evt_blk = pmbase + PM1_STS; |
| 783 | fadt->pm1b_evt_blk = 0x0; |
| 784 | fadt->pm1a_cnt_blk = pmbase + PM1_CNT; |
| 785 | fadt->pm1b_cnt_blk = 0x0; |
| 786 | fadt->pm2_cnt_blk = pmbase + PM2_CNT; |
| 787 | fadt->pm_tmr_blk = pmbase + PM1_TMR; |
| 788 | if (pch_is_lp()) |
| 789 | fadt->gpe0_blk = pmbase + LP_GPE0_STS_1; |
| 790 | else |
| 791 | fadt->gpe0_blk = pmbase + GPE0_STS; |
| 792 | fadt->gpe1_blk = 0; |
| 793 | |
| 794 | /* |
| 795 | * Some of the lengths here are doubled. This is because they describe |
| 796 | * blocks containing two registers, where the size of each register |
| 797 | * is found by halving the block length. See Table 5-34 and section |
| 798 | * 4.8.3 of the ACPI specification for details. |
| 799 | */ |
| 800 | fadt->pm1_evt_len = 2 * 2; |
| 801 | fadt->pm1_cnt_len = 2; |
| 802 | fadt->pm2_cnt_len = 1; |
| 803 | fadt->pm_tmr_len = 4; |
| 804 | if (pch_is_lp()) |
| 805 | fadt->gpe0_blk_len = 2 * 16; |
| 806 | else |
| 807 | fadt->gpe0_blk_len = 2 * 8; |
| 808 | fadt->gpe1_blk_len = 0; |
| 809 | fadt->gpe1_base = 0; |
| 810 | |
| 811 | fadt->cst_cnt = 0; |
| 812 | fadt->p_lvl2_lat = 1; |
| 813 | fadt->p_lvl3_lat = 87; |
| 814 | fadt->flush_size = 0; |
| 815 | fadt->flush_stride = 0; |
| 816 | fadt->duty_offset = 0; |
| 817 | fadt->duty_width = 0; |
| 818 | fadt->day_alrm = 0xd; |
| 819 | fadt->mon_alrm = 0x00; |
| 820 | fadt->century = 0x00; |
| 821 | fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; |
| 822 | |
| 823 | fadt->flags = ACPI_FADT_WBINVD | |
| 824 | ACPI_FADT_C1_SUPPORTED | |
| 825 | ACPI_FADT_C2_MP_SUPPORTED | |
| 826 | ACPI_FADT_SLEEP_BUTTON | |
| 827 | ACPI_FADT_RESET_REGISTER | |
| 828 | ACPI_FADT_SEALED_CASE | |
| 829 | ACPI_FADT_S4_RTC_WAKE | |
| 830 | ACPI_FADT_PLATFORM_CLOCK; |
| 831 | |
| 832 | if (cfg->docking_supported) |
| 833 | fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; |
| 834 | |
| 835 | fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; |
| 836 | fadt->reset_reg.bit_width = 8; |
| 837 | fadt->reset_reg.bit_offset = 0; |
| 838 | fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; |
| 839 | fadt->reset_reg.addrl = 0xcf9; |
| 840 | fadt->reset_reg.addrh = 0; |
| 841 | |
| 842 | fadt->reset_value = 6; |
| 843 | |
| 844 | fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 845 | fadt->x_pm1a_evt_blk.bit_width = 2 * 16; |
| 846 | fadt->x_pm1a_evt_blk.bit_offset = 0; |
| 847 | fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; |
| 848 | fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; |
| 849 | fadt->x_pm1a_evt_blk.addrh = 0x0; |
| 850 | |
| 851 | fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 852 | fadt->x_pm1b_evt_blk.bit_width = 0; |
| 853 | fadt->x_pm1b_evt_blk.bit_offset = 0; |
| 854 | fadt->x_pm1b_evt_blk.access_size = 0; |
| 855 | fadt->x_pm1b_evt_blk.addrl = 0x0; |
| 856 | fadt->x_pm1b_evt_blk.addrh = 0x0; |
| 857 | |
| 858 | fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 859 | fadt->x_pm1a_cnt_blk.bit_width = 16; |
| 860 | fadt->x_pm1a_cnt_blk.bit_offset = 0; |
| 861 | fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; |
| 862 | fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; |
| 863 | fadt->x_pm1a_cnt_blk.addrh = 0x0; |
| 864 | |
| 865 | fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 866 | fadt->x_pm1b_cnt_blk.bit_width = 0; |
| 867 | fadt->x_pm1b_cnt_blk.bit_offset = 0; |
| 868 | fadt->x_pm1b_cnt_blk.access_size = 0; |
| 869 | fadt->x_pm1b_cnt_blk.addrl = 0x0; |
| 870 | fadt->x_pm1b_cnt_blk.addrh = 0x0; |
| 871 | |
| 872 | fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 873 | fadt->x_pm2_cnt_blk.bit_width = 8; |
| 874 | fadt->x_pm2_cnt_blk.bit_offset = 0; |
| 875 | fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; |
| 876 | fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT; |
| 877 | fadt->x_pm2_cnt_blk.addrh = 0x0; |
| 878 | |
| 879 | fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 880 | fadt->x_pm_tmr_blk.bit_width = 32; |
| 881 | fadt->x_pm_tmr_blk.bit_offset = 0; |
| 882 | fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; |
| 883 | fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; |
| 884 | fadt->x_pm_tmr_blk.addrh = 0x0; |
| 885 | |
| 886 | /* |
| 887 | * We don't set `fadt->x_gpe0_blk` for Lynx Point LP since the correct |
| 888 | * bit width is 128 * 2, which is too large for an 8 bit unsigned int. |
| 889 | * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`. |
| 890 | */ |
| 891 | if (!pch_is_lp()) { |
| 892 | fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 893 | fadt->x_gpe0_blk.bit_width = 2 * 64; |
| 894 | fadt->x_gpe0_blk.bit_offset = 0; |
| 895 | fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; |
| 896 | fadt->x_gpe0_blk.addrl = pmbase + GPE0_STS; |
| 897 | fadt->x_gpe0_blk.addrh = 0x0; |
| 898 | } else { |
| 899 | fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 900 | fadt->x_gpe0_blk.bit_width = 0; |
| 901 | fadt->x_gpe0_blk.bit_offset = 0; |
| 902 | fadt->x_gpe0_blk.access_size = 0; |
| 903 | fadt->x_gpe0_blk.addrl = 0x0; |
| 904 | fadt->x_gpe0_blk.addrh = 0x0; |
| 905 | } |
| 906 | |
| 907 | fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 908 | fadt->x_gpe1_blk.bit_width = 0; |
| 909 | fadt->x_gpe1_blk.bit_offset = 0; |
| 910 | fadt->x_gpe1_blk.access_size = 0; |
| 911 | fadt->x_gpe1_blk.addrl = 0x0; |
| 912 | fadt->x_gpe1_blk.addrh = 0x0; |
| 913 | } |
| 914 | |
Tristan Corrick | f3127d4 | 2018-10-31 02:25:54 +1300 | [diff] [blame] | 915 | static const char *lpc_acpi_name(const struct device *dev) |
| 916 | { |
| 917 | return "LPCB"; |
| 918 | } |
| 919 | |
| 920 | static void southbridge_fill_ssdt(struct device *dev) |
| 921 | { |
| 922 | intel_acpi_gen_def_acpi_pirq(dev); |
| 923 | } |
| 924 | |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 925 | static unsigned long southbridge_write_acpi_tables(struct device *device, |
Alexander Couzens | 83fc32f | 2015-04-12 22:28:37 +0200 | [diff] [blame] | 926 | unsigned long start, |
| 927 | struct acpi_rsdp *rsdp) |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 928 | { |
| 929 | unsigned long current; |
| 930 | acpi_hpet_t *hpet; |
| 931 | acpi_header_t *ssdt; |
| 932 | |
| 933 | current = start; |
| 934 | |
| 935 | /* Align ACPI tables to 16byte */ |
Aaron Durbin | 07a1b28 | 2015-12-10 17:07:38 -0600 | [diff] [blame] | 936 | current = acpi_align_current(current); |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 937 | |
| 938 | /* |
| 939 | * We explicitly add these tables later on: |
| 940 | */ |
| 941 | printk(BIOS_DEBUG, "ACPI: * HPET\n"); |
| 942 | |
| 943 | hpet = (acpi_hpet_t *) current; |
| 944 | current += sizeof(acpi_hpet_t); |
Aaron Durbin | 07a1b28 | 2015-12-10 17:07:38 -0600 | [diff] [blame] | 945 | current = acpi_align_current(current); |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 946 | acpi_create_intel_hpet(hpet); |
| 947 | acpi_add_table(rsdp, hpet); |
| 948 | |
Aaron Durbin | 07a1b28 | 2015-12-10 17:07:38 -0600 | [diff] [blame] | 949 | current = acpi_align_current(current); |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 950 | |
| 951 | printk(BIOS_DEBUG, "ACPI: * SSDT2\n"); |
| 952 | ssdt = (acpi_header_t *)current; |
| 953 | acpi_create_serialio_ssdt(ssdt); |
| 954 | current += ssdt->length; |
| 955 | acpi_add_table(rsdp, ssdt); |
Aaron Durbin | 07a1b28 | 2015-12-10 17:07:38 -0600 | [diff] [blame] | 956 | current = acpi_align_current(current); |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 957 | |
| 958 | printk(BIOS_DEBUG, "current = %lx\n", current); |
| 959 | return current; |
| 960 | } |
| 961 | |
Tristan Corrick | 32ceed8 | 2018-11-30 22:53:27 +1300 | [diff] [blame] | 962 | static void lpc_final(struct device *dev) |
| 963 | { |
Arthur Heymans | a3121b0 | 2019-05-28 13:46:49 +0200 | [diff] [blame^] | 964 | spi_finalize_ops(); |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame] | 965 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 966 | if (acpi_is_wakeup_s3() || CONFIG(INTEL_CHIPSET_LOCKDOWN)) |
Tristan Corrick | 32ceed8 | 2018-11-30 22:53:27 +1300 | [diff] [blame] | 967 | outb(APM_CNT_FINALIZE, APM_CNT); |
| 968 | } |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 969 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 970 | static struct pci_operations pci_ops = { |
Subrata Banik | 4a0f071 | 2019-03-20 14:29:47 +0530 | [diff] [blame] | 971 | .set_subsystem = pci_dev_set_subsystem, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 972 | }; |
| 973 | |
| 974 | static struct device_operations device_ops = { |
| 975 | .read_resources = pch_lpc_read_resources, |
| 976 | .set_resources = pci_dev_set_resources, |
Duncan Laurie | 8d783b8 | 2013-05-14 11:16:34 -0700 | [diff] [blame] | 977 | .enable_resources = pci_dev_enable_resources, |
Tristan Corrick | f3127d4 | 2018-10-31 02:25:54 +1300 | [diff] [blame] | 978 | .acpi_fill_ssdt_generator = southbridge_fill_ssdt, |
Vladimir Serbinenko | 334fd8e | 2014-10-05 11:10:35 +0200 | [diff] [blame] | 979 | .acpi_inject_dsdt_generator = southbridge_inject_dsdt, |
Tristan Corrick | f3127d4 | 2018-10-31 02:25:54 +1300 | [diff] [blame] | 980 | .acpi_name = lpc_acpi_name, |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 981 | .write_acpi_tables = southbridge_write_acpi_tables, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 982 | .init = lpc_init, |
Tristan Corrick | 32ceed8 | 2018-11-30 22:53:27 +1300 | [diff] [blame] | 983 | .final = lpc_final, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 984 | .enable = pch_lpc_enable, |
Kyösti Mälkki | d0e212c | 2015-02-26 20:47:47 +0200 | [diff] [blame] | 985 | .scan_bus = scan_lpc_bus, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 986 | .ops_pci = &pci_ops, |
| 987 | }; |
| 988 | |
| 989 | |
Aaron Durbin | c1989c4 | 2012-12-11 17:13:17 -0600 | [diff] [blame] | 990 | /* IDs for LPC device of Intel 8 Series Chipset (Lynx Point) */ |
| 991 | static const unsigned short pci_device_ids[] = { |
| 992 | 0x8c41, /* Mobile Full Featured Engineering Sample. */ |
| 993 | 0x8c42, /* Desktop Full Featured Engineering Sample. */ |
| 994 | 0x8c44, /* Z87 SKU */ |
| 995 | 0x8c46, /* Z85 SKU */ |
| 996 | 0x8c49, /* HM86 SKU */ |
| 997 | 0x8c4a, /* H87 SKU */ |
| 998 | 0x8c4b, /* HM87 SKU */ |
| 999 | 0x8c4c, /* Q85 SKU */ |
| 1000 | 0x8c4e, /* Q87 SKU */ |
| 1001 | 0x8c4f, /* QM87 SKU */ |
Tristan Corrick | 9a08574 | 2018-10-31 02:20:28 +1300 | [diff] [blame] | 1002 | 0x8c50, /* B85 SKU */ |
| 1003 | 0x8c52, /* C222 SKU */ |
| 1004 | 0x8c54, /* C224 SKU */ |
| 1005 | 0x8c56, /* C226 SKU */ |
| 1006 | 0x8c5c, /* H81 SKU */ |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 1007 | 0x9c41, /* LP Full Featured Engineering Sample */ |
| 1008 | 0x9c43, /* LP Premium SKU */ |
| 1009 | 0x9c45, /* LP Mainstream SKU */ |
| 1010 | 0x9c47, /* LP Value SKU */ |
Aaron Durbin | c1989c4 | 2012-12-11 17:13:17 -0600 | [diff] [blame] | 1011 | 0 }; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1012 | |
| 1013 | static const struct pci_driver pch_lpc __pci_driver = { |
| 1014 | .ops = &device_ops, |
| 1015 | .vendor = PCI_VENDOR_ID_INTEL, |
| 1016 | .devices = pci_device_ids, |
| 1017 | }; |