Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 5 | * Copyright 2013 Google Inc. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of |
| 10 | * the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #include <console/console.h> |
| 19 | #include <device/device.h> |
| 20 | #include <device/pci.h> |
| 21 | #include <device/pci_ids.h> |
Patrick Rudolph | e56189c | 2018-04-18 10:11:59 +0200 | [diff] [blame] | 22 | #include <device/pci_ops.h> |
Kyösti Mälkki | cbf9571 | 2020-01-05 08:05:45 +0200 | [diff] [blame^] | 23 | #include <option.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 24 | #include <pc80/isa-dma.h> |
| 25 | #include <pc80/i8259.h> |
| 26 | #include <arch/io.h> |
| 27 | #include <arch/ioapic.h> |
| 28 | #include <arch/acpi.h> |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 29 | #include <cpu/x86/smm.h> |
Duncan Laurie | 9c07c8f | 2013-03-22 11:08:39 -0700 | [diff] [blame] | 30 | #include <cbmem.h> |
| 31 | #include <string.h> |
Kyösti Mälkki | 12b121c | 2019-08-18 16:33:39 +0300 | [diff] [blame] | 32 | #include "chip.h" |
Duncan Laurie | 9c07c8f | 2013-03-22 11:08:39 -0700 | [diff] [blame] | 33 | #include "nvs.h" |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 34 | #include "pch.h" |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 35 | #include <arch/acpigen.h> |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 36 | #include <drivers/intel/gma/i915.h> |
Tristan Corrick | f3127d4 | 2018-10-31 02:25:54 +1300 | [diff] [blame] | 37 | #include <southbridge/intel/common/acpi_pirq_gen.h> |
Patrick Rudolph | 6b93112 | 2018-11-01 17:48:37 +0100 | [diff] [blame] | 38 | #include <southbridge/intel/common/rtc.h> |
Arthur Heymans | a3121b0 | 2019-05-28 13:46:49 +0200 | [diff] [blame] | 39 | #include <southbridge/intel/common/spi.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 40 | |
| 41 | #define NMI_OFF 0 |
| 42 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 43 | typedef struct southbridge_intel_lynxpoint_config config_t; |
| 44 | |
Paul Menzel | 373a20c | 2013-05-03 12:17:02 +0200 | [diff] [blame] | 45 | /** |
| 46 | * Set miscellanous static southbridge features. |
| 47 | * |
| 48 | * @param dev PCI device with I/O APIC control registers |
| 49 | */ |
| 50 | static void pch_enable_ioapic(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 51 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 52 | u32 reg32; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 53 | |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 54 | /* Assign unique bus/dev/fn for I/O APIC */ |
| 55 | pci_write_config16(dev, LPC_IBDF, |
| 56 | PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3); |
| 57 | |
Paul Menzel | 373a20c | 2013-05-03 12:17:02 +0200 | [diff] [blame] | 58 | /* Enable ACPI I/O range decode */ |
| 59 | pci_write_config8(dev, ACPI_CNTL, ACPI_EN); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 60 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 61 | set_ioapic_id(VIO_APIC_VADDR, 0x02); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 62 | |
| 63 | /* affirm full set of redirection table entries ("write once") */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 64 | reg32 = io_apic_read(VIO_APIC_VADDR, 0x01); |
Duncan Laurie | c593999 | 2013-05-24 11:06:49 -0700 | [diff] [blame] | 65 | if (pch_is_lp()) { |
| 66 | /* PCH-LP has 39 redirection entries */ |
| 67 | reg32 &= ~0x00ff0000; |
| 68 | reg32 |= 0x00270000; |
| 69 | } |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 70 | io_apic_write(VIO_APIC_VADDR, 0x01, reg32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 71 | |
Paul Menzel | 373a20c | 2013-05-03 12:17:02 +0200 | [diff] [blame] | 72 | /* |
| 73 | * Select Boot Configuration register (0x03) and |
| 74 | * use Processor System Bus (0x01) to deliver interrupts. |
| 75 | */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 76 | io_apic_write(VIO_APIC_VADDR, 0x03, 0x01); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 77 | } |
| 78 | |
| 79 | static void pch_enable_serial_irqs(struct device *dev) |
| 80 | { |
| 81 | /* Set packet length and toggle silent mode bit for one frame. */ |
| 82 | pci_write_config8(dev, SERIRQ_CNTL, |
| 83 | (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 84 | #if !CONFIG(SERIRQ_CONTINUOUS_MODE) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 85 | pci_write_config8(dev, SERIRQ_CNTL, |
| 86 | (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); |
| 87 | #endif |
| 88 | } |
| 89 | |
| 90 | /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control |
| 91 | * 0x00 - 0000 = Reserved |
| 92 | * 0x01 - 0001 = Reserved |
| 93 | * 0x02 - 0010 = Reserved |
| 94 | * 0x03 - 0011 = IRQ3 |
| 95 | * 0x04 - 0100 = IRQ4 |
| 96 | * 0x05 - 0101 = IRQ5 |
| 97 | * 0x06 - 0110 = IRQ6 |
| 98 | * 0x07 - 0111 = IRQ7 |
| 99 | * 0x08 - 1000 = Reserved |
| 100 | * 0x09 - 1001 = IRQ9 |
| 101 | * 0x0A - 1010 = IRQ10 |
| 102 | * 0x0B - 1011 = IRQ11 |
| 103 | * 0x0C - 1100 = IRQ12 |
| 104 | * 0x0D - 1101 = Reserved |
| 105 | * 0x0E - 1110 = IRQ14 |
| 106 | * 0x0F - 1111 = IRQ15 |
| 107 | * PIRQ[n]_ROUT[7] - PIRQ Routing Control |
| 108 | * 0x80 - The PIRQ is not routed. |
| 109 | */ |
| 110 | |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 111 | static void pch_pirq_init(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 112 | { |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 113 | struct device *irq_dev; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 114 | /* Get the chip configuration */ |
| 115 | config_t *config = dev->chip_info; |
| 116 | |
| 117 | pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing); |
| 118 | pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing); |
| 119 | pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing); |
| 120 | pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing); |
| 121 | |
| 122 | pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing); |
| 123 | pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing); |
| 124 | pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing); |
| 125 | pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing); |
| 126 | |
| 127 | /* Eric Biederman once said we should let the OS do this. |
| 128 | * I am not so sure anymore he was right. |
| 129 | */ |
| 130 | |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 131 | for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 132 | u8 int_pin=0, int_line=0; |
| 133 | |
| 134 | if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) |
| 135 | continue; |
| 136 | |
| 137 | int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); |
| 138 | |
| 139 | switch (int_pin) { |
| 140 | case 1: /* INTA# */ int_line = config->pirqa_routing; break; |
| 141 | case 2: /* INTB# */ int_line = config->pirqb_routing; break; |
| 142 | case 3: /* INTC# */ int_line = config->pirqc_routing; break; |
| 143 | case 4: /* INTD# */ int_line = config->pirqd_routing; break; |
| 144 | } |
| 145 | |
| 146 | if (!int_line) |
| 147 | continue; |
| 148 | |
| 149 | pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); |
| 150 | } |
| 151 | } |
| 152 | |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 153 | static void pch_gpi_routing(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 154 | { |
| 155 | /* Get the chip configuration */ |
| 156 | config_t *config = dev->chip_info; |
| 157 | u32 reg32 = 0; |
| 158 | |
| 159 | /* An array would be much nicer here, or some |
| 160 | * other method of doing this. |
| 161 | */ |
| 162 | reg32 |= (config->gpi0_routing & 0x03) << 0; |
| 163 | reg32 |= (config->gpi1_routing & 0x03) << 2; |
| 164 | reg32 |= (config->gpi2_routing & 0x03) << 4; |
| 165 | reg32 |= (config->gpi3_routing & 0x03) << 6; |
| 166 | reg32 |= (config->gpi4_routing & 0x03) << 8; |
| 167 | reg32 |= (config->gpi5_routing & 0x03) << 10; |
| 168 | reg32 |= (config->gpi6_routing & 0x03) << 12; |
| 169 | reg32 |= (config->gpi7_routing & 0x03) << 14; |
| 170 | reg32 |= (config->gpi8_routing & 0x03) << 16; |
| 171 | reg32 |= (config->gpi9_routing & 0x03) << 18; |
| 172 | reg32 |= (config->gpi10_routing & 0x03) << 20; |
| 173 | reg32 |= (config->gpi11_routing & 0x03) << 22; |
| 174 | reg32 |= (config->gpi12_routing & 0x03) << 24; |
| 175 | reg32 |= (config->gpi13_routing & 0x03) << 26; |
| 176 | reg32 |= (config->gpi14_routing & 0x03) << 28; |
| 177 | reg32 |= (config->gpi15_routing & 0x03) << 30; |
| 178 | |
Kyösti Mälkki | b85a87b | 2014-12-29 11:32:27 +0200 | [diff] [blame] | 179 | pci_write_config32(dev, GPIO_ROUT, reg32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 180 | } |
| 181 | |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 182 | static void pch_power_options(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 183 | { |
| 184 | u8 reg8; |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 185 | u16 reg16; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 186 | u32 reg32; |
| 187 | const char *state; |
| 188 | /* Get the chip configuration */ |
| 189 | config_t *config = dev->chip_info; |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 190 | u16 pmbase = get_pmbase(); |
Nico Huber | 9faae2b | 2018-11-14 00:00:35 +0100 | [diff] [blame] | 191 | int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 192 | int nmi_option; |
| 193 | |
| 194 | /* Which state do we want to goto after g3 (power restored)? |
| 195 | * 0 == S0 Full On |
| 196 | * 1 == S5 Soft Off |
| 197 | * |
| 198 | * If the option is not existent (Laptops), use Kconfig setting. |
| 199 | */ |
| 200 | get_option(&pwr_on, "power_on_after_fail"); |
| 201 | |
| 202 | reg16 = pci_read_config16(dev, GEN_PMCON_3); |
| 203 | reg16 &= 0xfffe; |
| 204 | switch (pwr_on) { |
| 205 | case MAINBOARD_POWER_OFF: |
| 206 | reg16 |= 1; |
| 207 | state = "off"; |
| 208 | break; |
| 209 | case MAINBOARD_POWER_ON: |
| 210 | reg16 &= ~1; |
| 211 | state = "on"; |
| 212 | break; |
| 213 | case MAINBOARD_POWER_KEEP: |
| 214 | reg16 &= ~1; |
| 215 | state = "state keep"; |
| 216 | break; |
| 217 | default: |
| 218 | state = "undefined"; |
| 219 | } |
| 220 | |
| 221 | reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */ |
| 222 | reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */ |
| 223 | |
| 224 | reg16 &= ~(1 << 10); |
| 225 | reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */ |
| 226 | |
| 227 | reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */ |
| 228 | |
| 229 | pci_write_config16(dev, GEN_PMCON_3, reg16); |
| 230 | printk(BIOS_INFO, "Set power %s after power failure.\n", state); |
| 231 | |
| 232 | /* Set up NMI on errors. */ |
| 233 | reg8 = inb(0x61); |
| 234 | reg8 &= 0x0f; /* Higher Nibble must be 0 */ |
| 235 | reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */ |
| 236 | // reg8 &= ~(1 << 2); /* PCI SERR# Enable */ |
| 237 | reg8 |= (1 << 2); /* PCI SERR# Disable for now */ |
| 238 | outb(reg8, 0x61); |
| 239 | |
| 240 | reg8 = inb(0x70); |
| 241 | nmi_option = NMI_OFF; |
| 242 | get_option(&nmi_option, "nmi"); |
| 243 | if (nmi_option) { |
| 244 | printk(BIOS_INFO, "NMI sources enabled.\n"); |
| 245 | reg8 &= ~(1 << 7); /* Set NMI. */ |
| 246 | } else { |
| 247 | printk(BIOS_INFO, "NMI sources disabled.\n"); |
Elyes HAOUAS | 9c5d463 | 2018-04-26 22:21:21 +0200 | [diff] [blame] | 248 | reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 249 | } |
| 250 | outb(reg8, 0x70); |
| 251 | |
| 252 | /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */ |
| 253 | reg16 = pci_read_config16(dev, GEN_PMCON_1); |
| 254 | reg16 &= ~(3 << 0); // SMI# rate 1 minute |
| 255 | reg16 &= ~(1 << 10); // Disable BIOS_PCI_EXP_EN for native PME |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 256 | pci_write_config16(dev, GEN_PMCON_1, reg16); |
| 257 | |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 258 | /* |
| 259 | * Set the board's GPI routing on LynxPoint-H. |
| 260 | * This is done as part of GPIO configuration on LynxPoint-LP. |
| 261 | */ |
| 262 | if (pch_is_lp()) |
| 263 | pch_gpi_routing(dev); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 264 | |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 265 | /* GPE setup based on device tree configuration */ |
| 266 | enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2, |
| 267 | config->gpe0_en_3, config->gpe0_en_4); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 268 | |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 269 | /* SMI setup based on device tree configuration */ |
| 270 | enable_alt_smi(config->alt_gp_smi_en); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 271 | |
| 272 | /* Set up power management block and determine sleep mode */ |
| 273 | reg32 = inl(pmbase + 0x04); // PM1_CNT |
| 274 | reg32 &= ~(7 << 10); // SLP_TYP |
| 275 | reg32 |= (1 << 0); // SCI_EN |
| 276 | outl(reg32, pmbase + 0x04); |
| 277 | |
| 278 | /* Clear magic status bits to prevent unexpected wake */ |
| 279 | reg32 = RCBA32(0x3310); |
| 280 | reg32 |= (1 << 4)|(1 << 5)|(1 << 0); |
| 281 | RCBA32(0x3310) = reg32; |
| 282 | |
Ryan Salsamendi | 889ce9c | 2017-06-30 17:45:14 -0700 | [diff] [blame] | 283 | reg16 = RCBA16(0x3f02); |
| 284 | reg16 &= ~0xf; |
| 285 | RCBA16(0x3f02) = reg16; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 286 | } |
| 287 | |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 288 | /* LynxPoint PCH Power Management init */ |
| 289 | static void lpt_pm_init(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 290 | { |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 291 | printk(BIOS_DEBUG, "LynxPoint PM init\n"); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 292 | } |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 293 | |
| 294 | const struct rcba_config_instruction lpt_lp_pm_rcba[] = { |
Duncan Laurie | 4bc107b | 2013-06-24 13:14:44 -0700 | [diff] [blame] | 295 | RCBA_RMW_REG_32(0x232c, ~1, 0x00000000), |
| 296 | RCBA_RMW_REG_32(0x1100, ~0xc000, 0xc000), |
| 297 | RCBA_RMW_REG_32(0x1100, ~0, 0x00000100), |
| 298 | RCBA_RMW_REG_32(0x1100, ~0, 0x0000003f), |
| 299 | RCBA_RMW_REG_32(0x2320, ~0x60, 0x10), |
| 300 | RCBA_RMW_REG_32(0x3314, 0, 0x00012fff), |
| 301 | RCBA_RMW_REG_32(0x3318, 0, 0x0dcf0400), |
| 302 | RCBA_RMW_REG_32(0x3324, 0, 0x04000000), |
| 303 | RCBA_RMW_REG_32(0x3368, 0, 0x00041400), |
| 304 | RCBA_RMW_REG_32(0x3388, 0, 0x3f8ddbff), |
| 305 | RCBA_RMW_REG_32(0x33ac, 0, 0x00007001), |
| 306 | RCBA_RMW_REG_32(0x33b0, 0, 0x00181900), |
| 307 | RCBA_RMW_REG_32(0x33c0, 0, 0x00060A00), |
| 308 | RCBA_RMW_REG_32(0x33d0, 0, 0x06200840), |
| 309 | RCBA_RMW_REG_32(0x3a28, 0, 0x01010101), |
| 310 | RCBA_RMW_REG_32(0x3a2c, 0, 0x04040404), |
| 311 | RCBA_RMW_REG_32(0x2b1c, 0, 0x03808033), |
| 312 | RCBA_RMW_REG_32(0x2b34, 0, 0x80000009), |
| 313 | RCBA_RMW_REG_32(0x3348, 0, 0x022ddfff), |
| 314 | RCBA_RMW_REG_32(0x334c, 0, 0x00000001), |
| 315 | RCBA_RMW_REG_32(0x3358, 0, 0x0001c000), |
| 316 | RCBA_RMW_REG_32(0x3380, 0, 0x3f8ddbff), |
| 317 | RCBA_RMW_REG_32(0x3384, 0, 0x0001c7e1), |
| 318 | RCBA_RMW_REG_32(0x338c, 0, 0x0001c7e1), |
| 319 | RCBA_RMW_REG_32(0x3398, 0, 0x0001c000), |
| 320 | RCBA_RMW_REG_32(0x33a8, 0, 0x00181900), |
| 321 | RCBA_RMW_REG_32(0x33dc, 0, 0x00080000), |
| 322 | RCBA_RMW_REG_32(0x33e0, 0, 0x00000001), |
| 323 | RCBA_RMW_REG_32(0x3a20, 0, 0x00000404), |
| 324 | RCBA_RMW_REG_32(0x3a24, 0, 0x01010101), |
| 325 | RCBA_RMW_REG_32(0x3a30, 0, 0x01010101), |
| 326 | RCBA_RMW_REG_32(0x0410, ~0, 0x00000003), |
| 327 | RCBA_RMW_REG_32(0x2618, ~0, 0x08000000), |
| 328 | RCBA_RMW_REG_32(0x2300, ~0, 0x00000002), |
| 329 | RCBA_RMW_REG_32(0x2600, ~0, 0x00000008), |
| 330 | RCBA_RMW_REG_32(0x33b4, 0, 0x00007001), |
| 331 | RCBA_RMW_REG_32(0x3350, 0, 0x022ddfff), |
| 332 | RCBA_RMW_REG_32(0x3354, 0, 0x00000001), |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 333 | RCBA_RMW_REG_32(0x33d4, ~0, 0x08000000), /* Power Optimizer */ |
Matt DeVillier | c97e042 | 2017-02-16 11:36:16 -0600 | [diff] [blame] | 334 | RCBA_RMW_REG_32(0x33c8, ~0, 0x00000080), /* Power Optimizer */ |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 335 | RCBA_RMW_REG_32(0x2b10, 0, 0x0000883c), /* Power Optimizer */ |
Duncan Laurie | 5cf34ce | 2013-04-26 10:41:33 -0700 | [diff] [blame] | 336 | RCBA_RMW_REG_32(0x2b14, 0, 0x1e0a4616), /* Power Optimizer */ |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 337 | RCBA_RMW_REG_32(0x2b24, 0, 0x40000005), /* Power Optimizer */ |
| 338 | RCBA_RMW_REG_32(0x2b20, 0, 0x0005db01), /* Power Optimizer */ |
Duncan Laurie | 4bc107b | 2013-06-24 13:14:44 -0700 | [diff] [blame] | 339 | RCBA_RMW_REG_32(0x3a80, 0, 0x05145005), |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 340 | RCBA_END_CONFIG |
| 341 | }; |
| 342 | |
| 343 | /* LynxPoint LP PCH Power Management init */ |
| 344 | static void lpt_lp_pm_init(struct device *dev) |
| 345 | { |
| 346 | struct southbridge_intel_lynxpoint_config *config = dev->chip_info; |
| 347 | u32 data; |
| 348 | |
| 349 | printk(BIOS_DEBUG, "LynxPoint LP PM init\n"); |
| 350 | |
| 351 | pci_write_config8(dev, 0xa9, 0x46); |
| 352 | |
| 353 | pch_config_rcba(lpt_lp_pm_rcba); |
| 354 | |
| 355 | pci_write_config32(dev, 0xac, |
| 356 | pci_read_config32(dev, 0xac) | (1 << 21)); |
| 357 | |
Elyes HAOUAS | a0aea56 | 2017-07-03 21:38:53 +0200 | [diff] [blame] | 358 | pch_iobp_update(0xED00015C, ~(1 << 11), 0x00003700); |
Duncan Laurie | 4bc107b | 2013-06-24 13:14:44 -0700 | [diff] [blame] | 359 | pch_iobp_update(0xED000118, ~0UL, 0x00c00000); |
| 360 | pch_iobp_update(0xED000120, ~0UL, 0x00240000); |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 361 | pch_iobp_update(0xCA000000, ~0UL, 0x00000009); |
| 362 | |
| 363 | /* Set RCBA CIR28 0x3A84 based on SATA port enables */ |
| 364 | data = 0x00001005; |
| 365 | /* Port 3 and 2 disabled */ |
| 366 | if ((config->sata_port_map & ((1 << 3)|(1 << 2))) == 0) |
| 367 | data |= (1 << 24) | (1 << 26); |
| 368 | /* Port 1 and 0 disabled */ |
| 369 | if ((config->sata_port_map & ((1 << 1)|(1 << 0))) == 0) |
| 370 | data |= (1 << 20) | (1 << 18); |
| 371 | RCBA32(0x3a84) = data; |
| 372 | |
Duncan Laurie | 5cf34ce | 2013-04-26 10:41:33 -0700 | [diff] [blame] | 373 | /* Set RCBA 0x2b1c[29]=1 if DSP disabled */ |
| 374 | if (RCBA32(FD) & PCH_DISABLE_ADSPD) |
| 375 | RCBA32_OR(0x2b1c, (1 << 29)); |
| 376 | |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 377 | /* Lock */ |
| 378 | RCBA32_OR(0x3a6c, 0x00000001); |
| 379 | |
| 380 | /* Set RCBA 0x33D4 after other setup */ |
| 381 | RCBA32_OR(0x33d4, 0x2fff2fb1); |
| 382 | |
| 383 | /* Set RCBA 0x33C8[15]=1 as last step */ |
| 384 | RCBA32_OR(0x33c8, (1 << 15)); |
| 385 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 386 | |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 387 | static void enable_hpet(struct device *const dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 388 | { |
| 389 | u32 reg32; |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 390 | size_t i; |
| 391 | |
| 392 | /* Assign unique bus/dev/fn for each HPET */ |
| 393 | for (i = 0; i < 8; ++i) |
| 394 | pci_write_config16(dev, LPC_HnBDF(i), |
| 395 | PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | i); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 396 | |
| 397 | /* Move HPET to default address 0xfed00000 and enable it */ |
| 398 | reg32 = RCBA32(HPTC); |
| 399 | reg32 |= (1 << 7); // HPET Address Enable |
| 400 | reg32 &= ~(3 << 0); |
| 401 | RCBA32(HPTC) = reg32; |
| 402 | /* Read it back to stick. It's affected by posted write syndrome. */ |
Elyes HAOUAS | 6de151e | 2019-10-18 16:43:30 +0200 | [diff] [blame] | 403 | RCBA32(HPTC); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 404 | } |
| 405 | |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 406 | static void enable_clock_gating(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 407 | { |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 408 | /* LynxPoint Mobile */ |
| 409 | u32 reg32; |
| 410 | u16 reg16; |
| 411 | |
| 412 | /* DMI */ |
| 413 | RCBA32_AND_OR(0x2234, ~0UL, 0xf); |
| 414 | reg16 = pci_read_config16(dev, GEN_PMCON_1); |
| 415 | reg16 |= (1 << 11) | (1 << 12) | (1 << 14); |
| 416 | reg16 |= (1 << 2); // PCI CLKRUN# Enable |
| 417 | pci_write_config16(dev, GEN_PMCON_1, reg16); |
| 418 | RCBA32_OR(0x900, (1 << 14)); |
| 419 | |
| 420 | reg32 = RCBA32(CG); |
| 421 | reg32 |= (1 << 22); // HDA Dynamic |
Ryan Salsamendi | 0d9b360 | 2017-06-30 17:15:57 -0700 | [diff] [blame] | 422 | reg32 |= (1UL << 31); // LPC Dynamic |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 423 | reg32 |= (1 << 16); // PCIe Dynamic |
| 424 | reg32 |= (1 << 27); // HPET Dynamic |
| 425 | reg32 |= (1 << 28); // GPIO Dynamic |
| 426 | RCBA32(CG) = reg32; |
| 427 | |
| 428 | RCBA32_OR(0x38c0, 0x7); // SPI Dynamic |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 429 | } |
| 430 | |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 431 | static void enable_lp_clock_gating(struct device *dev) |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 432 | { |
| 433 | /* LynxPoint LP */ |
| 434 | u32 reg32; |
| 435 | u16 reg16; |
| 436 | |
| 437 | /* DMI */ |
| 438 | RCBA32_AND_OR(0x2234, ~0UL, 0xf); |
| 439 | reg16 = pci_read_config16(dev, GEN_PMCON_1); |
| 440 | reg16 &= ~((1 << 11) | (1 << 14)); |
| 441 | reg16 |= (1 << 5) | (1 << 6) | (1 << 7) | (1 << 12) | (1 << 13); |
| 442 | reg16 |= (1 << 2); // PCI CLKRUN# Enable |
| 443 | pci_write_config16(dev, GEN_PMCON_1, reg16); |
| 444 | |
| 445 | reg32 = pci_read_config32(dev, 0x64); |
| 446 | reg32 |= (1 << 6); |
| 447 | pci_write_config32(dev, 0x64, reg32); |
| 448 | |
Duncan Laurie | 4bc107b | 2013-06-24 13:14:44 -0700 | [diff] [blame] | 449 | /* |
| 450 | * RCBA + 0x2614[27:25,14:13,10,8] = 101,11,1,1 |
| 451 | * RCBA + 0x2614[23:16] = 0x20 |
| 452 | * RCBA + 0x2614[30:28] = 0x0 |
Duncan Laurie | d8c7d73 | 2013-07-16 09:01:43 -0700 | [diff] [blame] | 453 | * RCBA + 0x2614[26] = 1 (IF 0:2.0@0x08 >= 0x0b) |
Duncan Laurie | 4bc107b | 2013-06-24 13:14:44 -0700 | [diff] [blame] | 454 | */ |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 455 | RCBA32_AND_OR(0x2614, 0x8bffffff, 0x0a206500); |
Duncan Laurie | 4bc107b | 2013-06-24 13:14:44 -0700 | [diff] [blame] | 456 | |
| 457 | /* Check for LPT-LP B2 stepping and 0:31.0@0xFA > 4 */ |
Nico Huber | 744d6bd | 2019-01-12 14:58:20 +0100 | [diff] [blame] | 458 | struct device *const gma = pcidev_on_root(2, 0); |
| 459 | if (gma && pci_read_config8(gma, 0x8) >= 0x0b) |
Elyes HAOUAS | a0aea56 | 2017-07-03 21:38:53 +0200 | [diff] [blame] | 460 | RCBA32_OR(0x2614, (1 << 26)); |
Duncan Laurie | 4bc107b | 2013-06-24 13:14:44 -0700 | [diff] [blame] | 461 | |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 462 | RCBA32_OR(0x900, 0x0000031f); |
| 463 | |
| 464 | reg32 = RCBA32(CG); |
Duncan Laurie | a2d6a40 | 2013-03-22 11:24:45 -0700 | [diff] [blame] | 465 | if (RCBA32(0x3454) & (1 << 4)) |
| 466 | reg32 &= ~(1 << 29); // LPC Dynamic |
| 467 | else |
| 468 | reg32 |= (1 << 29); // LPC Dynamic |
Ryan Salsamendi | 3f2fe18 | 2017-07-04 13:14:16 -0700 | [diff] [blame] | 469 | reg32 |= (1UL << 31); // LP LPC |
Duncan Laurie | 5cf34ce | 2013-04-26 10:41:33 -0700 | [diff] [blame] | 470 | reg32 |= (1 << 30); // LP BLA |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 471 | reg32 |= (1 << 28); // GPIO Dynamic |
| 472 | reg32 |= (1 << 27); // HPET Dynamic |
Duncan Laurie | 5cf34ce | 2013-04-26 10:41:33 -0700 | [diff] [blame] | 473 | reg32 |= (1 << 26); // Generic Platform Event Clock |
| 474 | if (RCBA32(BUC) & PCH_DISABLE_GBE) |
| 475 | reg32 |= (1 << 23); // GbE Static |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 476 | reg32 |= (1 << 22); // HDA Dynamic |
Duncan Laurie | 5cf34ce | 2013-04-26 10:41:33 -0700 | [diff] [blame] | 477 | reg32 |= (1 << 16); // PCI Dynamic |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 478 | RCBA32(CG) = reg32; |
| 479 | |
| 480 | RCBA32_OR(0x3434, 0x7); // LP LPC |
| 481 | |
| 482 | RCBA32_AND_OR(0x333c, 0xffcfffff, 0x00c00000); // SATA |
| 483 | |
| 484 | RCBA32_OR(0x38c0, 0x3c07); // SPI Dynamic |
| 485 | |
| 486 | pch_iobp_update(0xCF000000, ~0UL, 0x00007001); |
Duncan Laurie | 5cf34ce | 2013-04-26 10:41:33 -0700 | [diff] [blame] | 487 | pch_iobp_update(0xCE00C000, ~1UL, 0x00000000); // bit0=0 in BWG 1.4.0 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 488 | } |
| 489 | |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 490 | static void pch_set_acpi_mode(void) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 491 | { |
Kyösti Mälkki | b490562 | 2019-07-12 08:02:35 +0300 | [diff] [blame] | 492 | if (CONFIG(HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 493 | printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 494 | outb(APM_CNT_ACPI_DISABLE, APM_CNT); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 495 | printk(BIOS_DEBUG, "done.\n"); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 496 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 497 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 498 | |
| 499 | static void pch_disable_smm_only_flashing(struct device *dev) |
| 500 | { |
| 501 | u8 reg8; |
| 502 | |
| 503 | printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); |
Elyes HAOUAS | 0c22d2f | 2018-12-01 12:19:52 +0100 | [diff] [blame] | 504 | reg8 = pci_read_config8(dev, BIOS_CNTL); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 505 | reg8 &= ~(1 << 5); |
Elyes HAOUAS | 0c22d2f | 2018-12-01 12:19:52 +0100 | [diff] [blame] | 506 | pci_write_config8(dev, BIOS_CNTL, reg8); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 507 | } |
| 508 | |
| 509 | static void pch_fixups(struct device *dev) |
| 510 | { |
| 511 | u8 gen_pmcon_2; |
| 512 | |
| 513 | /* Indicate DRAM init done for MRC S3 to know it can resume */ |
| 514 | gen_pmcon_2 = pci_read_config8(dev, GEN_PMCON_2); |
| 515 | gen_pmcon_2 |= (1 << 7); |
| 516 | pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2); |
| 517 | |
| 518 | /* |
| 519 | * Enable DMI ASPM in the PCH |
| 520 | */ |
| 521 | RCBA32_AND_OR(0x2304, ~(1 << 10), 0); |
| 522 | RCBA32_OR(0x21a4, (1 << 11)|(1 << 10)); |
| 523 | RCBA32_OR(0x21a8, 0x3); |
| 524 | } |
| 525 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 526 | static void lpc_init(struct device *dev) |
| 527 | { |
| 528 | printk(BIOS_DEBUG, "pch: lpc_init\n"); |
| 529 | |
| 530 | /* Set the value for PCI command register. */ |
| 531 | pci_write_config16(dev, PCI_COMMAND, 0x000f); |
| 532 | |
| 533 | /* IO APIC initialization. */ |
Paul Menzel | 373a20c | 2013-05-03 12:17:02 +0200 | [diff] [blame] | 534 | pch_enable_ioapic(dev); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 535 | |
| 536 | pch_enable_serial_irqs(dev); |
| 537 | |
| 538 | /* Setup the PIRQ. */ |
| 539 | pch_pirq_init(dev); |
| 540 | |
| 541 | /* Setup power options. */ |
| 542 | pch_power_options(dev); |
| 543 | |
| 544 | /* Initialize power management */ |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 545 | if (pch_is_lp()) { |
| 546 | lpt_lp_pm_init(dev); |
| 547 | enable_lp_clock_gating(dev); |
| 548 | } else { |
| 549 | lpt_pm_init(dev); |
| 550 | enable_clock_gating(dev); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 551 | } |
| 552 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 553 | /* Initialize the real time clock. */ |
Patrick Rudolph | 6b93112 | 2018-11-01 17:48:37 +0100 | [diff] [blame] | 554 | sb_rtc_init(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 555 | |
| 556 | /* Initialize ISA DMA. */ |
| 557 | isa_dma_init(); |
| 558 | |
| 559 | /* Initialize the High Precision Event Timers, if present. */ |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 560 | enable_hpet(dev); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 561 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 562 | setup_i8259(); |
| 563 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 564 | /* Interrupt 9 should be level triggered (SCI) */ |
| 565 | i8259_configure_irq_trigger(9, 1); |
| 566 | |
| 567 | pch_disable_smm_only_flashing(dev); |
| 568 | |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 569 | pch_set_acpi_mode(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 570 | |
| 571 | pch_fixups(dev); |
| 572 | } |
| 573 | |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 574 | static void pch_lpc_add_mmio_resources(struct device *dev) |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 575 | { |
| 576 | u32 reg; |
| 577 | struct resource *res; |
| 578 | const u32 default_decode_base = IO_APIC_ADDR; |
| 579 | |
| 580 | /* |
| 581 | * Just report all resources from IO-APIC base to 4GiB. Don't mark |
| 582 | * them reserved as that may upset the OS if this range is marked |
| 583 | * as reserved in the e820. |
| 584 | */ |
| 585 | res = new_resource(dev, OIC); |
| 586 | res->base = default_decode_base; |
| 587 | res->size = 0 - default_decode_base; |
| 588 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 589 | |
| 590 | /* RCBA */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 591 | if ((uintptr_t)DEFAULT_RCBA < default_decode_base) { |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 592 | res = new_resource(dev, RCBA); |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 593 | res->base = (resource_t)(uintptr_t)DEFAULT_RCBA; |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 594 | res->size = 16 * 1024; |
| 595 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | |
| 596 | IORESOURCE_FIXED | IORESOURCE_RESERVE; |
| 597 | } |
| 598 | |
| 599 | /* Check LPC Memory Decode register. */ |
| 600 | reg = pci_read_config32(dev, LGMR); |
| 601 | if (reg & 1) { |
| 602 | reg &= ~0xffff; |
| 603 | if (reg < default_decode_base) { |
| 604 | res = new_resource(dev, LGMR); |
| 605 | res->base = reg; |
| 606 | res->size = 16 * 1024; |
| 607 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | |
| 608 | IORESOURCE_FIXED | IORESOURCE_RESERVE; |
| 609 | } |
| 610 | } |
| 611 | } |
| 612 | |
| 613 | /* Default IO range claimed by the LPC device. The upper bound is exclusive. */ |
| 614 | #define LPC_DEFAULT_IO_RANGE_LOWER 0 |
| 615 | #define LPC_DEFAULT_IO_RANGE_UPPER 0x1000 |
| 616 | |
Julius Werner | 7c712bb | 2019-05-01 16:51:20 -0700 | [diff] [blame] | 617 | static inline int pch_io_range_in_default(int base, int size) |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 618 | { |
| 619 | /* Does it start above the range? */ |
| 620 | if (base >= LPC_DEFAULT_IO_RANGE_UPPER) |
| 621 | return 0; |
| 622 | |
| 623 | /* Is it entirely contained? */ |
| 624 | if (base >= LPC_DEFAULT_IO_RANGE_LOWER && |
| 625 | (base + size) < LPC_DEFAULT_IO_RANGE_UPPER) |
| 626 | return 1; |
| 627 | |
| 628 | /* This will return not in range for partial overlaps. */ |
| 629 | return 0; |
| 630 | } |
| 631 | |
| 632 | /* |
| 633 | * Note: this function assumes there is no overlap with the default LPC device's |
| 634 | * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. |
| 635 | */ |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 636 | static void pch_lpc_add_io_resource(struct device *dev, u16 base, u16 size, |
| 637 | int index) |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 638 | { |
| 639 | struct resource *res; |
| 640 | |
| 641 | if (pch_io_range_in_default(base, size)) |
| 642 | return; |
| 643 | |
| 644 | res = new_resource(dev, index); |
| 645 | res->base = base; |
| 646 | res->size = size; |
| 647 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 648 | } |
| 649 | |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 650 | static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value, |
| 651 | int index) |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 652 | { |
| 653 | /* |
| 654 | * Check if the register is enabled. If so and the base exceeds the |
Kyösti Mälkki | b544c00 | 2019-01-06 10:41:41 +0200 | [diff] [blame] | 655 | * device's default, claim range and add the resource. |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 656 | */ |
| 657 | if (reg_value & 1) { |
| 658 | u16 base = reg_value & 0xfffc; |
| 659 | u16 size = (0x3 | ((reg_value >> 16) & 0xfc)) + 1; |
| 660 | pch_lpc_add_io_resource(dev, base, size, index); |
| 661 | } |
| 662 | } |
| 663 | |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 664 | static void pch_lpc_add_io_resources(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 665 | { |
| 666 | struct resource *res; |
| 667 | config_t *config = dev->chip_info; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 668 | |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 669 | /* Add the default claimed IO range for the LPC device. */ |
| 670 | res = new_resource(dev, 0); |
| 671 | res->base = LPC_DEFAULT_IO_RANGE_LOWER; |
| 672 | res->size = LPC_DEFAULT_IO_RANGE_UPPER - LPC_DEFAULT_IO_RANGE_LOWER; |
| 673 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 674 | |
| 675 | /* GPIOBASE */ |
Duncan Laurie | 7922b46 | 2013-03-08 16:34:33 -0800 | [diff] [blame] | 676 | pch_lpc_add_io_resource(dev, get_gpiobase(), DEFAULT_GPIOSIZE, |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 677 | GPIO_BASE); |
| 678 | |
| 679 | /* PMBASE */ |
Duncan Laurie | 7922b46 | 2013-03-08 16:34:33 -0800 | [diff] [blame] | 680 | pch_lpc_add_io_resource(dev, get_pmbase(), 256, PMBASE); |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 681 | |
| 682 | /* LPC Generic IO Decode range. */ |
| 683 | pch_lpc_add_gen_io_resources(dev, config->gen1_dec, LPC_GEN1_DEC); |
| 684 | pch_lpc_add_gen_io_resources(dev, config->gen2_dec, LPC_GEN2_DEC); |
| 685 | pch_lpc_add_gen_io_resources(dev, config->gen3_dec, LPC_GEN3_DEC); |
| 686 | pch_lpc_add_gen_io_resources(dev, config->gen4_dec, LPC_GEN4_DEC); |
| 687 | } |
| 688 | |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 689 | static void pch_lpc_read_resources(struct device *dev) |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 690 | { |
Duncan Laurie | 9c07c8f | 2013-03-22 11:08:39 -0700 | [diff] [blame] | 691 | global_nvs_t *gnvs; |
| 692 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 693 | /* Get the normal PCI resources of this device. */ |
| 694 | pci_dev_read_resources(dev); |
| 695 | |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 696 | /* Add non-standard MMIO resources. */ |
| 697 | pch_lpc_add_mmio_resources(dev); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 698 | |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 699 | /* Add IO resources. */ |
| 700 | pch_lpc_add_io_resources(dev); |
Duncan Laurie | 9c07c8f | 2013-03-22 11:08:39 -0700 | [diff] [blame] | 701 | |
| 702 | /* Allocate ACPI NVS in CBMEM */ |
| 703 | gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); |
Kyösti Mälkki | c3ed886 | 2014-06-19 19:50:51 +0300 | [diff] [blame] | 704 | if (!acpi_is_wakeup_s3() && gnvs) |
Duncan Laurie | 9c07c8f | 2013-03-22 11:08:39 -0700 | [diff] [blame] | 705 | memset(gnvs, 0, sizeof(global_nvs_t)); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 706 | } |
| 707 | |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 708 | static void pch_lpc_enable(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 709 | { |
| 710 | /* Enable PCH Display Port */ |
| 711 | RCBA16(DISPBDF) = 0x0010; |
| 712 | RCBA32_OR(FD2, PCH_ENABLE_DBDF); |
| 713 | |
| 714 | pch_enable(dev); |
| 715 | } |
| 716 | |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 717 | static void southbridge_inject_dsdt(struct device *dev) |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 718 | { |
Vladimir Serbinenko | 7309c64 | 2014-10-05 11:07:33 +0200 | [diff] [blame] | 719 | global_nvs_t *gnvs; |
| 720 | |
| 721 | gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 722 | if (!gnvs) { |
Elyes HAOUAS | 035df00 | 2016-10-03 21:54:16 +0200 | [diff] [blame] | 723 | gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); |
Vladimir Serbinenko | 7309c64 | 2014-10-05 11:07:33 +0200 | [diff] [blame] | 724 | if (gnvs) |
| 725 | memset(gnvs, 0, sizeof(*gnvs)); |
| 726 | } |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 727 | |
| 728 | if (gnvs) { |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 729 | const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); |
| 730 | |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 731 | acpi_create_gnvs(gnvs); |
Vladimir Serbinenko | 1b409fd | 2014-10-12 00:26:21 +0200 | [diff] [blame] | 732 | |
| 733 | gnvs->apic = 1; |
| 734 | gnvs->mpen = 1; /* Enable Multi Processing */ |
| 735 | gnvs->pcnt = dev_count_cpu(); |
| 736 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 737 | #if CONFIG(CHROMEOS) |
Joel Kitching | 6fbd874 | 2018-08-23 14:56:25 +0800 | [diff] [blame] | 738 | chromeos_init_chromeos_acpi(&(gnvs->chromeos)); |
Vladimir Serbinenko | 1b409fd | 2014-10-12 00:26:21 +0200 | [diff] [blame] | 739 | #endif |
| 740 | |
| 741 | /* Update the mem console pointer. */ |
| 742 | gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); |
| 743 | |
Nico Huber | 744d6bd | 2019-01-12 14:58:20 +0100 | [diff] [blame] | 744 | if (gfx) { |
| 745 | gnvs->ndid = gfx->ndid; |
| 746 | memcpy(gnvs->did, gfx->did, sizeof(gnvs->did)); |
| 747 | } |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 748 | |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 749 | /* And tell SMI about it */ |
| 750 | smm_setup_structures(gnvs, NULL, NULL); |
| 751 | |
Vladimir Serbinenko | 334fd8e | 2014-10-05 11:10:35 +0200 | [diff] [blame] | 752 | /* Add it to DSDT. */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 753 | acpigen_write_scope("\\"); |
| 754 | acpigen_write_name_dword("NVSA", (u32) gnvs); |
| 755 | acpigen_pop_len(); |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 756 | } |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 757 | } |
| 758 | |
Tristan Corrick | b2632ce | 2018-10-31 02:28:13 +1300 | [diff] [blame] | 759 | void acpi_fill_fadt(acpi_fadt_t *fadt) |
| 760 | { |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 761 | struct device *dev = pcidev_on_root(0x1f, 0); |
Tristan Corrick | b2632ce | 2018-10-31 02:28:13 +1300 | [diff] [blame] | 762 | struct southbridge_intel_lynxpoint_config *cfg = dev->chip_info; |
| 763 | u16 pmbase = get_pmbase(); |
| 764 | |
| 765 | fadt->sci_int = 0x9; |
| 766 | fadt->smi_cmd = APM_CNT; |
| 767 | fadt->acpi_enable = APM_CNT_ACPI_ENABLE; |
| 768 | fadt->acpi_disable = APM_CNT_ACPI_DISABLE; |
| 769 | fadt->s4bios_req = 0x0; |
| 770 | fadt->pstate_cnt = 0; |
| 771 | |
| 772 | fadt->pm1a_evt_blk = pmbase + PM1_STS; |
| 773 | fadt->pm1b_evt_blk = 0x0; |
| 774 | fadt->pm1a_cnt_blk = pmbase + PM1_CNT; |
| 775 | fadt->pm1b_cnt_blk = 0x0; |
| 776 | fadt->pm2_cnt_blk = pmbase + PM2_CNT; |
| 777 | fadt->pm_tmr_blk = pmbase + PM1_TMR; |
| 778 | if (pch_is_lp()) |
| 779 | fadt->gpe0_blk = pmbase + LP_GPE0_STS_1; |
| 780 | else |
| 781 | fadt->gpe0_blk = pmbase + GPE0_STS; |
| 782 | fadt->gpe1_blk = 0; |
| 783 | |
| 784 | /* |
| 785 | * Some of the lengths here are doubled. This is because they describe |
| 786 | * blocks containing two registers, where the size of each register |
| 787 | * is found by halving the block length. See Table 5-34 and section |
| 788 | * 4.8.3 of the ACPI specification for details. |
| 789 | */ |
| 790 | fadt->pm1_evt_len = 2 * 2; |
| 791 | fadt->pm1_cnt_len = 2; |
| 792 | fadt->pm2_cnt_len = 1; |
| 793 | fadt->pm_tmr_len = 4; |
| 794 | if (pch_is_lp()) |
| 795 | fadt->gpe0_blk_len = 2 * 16; |
| 796 | else |
| 797 | fadt->gpe0_blk_len = 2 * 8; |
| 798 | fadt->gpe1_blk_len = 0; |
| 799 | fadt->gpe1_base = 0; |
| 800 | |
| 801 | fadt->cst_cnt = 0; |
| 802 | fadt->p_lvl2_lat = 1; |
| 803 | fadt->p_lvl3_lat = 87; |
| 804 | fadt->flush_size = 0; |
| 805 | fadt->flush_stride = 0; |
| 806 | fadt->duty_offset = 0; |
| 807 | fadt->duty_width = 0; |
| 808 | fadt->day_alrm = 0xd; |
| 809 | fadt->mon_alrm = 0x00; |
| 810 | fadt->century = 0x00; |
| 811 | fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; |
| 812 | |
| 813 | fadt->flags = ACPI_FADT_WBINVD | |
| 814 | ACPI_FADT_C1_SUPPORTED | |
| 815 | ACPI_FADT_C2_MP_SUPPORTED | |
| 816 | ACPI_FADT_SLEEP_BUTTON | |
| 817 | ACPI_FADT_RESET_REGISTER | |
| 818 | ACPI_FADT_SEALED_CASE | |
| 819 | ACPI_FADT_S4_RTC_WAKE | |
| 820 | ACPI_FADT_PLATFORM_CLOCK; |
| 821 | |
| 822 | if (cfg->docking_supported) |
| 823 | fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; |
| 824 | |
| 825 | fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; |
| 826 | fadt->reset_reg.bit_width = 8; |
| 827 | fadt->reset_reg.bit_offset = 0; |
| 828 | fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; |
| 829 | fadt->reset_reg.addrl = 0xcf9; |
| 830 | fadt->reset_reg.addrh = 0; |
| 831 | |
| 832 | fadt->reset_value = 6; |
| 833 | |
| 834 | fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 835 | fadt->x_pm1a_evt_blk.bit_width = 2 * 16; |
| 836 | fadt->x_pm1a_evt_blk.bit_offset = 0; |
| 837 | fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; |
| 838 | fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; |
| 839 | fadt->x_pm1a_evt_blk.addrh = 0x0; |
| 840 | |
| 841 | fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 842 | fadt->x_pm1b_evt_blk.bit_width = 0; |
| 843 | fadt->x_pm1b_evt_blk.bit_offset = 0; |
| 844 | fadt->x_pm1b_evt_blk.access_size = 0; |
| 845 | fadt->x_pm1b_evt_blk.addrl = 0x0; |
| 846 | fadt->x_pm1b_evt_blk.addrh = 0x0; |
| 847 | |
| 848 | fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 849 | fadt->x_pm1a_cnt_blk.bit_width = 16; |
| 850 | fadt->x_pm1a_cnt_blk.bit_offset = 0; |
| 851 | fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; |
| 852 | fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; |
| 853 | fadt->x_pm1a_cnt_blk.addrh = 0x0; |
| 854 | |
| 855 | fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 856 | fadt->x_pm1b_cnt_blk.bit_width = 0; |
| 857 | fadt->x_pm1b_cnt_blk.bit_offset = 0; |
| 858 | fadt->x_pm1b_cnt_blk.access_size = 0; |
| 859 | fadt->x_pm1b_cnt_blk.addrl = 0x0; |
| 860 | fadt->x_pm1b_cnt_blk.addrh = 0x0; |
| 861 | |
| 862 | fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 863 | fadt->x_pm2_cnt_blk.bit_width = 8; |
| 864 | fadt->x_pm2_cnt_blk.bit_offset = 0; |
| 865 | fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; |
| 866 | fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT; |
| 867 | fadt->x_pm2_cnt_blk.addrh = 0x0; |
| 868 | |
| 869 | fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 870 | fadt->x_pm_tmr_blk.bit_width = 32; |
| 871 | fadt->x_pm_tmr_blk.bit_offset = 0; |
| 872 | fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; |
| 873 | fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; |
| 874 | fadt->x_pm_tmr_blk.addrh = 0x0; |
| 875 | |
| 876 | /* |
| 877 | * We don't set `fadt->x_gpe0_blk` for Lynx Point LP since the correct |
| 878 | * bit width is 128 * 2, which is too large for an 8 bit unsigned int. |
| 879 | * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`. |
| 880 | */ |
| 881 | if (!pch_is_lp()) { |
| 882 | fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 883 | fadt->x_gpe0_blk.bit_width = 2 * 64; |
| 884 | fadt->x_gpe0_blk.bit_offset = 0; |
| 885 | fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; |
| 886 | fadt->x_gpe0_blk.addrl = pmbase + GPE0_STS; |
| 887 | fadt->x_gpe0_blk.addrh = 0x0; |
| 888 | } else { |
| 889 | fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 890 | fadt->x_gpe0_blk.bit_width = 0; |
| 891 | fadt->x_gpe0_blk.bit_offset = 0; |
| 892 | fadt->x_gpe0_blk.access_size = 0; |
| 893 | fadt->x_gpe0_blk.addrl = 0x0; |
| 894 | fadt->x_gpe0_blk.addrh = 0x0; |
| 895 | } |
| 896 | |
| 897 | fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 898 | fadt->x_gpe1_blk.bit_width = 0; |
| 899 | fadt->x_gpe1_blk.bit_offset = 0; |
| 900 | fadt->x_gpe1_blk.access_size = 0; |
| 901 | fadt->x_gpe1_blk.addrl = 0x0; |
| 902 | fadt->x_gpe1_blk.addrh = 0x0; |
| 903 | } |
| 904 | |
Tristan Corrick | f3127d4 | 2018-10-31 02:25:54 +1300 | [diff] [blame] | 905 | static const char *lpc_acpi_name(const struct device *dev) |
| 906 | { |
| 907 | return "LPCB"; |
| 908 | } |
| 909 | |
| 910 | static void southbridge_fill_ssdt(struct device *dev) |
| 911 | { |
| 912 | intel_acpi_gen_def_acpi_pirq(dev); |
| 913 | } |
| 914 | |
Elyes HAOUAS | 7a5f771 | 2018-06-08 17:20:38 +0200 | [diff] [blame] | 915 | static unsigned long southbridge_write_acpi_tables(struct device *device, |
Alexander Couzens | 83fc32f | 2015-04-12 22:28:37 +0200 | [diff] [blame] | 916 | unsigned long start, |
| 917 | struct acpi_rsdp *rsdp) |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 918 | { |
| 919 | unsigned long current; |
| 920 | acpi_hpet_t *hpet; |
| 921 | acpi_header_t *ssdt; |
| 922 | |
| 923 | current = start; |
| 924 | |
| 925 | /* Align ACPI tables to 16byte */ |
Aaron Durbin | 07a1b28 | 2015-12-10 17:07:38 -0600 | [diff] [blame] | 926 | current = acpi_align_current(current); |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 927 | |
| 928 | /* |
| 929 | * We explicitly add these tables later on: |
| 930 | */ |
| 931 | printk(BIOS_DEBUG, "ACPI: * HPET\n"); |
| 932 | |
| 933 | hpet = (acpi_hpet_t *) current; |
| 934 | current += sizeof(acpi_hpet_t); |
Aaron Durbin | 07a1b28 | 2015-12-10 17:07:38 -0600 | [diff] [blame] | 935 | current = acpi_align_current(current); |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 936 | acpi_create_intel_hpet(hpet); |
| 937 | acpi_add_table(rsdp, hpet); |
| 938 | |
Aaron Durbin | 07a1b28 | 2015-12-10 17:07:38 -0600 | [diff] [blame] | 939 | current = acpi_align_current(current); |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 940 | |
| 941 | printk(BIOS_DEBUG, "ACPI: * SSDT2\n"); |
| 942 | ssdt = (acpi_header_t *)current; |
| 943 | acpi_create_serialio_ssdt(ssdt); |
| 944 | current += ssdt->length; |
| 945 | acpi_add_table(rsdp, ssdt); |
Aaron Durbin | 07a1b28 | 2015-12-10 17:07:38 -0600 | [diff] [blame] | 946 | current = acpi_align_current(current); |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 947 | |
| 948 | printk(BIOS_DEBUG, "current = %lx\n", current); |
| 949 | return current; |
| 950 | } |
| 951 | |
Tristan Corrick | 32ceed8 | 2018-11-30 22:53:27 +1300 | [diff] [blame] | 952 | static void lpc_final(struct device *dev) |
| 953 | { |
Arthur Heymans | a3121b0 | 2019-05-28 13:46:49 +0200 | [diff] [blame] | 954 | spi_finalize_ops(); |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame] | 955 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 956 | if (acpi_is_wakeup_s3() || CONFIG(INTEL_CHIPSET_LOCKDOWN)) |
Tristan Corrick | 32ceed8 | 2018-11-30 22:53:27 +1300 | [diff] [blame] | 957 | outb(APM_CNT_FINALIZE, APM_CNT); |
| 958 | } |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 959 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 960 | static struct pci_operations pci_ops = { |
Subrata Banik | 4a0f071 | 2019-03-20 14:29:47 +0530 | [diff] [blame] | 961 | .set_subsystem = pci_dev_set_subsystem, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 962 | }; |
| 963 | |
| 964 | static struct device_operations device_ops = { |
| 965 | .read_resources = pch_lpc_read_resources, |
| 966 | .set_resources = pci_dev_set_resources, |
Duncan Laurie | 8d783b8 | 2013-05-14 11:16:34 -0700 | [diff] [blame] | 967 | .enable_resources = pci_dev_enable_resources, |
Tristan Corrick | f3127d4 | 2018-10-31 02:25:54 +1300 | [diff] [blame] | 968 | .acpi_fill_ssdt_generator = southbridge_fill_ssdt, |
Vladimir Serbinenko | 334fd8e | 2014-10-05 11:10:35 +0200 | [diff] [blame] | 969 | .acpi_inject_dsdt_generator = southbridge_inject_dsdt, |
Tristan Corrick | f3127d4 | 2018-10-31 02:25:54 +1300 | [diff] [blame] | 970 | .acpi_name = lpc_acpi_name, |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 971 | .write_acpi_tables = southbridge_write_acpi_tables, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 972 | .init = lpc_init, |
Tristan Corrick | 32ceed8 | 2018-11-30 22:53:27 +1300 | [diff] [blame] | 973 | .final = lpc_final, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 974 | .enable = pch_lpc_enable, |
Nico Huber | 51b75ae | 2019-03-14 16:02:05 +0100 | [diff] [blame] | 975 | .scan_bus = scan_static_bus, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 976 | .ops_pci = &pci_ops, |
| 977 | }; |
| 978 | |
| 979 | |
Aaron Durbin | c1989c4 | 2012-12-11 17:13:17 -0600 | [diff] [blame] | 980 | /* IDs for LPC device of Intel 8 Series Chipset (Lynx Point) */ |
| 981 | static const unsigned short pci_device_ids[] = { |
| 982 | 0x8c41, /* Mobile Full Featured Engineering Sample. */ |
| 983 | 0x8c42, /* Desktop Full Featured Engineering Sample. */ |
| 984 | 0x8c44, /* Z87 SKU */ |
| 985 | 0x8c46, /* Z85 SKU */ |
| 986 | 0x8c49, /* HM86 SKU */ |
| 987 | 0x8c4a, /* H87 SKU */ |
| 988 | 0x8c4b, /* HM87 SKU */ |
| 989 | 0x8c4c, /* Q85 SKU */ |
| 990 | 0x8c4e, /* Q87 SKU */ |
| 991 | 0x8c4f, /* QM87 SKU */ |
Tristan Corrick | 9a08574 | 2018-10-31 02:20:28 +1300 | [diff] [blame] | 992 | 0x8c50, /* B85 SKU */ |
| 993 | 0x8c52, /* C222 SKU */ |
| 994 | 0x8c54, /* C224 SKU */ |
| 995 | 0x8c56, /* C226 SKU */ |
| 996 | 0x8c5c, /* H81 SKU */ |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 997 | 0x9c41, /* LP Full Featured Engineering Sample */ |
| 998 | 0x9c43, /* LP Premium SKU */ |
| 999 | 0x9c45, /* LP Mainstream SKU */ |
| 1000 | 0x9c47, /* LP Value SKU */ |
Aaron Durbin | c1989c4 | 2012-12-11 17:13:17 -0600 | [diff] [blame] | 1001 | 0 }; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1002 | |
| 1003 | static const struct pci_driver pch_lpc __pci_driver = { |
| 1004 | .ops = &device_ops, |
| 1005 | .vendor = PCI_VENDOR_ID_INTEL, |
| 1006 | .devices = pci_device_ids, |
| 1007 | }; |