Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 5 | * Copyright 2013 Google Inc. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of |
| 10 | * the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #include <console/console.h> |
| 19 | #include <device/device.h> |
| 20 | #include <device/pci.h> |
| 21 | #include <device/pci_ids.h> |
Patrick Rudolph | e56189c | 2018-04-18 10:11:59 +0200 | [diff] [blame] | 22 | #include <device/pci_ops.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 23 | #include <pc80/mc146818rtc.h> |
| 24 | #include <pc80/isa-dma.h> |
| 25 | #include <pc80/i8259.h> |
| 26 | #include <arch/io.h> |
| 27 | #include <arch/ioapic.h> |
| 28 | #include <arch/acpi.h> |
| 29 | #include <cpu/cpu.h> |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 30 | #include <cpu/x86/smm.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 31 | #include <elog.h> |
Duncan Laurie | 9c07c8f | 2013-03-22 11:08:39 -0700 | [diff] [blame] | 32 | #include <cbmem.h> |
| 33 | #include <string.h> |
| 34 | #include "nvs.h" |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 35 | #include "pch.h" |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 36 | #include <arch/acpigen.h> |
| 37 | #include <cbmem.h> |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 38 | #include <drivers/intel/gma/i915.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 39 | |
| 40 | #define NMI_OFF 0 |
| 41 | |
| 42 | #define ENABLE_ACPI_MODE_IN_COREBOOT 0 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 43 | |
| 44 | typedef struct southbridge_intel_lynxpoint_config config_t; |
| 45 | |
Paul Menzel | 373a20c | 2013-05-03 12:17:02 +0200 | [diff] [blame] | 46 | /** |
| 47 | * Set miscellanous static southbridge features. |
| 48 | * |
| 49 | * @param dev PCI device with I/O APIC control registers |
| 50 | */ |
| 51 | static void pch_enable_ioapic(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 52 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 53 | u32 reg32; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 54 | |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 55 | /* Assign unique bus/dev/fn for I/O APIC */ |
| 56 | pci_write_config16(dev, LPC_IBDF, |
| 57 | PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3); |
| 58 | |
Paul Menzel | 373a20c | 2013-05-03 12:17:02 +0200 | [diff] [blame] | 59 | /* Enable ACPI I/O range decode */ |
| 60 | pci_write_config8(dev, ACPI_CNTL, ACPI_EN); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 61 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 62 | set_ioapic_id(VIO_APIC_VADDR, 0x02); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 63 | |
| 64 | /* affirm full set of redirection table entries ("write once") */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 65 | reg32 = io_apic_read(VIO_APIC_VADDR, 0x01); |
Duncan Laurie | c593999 | 2013-05-24 11:06:49 -0700 | [diff] [blame] | 66 | if (pch_is_lp()) { |
| 67 | /* PCH-LP has 39 redirection entries */ |
| 68 | reg32 &= ~0x00ff0000; |
| 69 | reg32 |= 0x00270000; |
| 70 | } |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 71 | io_apic_write(VIO_APIC_VADDR, 0x01, reg32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 72 | |
Paul Menzel | 373a20c | 2013-05-03 12:17:02 +0200 | [diff] [blame] | 73 | /* |
| 74 | * Select Boot Configuration register (0x03) and |
| 75 | * use Processor System Bus (0x01) to deliver interrupts. |
| 76 | */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 77 | io_apic_write(VIO_APIC_VADDR, 0x03, 0x01); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 78 | } |
| 79 | |
| 80 | static void pch_enable_serial_irqs(struct device *dev) |
| 81 | { |
| 82 | /* Set packet length and toggle silent mode bit for one frame. */ |
| 83 | pci_write_config8(dev, SERIRQ_CNTL, |
| 84 | (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); |
Martin Roth | 7a1a3ad | 2017-06-24 21:29:38 -0600 | [diff] [blame] | 85 | #if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 86 | pci_write_config8(dev, SERIRQ_CNTL, |
| 87 | (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); |
| 88 | #endif |
| 89 | } |
| 90 | |
| 91 | /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control |
| 92 | * 0x00 - 0000 = Reserved |
| 93 | * 0x01 - 0001 = Reserved |
| 94 | * 0x02 - 0010 = Reserved |
| 95 | * 0x03 - 0011 = IRQ3 |
| 96 | * 0x04 - 0100 = IRQ4 |
| 97 | * 0x05 - 0101 = IRQ5 |
| 98 | * 0x06 - 0110 = IRQ6 |
| 99 | * 0x07 - 0111 = IRQ7 |
| 100 | * 0x08 - 1000 = Reserved |
| 101 | * 0x09 - 1001 = IRQ9 |
| 102 | * 0x0A - 1010 = IRQ10 |
| 103 | * 0x0B - 1011 = IRQ11 |
| 104 | * 0x0C - 1100 = IRQ12 |
| 105 | * 0x0D - 1101 = Reserved |
| 106 | * 0x0E - 1110 = IRQ14 |
| 107 | * 0x0F - 1111 = IRQ15 |
| 108 | * PIRQ[n]_ROUT[7] - PIRQ Routing Control |
| 109 | * 0x80 - The PIRQ is not routed. |
| 110 | */ |
| 111 | |
| 112 | static void pch_pirq_init(device_t dev) |
| 113 | { |
| 114 | device_t irq_dev; |
| 115 | /* Get the chip configuration */ |
| 116 | config_t *config = dev->chip_info; |
| 117 | |
| 118 | pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing); |
| 119 | pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing); |
| 120 | pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing); |
| 121 | pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing); |
| 122 | |
| 123 | pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing); |
| 124 | pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing); |
| 125 | pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing); |
| 126 | pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing); |
| 127 | |
| 128 | /* Eric Biederman once said we should let the OS do this. |
| 129 | * I am not so sure anymore he was right. |
| 130 | */ |
| 131 | |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 132 | for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 133 | u8 int_pin=0, int_line=0; |
| 134 | |
| 135 | if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) |
| 136 | continue; |
| 137 | |
| 138 | int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); |
| 139 | |
| 140 | switch (int_pin) { |
| 141 | case 1: /* INTA# */ int_line = config->pirqa_routing; break; |
| 142 | case 2: /* INTB# */ int_line = config->pirqb_routing; break; |
| 143 | case 3: /* INTC# */ int_line = config->pirqc_routing; break; |
| 144 | case 4: /* INTD# */ int_line = config->pirqd_routing; break; |
| 145 | } |
| 146 | |
| 147 | if (!int_line) |
| 148 | continue; |
| 149 | |
| 150 | pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); |
| 151 | } |
| 152 | } |
| 153 | |
| 154 | static void pch_gpi_routing(device_t dev) |
| 155 | { |
| 156 | /* Get the chip configuration */ |
| 157 | config_t *config = dev->chip_info; |
| 158 | u32 reg32 = 0; |
| 159 | |
| 160 | /* An array would be much nicer here, or some |
| 161 | * other method of doing this. |
| 162 | */ |
| 163 | reg32 |= (config->gpi0_routing & 0x03) << 0; |
| 164 | reg32 |= (config->gpi1_routing & 0x03) << 2; |
| 165 | reg32 |= (config->gpi2_routing & 0x03) << 4; |
| 166 | reg32 |= (config->gpi3_routing & 0x03) << 6; |
| 167 | reg32 |= (config->gpi4_routing & 0x03) << 8; |
| 168 | reg32 |= (config->gpi5_routing & 0x03) << 10; |
| 169 | reg32 |= (config->gpi6_routing & 0x03) << 12; |
| 170 | reg32 |= (config->gpi7_routing & 0x03) << 14; |
| 171 | reg32 |= (config->gpi8_routing & 0x03) << 16; |
| 172 | reg32 |= (config->gpi9_routing & 0x03) << 18; |
| 173 | reg32 |= (config->gpi10_routing & 0x03) << 20; |
| 174 | reg32 |= (config->gpi11_routing & 0x03) << 22; |
| 175 | reg32 |= (config->gpi12_routing & 0x03) << 24; |
| 176 | reg32 |= (config->gpi13_routing & 0x03) << 26; |
| 177 | reg32 |= (config->gpi14_routing & 0x03) << 28; |
| 178 | reg32 |= (config->gpi15_routing & 0x03) << 30; |
| 179 | |
Kyösti Mälkki | b85a87b | 2014-12-29 11:32:27 +0200 | [diff] [blame] | 180 | pci_write_config32(dev, GPIO_ROUT, reg32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 181 | } |
| 182 | |
| 183 | static void pch_power_options(device_t dev) |
| 184 | { |
| 185 | u8 reg8; |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 186 | u16 reg16; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 187 | u32 reg32; |
| 188 | const char *state; |
| 189 | /* Get the chip configuration */ |
| 190 | config_t *config = dev->chip_info; |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 191 | u16 pmbase = get_pmbase(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 192 | int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; |
| 193 | int nmi_option; |
| 194 | |
| 195 | /* Which state do we want to goto after g3 (power restored)? |
| 196 | * 0 == S0 Full On |
| 197 | * 1 == S5 Soft Off |
| 198 | * |
| 199 | * If the option is not existent (Laptops), use Kconfig setting. |
| 200 | */ |
| 201 | get_option(&pwr_on, "power_on_after_fail"); |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 202 | pwr_on = MAINBOARD_POWER_KEEP; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 203 | |
| 204 | reg16 = pci_read_config16(dev, GEN_PMCON_3); |
| 205 | reg16 &= 0xfffe; |
| 206 | switch (pwr_on) { |
| 207 | case MAINBOARD_POWER_OFF: |
| 208 | reg16 |= 1; |
| 209 | state = "off"; |
| 210 | break; |
| 211 | case MAINBOARD_POWER_ON: |
| 212 | reg16 &= ~1; |
| 213 | state = "on"; |
| 214 | break; |
| 215 | case MAINBOARD_POWER_KEEP: |
| 216 | reg16 &= ~1; |
| 217 | state = "state keep"; |
| 218 | break; |
| 219 | default: |
| 220 | state = "undefined"; |
| 221 | } |
| 222 | |
| 223 | reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */ |
| 224 | reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */ |
| 225 | |
| 226 | reg16 &= ~(1 << 10); |
| 227 | reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */ |
| 228 | |
| 229 | reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */ |
| 230 | |
| 231 | pci_write_config16(dev, GEN_PMCON_3, reg16); |
| 232 | printk(BIOS_INFO, "Set power %s after power failure.\n", state); |
| 233 | |
| 234 | /* Set up NMI on errors. */ |
| 235 | reg8 = inb(0x61); |
| 236 | reg8 &= 0x0f; /* Higher Nibble must be 0 */ |
| 237 | reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */ |
| 238 | // reg8 &= ~(1 << 2); /* PCI SERR# Enable */ |
| 239 | reg8 |= (1 << 2); /* PCI SERR# Disable for now */ |
| 240 | outb(reg8, 0x61); |
| 241 | |
| 242 | reg8 = inb(0x70); |
| 243 | nmi_option = NMI_OFF; |
| 244 | get_option(&nmi_option, "nmi"); |
| 245 | if (nmi_option) { |
| 246 | printk(BIOS_INFO, "NMI sources enabled.\n"); |
| 247 | reg8 &= ~(1 << 7); /* Set NMI. */ |
| 248 | } else { |
| 249 | printk(BIOS_INFO, "NMI sources disabled.\n"); |
Elyes HAOUAS | 9c5d463 | 2018-04-26 22:21:21 +0200 | [diff] [blame^] | 250 | reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 251 | } |
| 252 | outb(reg8, 0x70); |
| 253 | |
| 254 | /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */ |
| 255 | reg16 = pci_read_config16(dev, GEN_PMCON_1); |
| 256 | reg16 &= ~(3 << 0); // SMI# rate 1 minute |
| 257 | reg16 &= ~(1 << 10); // Disable BIOS_PCI_EXP_EN for native PME |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 258 | pci_write_config16(dev, GEN_PMCON_1, reg16); |
| 259 | |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 260 | /* |
| 261 | * Set the board's GPI routing on LynxPoint-H. |
| 262 | * This is done as part of GPIO configuration on LynxPoint-LP. |
| 263 | */ |
| 264 | if (pch_is_lp()) |
| 265 | pch_gpi_routing(dev); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 266 | |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 267 | /* GPE setup based on device tree configuration */ |
| 268 | enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2, |
| 269 | config->gpe0_en_3, config->gpe0_en_4); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 270 | |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 271 | /* SMI setup based on device tree configuration */ |
| 272 | enable_alt_smi(config->alt_gp_smi_en); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 273 | |
| 274 | /* Set up power management block and determine sleep mode */ |
| 275 | reg32 = inl(pmbase + 0x04); // PM1_CNT |
| 276 | reg32 &= ~(7 << 10); // SLP_TYP |
| 277 | reg32 |= (1 << 0); // SCI_EN |
| 278 | outl(reg32, pmbase + 0x04); |
| 279 | |
| 280 | /* Clear magic status bits to prevent unexpected wake */ |
| 281 | reg32 = RCBA32(0x3310); |
| 282 | reg32 |= (1 << 4)|(1 << 5)|(1 << 0); |
| 283 | RCBA32(0x3310) = reg32; |
| 284 | |
Ryan Salsamendi | 889ce9c | 2017-06-30 17:45:14 -0700 | [diff] [blame] | 285 | reg16 = RCBA16(0x3f02); |
| 286 | reg16 &= ~0xf; |
| 287 | RCBA16(0x3f02) = reg16; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 288 | } |
| 289 | |
| 290 | static void pch_rtc_init(struct device *dev) |
| 291 | { |
Aaron Durbin | cfe7ad1 | 2017-09-15 14:59:27 -0600 | [diff] [blame] | 292 | int rtc_failed = rtc_failure(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 293 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 294 | if (rtc_failed) { |
Aaron Durbin | cfe7ad1 | 2017-09-15 14:59:27 -0600 | [diff] [blame] | 295 | if (IS_ENABLED(CONFIG_ELOG)) |
| 296 | elog_add_event(ELOG_TYPE_RTC_RESET); |
| 297 | pci_update_config8(dev, GEN_PMCON_3, ~RTC_BATTERY_DEAD, 0); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 298 | } |
Aaron Durbin | cfe7ad1 | 2017-09-15 14:59:27 -0600 | [diff] [blame] | 299 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 300 | printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); |
| 301 | |
Gabe Black | b3f08c6 | 2014-04-30 17:12:25 -0700 | [diff] [blame] | 302 | cmos_init(rtc_failed); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 303 | } |
| 304 | |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 305 | /* LynxPoint PCH Power Management init */ |
| 306 | static void lpt_pm_init(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 307 | { |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 308 | printk(BIOS_DEBUG, "LynxPoint PM init\n"); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 309 | } |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 310 | |
| 311 | const struct rcba_config_instruction lpt_lp_pm_rcba[] = { |
Duncan Laurie | 4bc107b | 2013-06-24 13:14:44 -0700 | [diff] [blame] | 312 | RCBA_RMW_REG_32(0x232c, ~1, 0x00000000), |
| 313 | RCBA_RMW_REG_32(0x1100, ~0xc000, 0xc000), |
| 314 | RCBA_RMW_REG_32(0x1100, ~0, 0x00000100), |
| 315 | RCBA_RMW_REG_32(0x1100, ~0, 0x0000003f), |
| 316 | RCBA_RMW_REG_32(0x2320, ~0x60, 0x10), |
| 317 | RCBA_RMW_REG_32(0x3314, 0, 0x00012fff), |
| 318 | RCBA_RMW_REG_32(0x3318, 0, 0x0dcf0400), |
| 319 | RCBA_RMW_REG_32(0x3324, 0, 0x04000000), |
| 320 | RCBA_RMW_REG_32(0x3368, 0, 0x00041400), |
| 321 | RCBA_RMW_REG_32(0x3388, 0, 0x3f8ddbff), |
| 322 | RCBA_RMW_REG_32(0x33ac, 0, 0x00007001), |
| 323 | RCBA_RMW_REG_32(0x33b0, 0, 0x00181900), |
| 324 | RCBA_RMW_REG_32(0x33c0, 0, 0x00060A00), |
| 325 | RCBA_RMW_REG_32(0x33d0, 0, 0x06200840), |
| 326 | RCBA_RMW_REG_32(0x3a28, 0, 0x01010101), |
| 327 | RCBA_RMW_REG_32(0x3a2c, 0, 0x04040404), |
| 328 | RCBA_RMW_REG_32(0x2b1c, 0, 0x03808033), |
| 329 | RCBA_RMW_REG_32(0x2b34, 0, 0x80000009), |
| 330 | RCBA_RMW_REG_32(0x3348, 0, 0x022ddfff), |
| 331 | RCBA_RMW_REG_32(0x334c, 0, 0x00000001), |
| 332 | RCBA_RMW_REG_32(0x3358, 0, 0x0001c000), |
| 333 | RCBA_RMW_REG_32(0x3380, 0, 0x3f8ddbff), |
| 334 | RCBA_RMW_REG_32(0x3384, 0, 0x0001c7e1), |
| 335 | RCBA_RMW_REG_32(0x338c, 0, 0x0001c7e1), |
| 336 | RCBA_RMW_REG_32(0x3398, 0, 0x0001c000), |
| 337 | RCBA_RMW_REG_32(0x33a8, 0, 0x00181900), |
| 338 | RCBA_RMW_REG_32(0x33dc, 0, 0x00080000), |
| 339 | RCBA_RMW_REG_32(0x33e0, 0, 0x00000001), |
| 340 | RCBA_RMW_REG_32(0x3a20, 0, 0x00000404), |
| 341 | RCBA_RMW_REG_32(0x3a24, 0, 0x01010101), |
| 342 | RCBA_RMW_REG_32(0x3a30, 0, 0x01010101), |
| 343 | RCBA_RMW_REG_32(0x0410, ~0, 0x00000003), |
| 344 | RCBA_RMW_REG_32(0x2618, ~0, 0x08000000), |
| 345 | RCBA_RMW_REG_32(0x2300, ~0, 0x00000002), |
| 346 | RCBA_RMW_REG_32(0x2600, ~0, 0x00000008), |
| 347 | RCBA_RMW_REG_32(0x33b4, 0, 0x00007001), |
| 348 | RCBA_RMW_REG_32(0x3350, 0, 0x022ddfff), |
| 349 | RCBA_RMW_REG_32(0x3354, 0, 0x00000001), |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 350 | RCBA_RMW_REG_32(0x33d4, ~0, 0x08000000), /* Power Optimizer */ |
Matt DeVillier | c97e042 | 2017-02-16 11:36:16 -0600 | [diff] [blame] | 351 | RCBA_RMW_REG_32(0x33c8, ~0, 0x00000080), /* Power Optimizer */ |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 352 | RCBA_RMW_REG_32(0x2b10, 0, 0x0000883c), /* Power Optimizer */ |
Duncan Laurie | 5cf34ce | 2013-04-26 10:41:33 -0700 | [diff] [blame] | 353 | RCBA_RMW_REG_32(0x2b14, 0, 0x1e0a4616), /* Power Optimizer */ |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 354 | RCBA_RMW_REG_32(0x2b24, 0, 0x40000005), /* Power Optimizer */ |
| 355 | RCBA_RMW_REG_32(0x2b20, 0, 0x0005db01), /* Power Optimizer */ |
Duncan Laurie | 4bc107b | 2013-06-24 13:14:44 -0700 | [diff] [blame] | 356 | RCBA_RMW_REG_32(0x3a80, 0, 0x05145005), |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 357 | RCBA_END_CONFIG |
| 358 | }; |
| 359 | |
| 360 | /* LynxPoint LP PCH Power Management init */ |
| 361 | static void lpt_lp_pm_init(struct device *dev) |
| 362 | { |
| 363 | struct southbridge_intel_lynxpoint_config *config = dev->chip_info; |
| 364 | u32 data; |
| 365 | |
| 366 | printk(BIOS_DEBUG, "LynxPoint LP PM init\n"); |
| 367 | |
| 368 | pci_write_config8(dev, 0xa9, 0x46); |
| 369 | |
| 370 | pch_config_rcba(lpt_lp_pm_rcba); |
| 371 | |
| 372 | pci_write_config32(dev, 0xac, |
| 373 | pci_read_config32(dev, 0xac) | (1 << 21)); |
| 374 | |
Elyes HAOUAS | a0aea56 | 2017-07-03 21:38:53 +0200 | [diff] [blame] | 375 | pch_iobp_update(0xED00015C, ~(1 << 11), 0x00003700); |
Duncan Laurie | 4bc107b | 2013-06-24 13:14:44 -0700 | [diff] [blame] | 376 | pch_iobp_update(0xED000118, ~0UL, 0x00c00000); |
| 377 | pch_iobp_update(0xED000120, ~0UL, 0x00240000); |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 378 | pch_iobp_update(0xCA000000, ~0UL, 0x00000009); |
| 379 | |
| 380 | /* Set RCBA CIR28 0x3A84 based on SATA port enables */ |
| 381 | data = 0x00001005; |
| 382 | /* Port 3 and 2 disabled */ |
| 383 | if ((config->sata_port_map & ((1 << 3)|(1 << 2))) == 0) |
| 384 | data |= (1 << 24) | (1 << 26); |
| 385 | /* Port 1 and 0 disabled */ |
| 386 | if ((config->sata_port_map & ((1 << 1)|(1 << 0))) == 0) |
| 387 | data |= (1 << 20) | (1 << 18); |
| 388 | RCBA32(0x3a84) = data; |
| 389 | |
Duncan Laurie | 5cf34ce | 2013-04-26 10:41:33 -0700 | [diff] [blame] | 390 | /* Set RCBA 0x2b1c[29]=1 if DSP disabled */ |
| 391 | if (RCBA32(FD) & PCH_DISABLE_ADSPD) |
| 392 | RCBA32_OR(0x2b1c, (1 << 29)); |
| 393 | |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 394 | /* Lock */ |
| 395 | RCBA32_OR(0x3a6c, 0x00000001); |
| 396 | |
| 397 | /* Set RCBA 0x33D4 after other setup */ |
| 398 | RCBA32_OR(0x33d4, 0x2fff2fb1); |
| 399 | |
| 400 | /* Set RCBA 0x33C8[15]=1 as last step */ |
| 401 | RCBA32_OR(0x33c8, (1 << 15)); |
| 402 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 403 | |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 404 | static void enable_hpet(struct device *const dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 405 | { |
| 406 | u32 reg32; |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 407 | size_t i; |
| 408 | |
| 409 | /* Assign unique bus/dev/fn for each HPET */ |
| 410 | for (i = 0; i < 8; ++i) |
| 411 | pci_write_config16(dev, LPC_HnBDF(i), |
| 412 | PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | i); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 413 | |
| 414 | /* Move HPET to default address 0xfed00000 and enable it */ |
| 415 | reg32 = RCBA32(HPTC); |
| 416 | reg32 |= (1 << 7); // HPET Address Enable |
| 417 | reg32 &= ~(3 << 0); |
| 418 | RCBA32(HPTC) = reg32; |
| 419 | /* Read it back to stick. It's affected by posted write syndrome. */ |
| 420 | reg32 = RCBA32(HPTC); |
| 421 | } |
| 422 | |
| 423 | static void enable_clock_gating(device_t dev) |
| 424 | { |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 425 | /* LynxPoint Mobile */ |
| 426 | u32 reg32; |
| 427 | u16 reg16; |
| 428 | |
| 429 | /* DMI */ |
| 430 | RCBA32_AND_OR(0x2234, ~0UL, 0xf); |
| 431 | reg16 = pci_read_config16(dev, GEN_PMCON_1); |
| 432 | reg16 |= (1 << 11) | (1 << 12) | (1 << 14); |
| 433 | reg16 |= (1 << 2); // PCI CLKRUN# Enable |
| 434 | pci_write_config16(dev, GEN_PMCON_1, reg16); |
| 435 | RCBA32_OR(0x900, (1 << 14)); |
| 436 | |
| 437 | reg32 = RCBA32(CG); |
| 438 | reg32 |= (1 << 22); // HDA Dynamic |
Ryan Salsamendi | 0d9b360 | 2017-06-30 17:15:57 -0700 | [diff] [blame] | 439 | reg32 |= (1UL << 31); // LPC Dynamic |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 440 | reg32 |= (1 << 16); // PCIe Dynamic |
| 441 | reg32 |= (1 << 27); // HPET Dynamic |
| 442 | reg32 |= (1 << 28); // GPIO Dynamic |
| 443 | RCBA32(CG) = reg32; |
| 444 | |
| 445 | RCBA32_OR(0x38c0, 0x7); // SPI Dynamic |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 446 | } |
| 447 | |
| 448 | static void enable_lp_clock_gating(device_t dev) |
| 449 | { |
| 450 | /* LynxPoint LP */ |
| 451 | u32 reg32; |
| 452 | u16 reg16; |
| 453 | |
| 454 | /* DMI */ |
| 455 | RCBA32_AND_OR(0x2234, ~0UL, 0xf); |
| 456 | reg16 = pci_read_config16(dev, GEN_PMCON_1); |
| 457 | reg16 &= ~((1 << 11) | (1 << 14)); |
| 458 | reg16 |= (1 << 5) | (1 << 6) | (1 << 7) | (1 << 12) | (1 << 13); |
| 459 | reg16 |= (1 << 2); // PCI CLKRUN# Enable |
| 460 | pci_write_config16(dev, GEN_PMCON_1, reg16); |
| 461 | |
| 462 | reg32 = pci_read_config32(dev, 0x64); |
| 463 | reg32 |= (1 << 6); |
| 464 | pci_write_config32(dev, 0x64, reg32); |
| 465 | |
Duncan Laurie | 4bc107b | 2013-06-24 13:14:44 -0700 | [diff] [blame] | 466 | /* |
| 467 | * RCBA + 0x2614[27:25,14:13,10,8] = 101,11,1,1 |
| 468 | * RCBA + 0x2614[23:16] = 0x20 |
| 469 | * RCBA + 0x2614[30:28] = 0x0 |
Duncan Laurie | d8c7d73 | 2013-07-16 09:01:43 -0700 | [diff] [blame] | 470 | * RCBA + 0x2614[26] = 1 (IF 0:2.0@0x08 >= 0x0b) |
Duncan Laurie | 4bc107b | 2013-06-24 13:14:44 -0700 | [diff] [blame] | 471 | */ |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 472 | RCBA32_AND_OR(0x2614, 0x8bffffff, 0x0a206500); |
Duncan Laurie | 4bc107b | 2013-06-24 13:14:44 -0700 | [diff] [blame] | 473 | |
| 474 | /* Check for LPT-LP B2 stepping and 0:31.0@0xFA > 4 */ |
Duncan Laurie | d8c7d73 | 2013-07-16 09:01:43 -0700 | [diff] [blame] | 475 | if (pci_read_config8(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x8) >= 0x0b) |
Elyes HAOUAS | a0aea56 | 2017-07-03 21:38:53 +0200 | [diff] [blame] | 476 | RCBA32_OR(0x2614, (1 << 26)); |
Duncan Laurie | 4bc107b | 2013-06-24 13:14:44 -0700 | [diff] [blame] | 477 | |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 478 | RCBA32_OR(0x900, 0x0000031f); |
| 479 | |
| 480 | reg32 = RCBA32(CG); |
Duncan Laurie | a2d6a40 | 2013-03-22 11:24:45 -0700 | [diff] [blame] | 481 | if (RCBA32(0x3454) & (1 << 4)) |
| 482 | reg32 &= ~(1 << 29); // LPC Dynamic |
| 483 | else |
| 484 | reg32 |= (1 << 29); // LPC Dynamic |
Ryan Salsamendi | 3f2fe18 | 2017-07-04 13:14:16 -0700 | [diff] [blame] | 485 | reg32 |= (1UL << 31); // LP LPC |
Duncan Laurie | 5cf34ce | 2013-04-26 10:41:33 -0700 | [diff] [blame] | 486 | reg32 |= (1 << 30); // LP BLA |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 487 | reg32 |= (1 << 28); // GPIO Dynamic |
| 488 | reg32 |= (1 << 27); // HPET Dynamic |
Duncan Laurie | 5cf34ce | 2013-04-26 10:41:33 -0700 | [diff] [blame] | 489 | reg32 |= (1 << 26); // Generic Platform Event Clock |
| 490 | if (RCBA32(BUC) & PCH_DISABLE_GBE) |
| 491 | reg32 |= (1 << 23); // GbE Static |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 492 | reg32 |= (1 << 22); // HDA Dynamic |
Duncan Laurie | 5cf34ce | 2013-04-26 10:41:33 -0700 | [diff] [blame] | 493 | reg32 |= (1 << 16); // PCI Dynamic |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 494 | RCBA32(CG) = reg32; |
| 495 | |
| 496 | RCBA32_OR(0x3434, 0x7); // LP LPC |
| 497 | |
| 498 | RCBA32_AND_OR(0x333c, 0xffcfffff, 0x00c00000); // SATA |
| 499 | |
| 500 | RCBA32_OR(0x38c0, 0x3c07); // SPI Dynamic |
| 501 | |
| 502 | pch_iobp_update(0xCF000000, ~0UL, 0x00007001); |
Duncan Laurie | 5cf34ce | 2013-04-26 10:41:33 -0700 | [diff] [blame] | 503 | pch_iobp_update(0xCE00C000, ~1UL, 0x00000000); // bit0=0 in BWG 1.4.0 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 504 | } |
| 505 | |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 506 | static void pch_set_acpi_mode(void) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 507 | { |
Martin Roth | 7a1a3ad | 2017-06-24 21:29:38 -0600 | [diff] [blame] | 508 | #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) |
Kyösti Mälkki | c3ed886 | 2014-06-19 19:50:51 +0300 | [diff] [blame] | 509 | if (!acpi_is_wakeup_s3()) { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 510 | #if ENABLE_ACPI_MODE_IN_COREBOOT |
| 511 | printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 512 | outb(APM_CNT_ACPI_ENABLE, APM_CNT); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 513 | printk(BIOS_DEBUG, "done.\n"); |
| 514 | #else |
| 515 | printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 516 | outb(APM_CNT_ACPI_DISABLE, APM_CNT); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 517 | printk(BIOS_DEBUG, "done.\n"); |
| 518 | #endif |
| 519 | } |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 520 | #endif /* CONFIG_HAVE_SMI_HANDLER */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 521 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 522 | |
| 523 | static void pch_disable_smm_only_flashing(struct device *dev) |
| 524 | { |
| 525 | u8 reg8; |
| 526 | |
| 527 | printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); |
| 528 | reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ |
| 529 | reg8 &= ~(1 << 5); |
| 530 | pci_write_config8(dev, 0xdc, reg8); |
| 531 | } |
| 532 | |
| 533 | static void pch_fixups(struct device *dev) |
| 534 | { |
| 535 | u8 gen_pmcon_2; |
| 536 | |
| 537 | /* Indicate DRAM init done for MRC S3 to know it can resume */ |
| 538 | gen_pmcon_2 = pci_read_config8(dev, GEN_PMCON_2); |
| 539 | gen_pmcon_2 |= (1 << 7); |
| 540 | pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2); |
| 541 | |
| 542 | /* |
| 543 | * Enable DMI ASPM in the PCH |
| 544 | */ |
| 545 | RCBA32_AND_OR(0x2304, ~(1 << 10), 0); |
| 546 | RCBA32_OR(0x21a4, (1 << 11)|(1 << 10)); |
| 547 | RCBA32_OR(0x21a8, 0x3); |
| 548 | } |
| 549 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 550 | static void lpc_init(struct device *dev) |
| 551 | { |
| 552 | printk(BIOS_DEBUG, "pch: lpc_init\n"); |
| 553 | |
| 554 | /* Set the value for PCI command register. */ |
| 555 | pci_write_config16(dev, PCI_COMMAND, 0x000f); |
| 556 | |
| 557 | /* IO APIC initialization. */ |
Paul Menzel | 373a20c | 2013-05-03 12:17:02 +0200 | [diff] [blame] | 558 | pch_enable_ioapic(dev); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 559 | |
| 560 | pch_enable_serial_irqs(dev); |
| 561 | |
| 562 | /* Setup the PIRQ. */ |
| 563 | pch_pirq_init(dev); |
| 564 | |
| 565 | /* Setup power options. */ |
| 566 | pch_power_options(dev); |
| 567 | |
| 568 | /* Initialize power management */ |
Duncan Laurie | deb90f4 | 2013-03-08 17:22:37 -0800 | [diff] [blame] | 569 | if (pch_is_lp()) { |
| 570 | lpt_lp_pm_init(dev); |
| 571 | enable_lp_clock_gating(dev); |
| 572 | } else { |
| 573 | lpt_pm_init(dev); |
| 574 | enable_clock_gating(dev); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 575 | } |
| 576 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 577 | /* Initialize the real time clock. */ |
| 578 | pch_rtc_init(dev); |
| 579 | |
| 580 | /* Initialize ISA DMA. */ |
| 581 | isa_dma_init(); |
| 582 | |
| 583 | /* Initialize the High Precision Event Timers, if present. */ |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 584 | enable_hpet(dev); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 585 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 586 | setup_i8259(); |
| 587 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 588 | /* Interrupt 9 should be level triggered (SCI) */ |
| 589 | i8259_configure_irq_trigger(9, 1); |
| 590 | |
| 591 | pch_disable_smm_only_flashing(dev); |
| 592 | |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 593 | pch_set_acpi_mode(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 594 | |
| 595 | pch_fixups(dev); |
| 596 | } |
| 597 | |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 598 | static void pch_lpc_add_mmio_resources(device_t dev) |
| 599 | { |
| 600 | u32 reg; |
| 601 | struct resource *res; |
| 602 | const u32 default_decode_base = IO_APIC_ADDR; |
| 603 | |
| 604 | /* |
| 605 | * Just report all resources from IO-APIC base to 4GiB. Don't mark |
| 606 | * them reserved as that may upset the OS if this range is marked |
| 607 | * as reserved in the e820. |
| 608 | */ |
| 609 | res = new_resource(dev, OIC); |
| 610 | res->base = default_decode_base; |
| 611 | res->size = 0 - default_decode_base; |
| 612 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 613 | |
| 614 | /* RCBA */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 615 | if ((uintptr_t)DEFAULT_RCBA < default_decode_base) { |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 616 | res = new_resource(dev, RCBA); |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 617 | res->base = (resource_t)(uintptr_t)DEFAULT_RCBA; |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 618 | res->size = 16 * 1024; |
| 619 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | |
| 620 | IORESOURCE_FIXED | IORESOURCE_RESERVE; |
| 621 | } |
| 622 | |
| 623 | /* Check LPC Memory Decode register. */ |
| 624 | reg = pci_read_config32(dev, LGMR); |
| 625 | if (reg & 1) { |
| 626 | reg &= ~0xffff; |
| 627 | if (reg < default_decode_base) { |
| 628 | res = new_resource(dev, LGMR); |
| 629 | res->base = reg; |
| 630 | res->size = 16 * 1024; |
| 631 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | |
| 632 | IORESOURCE_FIXED | IORESOURCE_RESERVE; |
| 633 | } |
| 634 | } |
| 635 | } |
| 636 | |
| 637 | /* Default IO range claimed by the LPC device. The upper bound is exclusive. */ |
| 638 | #define LPC_DEFAULT_IO_RANGE_LOWER 0 |
| 639 | #define LPC_DEFAULT_IO_RANGE_UPPER 0x1000 |
| 640 | |
| 641 | static inline int pch_io_range_in_default(u16 base, u16 size) |
| 642 | { |
| 643 | /* Does it start above the range? */ |
| 644 | if (base >= LPC_DEFAULT_IO_RANGE_UPPER) |
| 645 | return 0; |
| 646 | |
| 647 | /* Is it entirely contained? */ |
| 648 | if (base >= LPC_DEFAULT_IO_RANGE_LOWER && |
| 649 | (base + size) < LPC_DEFAULT_IO_RANGE_UPPER) |
| 650 | return 1; |
| 651 | |
| 652 | /* This will return not in range for partial overlaps. */ |
| 653 | return 0; |
| 654 | } |
| 655 | |
| 656 | /* |
| 657 | * Note: this function assumes there is no overlap with the default LPC device's |
| 658 | * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. |
| 659 | */ |
| 660 | static void pch_lpc_add_io_resource(device_t dev, u16 base, u16 size, int index) |
| 661 | { |
| 662 | struct resource *res; |
| 663 | |
| 664 | if (pch_io_range_in_default(base, size)) |
| 665 | return; |
| 666 | |
| 667 | res = new_resource(dev, index); |
| 668 | res->base = base; |
| 669 | res->size = size; |
| 670 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 671 | } |
| 672 | |
| 673 | static void pch_lpc_add_gen_io_resources(device_t dev, int reg_value, int index) |
| 674 | { |
| 675 | /* |
| 676 | * Check if the register is enabled. If so and the base exceeds the |
| 677 | * device's deafult claim range add the resoure. |
| 678 | */ |
| 679 | if (reg_value & 1) { |
| 680 | u16 base = reg_value & 0xfffc; |
| 681 | u16 size = (0x3 | ((reg_value >> 16) & 0xfc)) + 1; |
| 682 | pch_lpc_add_io_resource(dev, base, size, index); |
| 683 | } |
| 684 | } |
| 685 | |
| 686 | static void pch_lpc_add_io_resources(device_t dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 687 | { |
| 688 | struct resource *res; |
| 689 | config_t *config = dev->chip_info; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 690 | |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 691 | /* Add the default claimed IO range for the LPC device. */ |
| 692 | res = new_resource(dev, 0); |
| 693 | res->base = LPC_DEFAULT_IO_RANGE_LOWER; |
| 694 | res->size = LPC_DEFAULT_IO_RANGE_UPPER - LPC_DEFAULT_IO_RANGE_LOWER; |
| 695 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 696 | |
| 697 | /* GPIOBASE */ |
Duncan Laurie | 7922b46 | 2013-03-08 16:34:33 -0800 | [diff] [blame] | 698 | pch_lpc_add_io_resource(dev, get_gpiobase(), DEFAULT_GPIOSIZE, |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 699 | GPIO_BASE); |
| 700 | |
| 701 | /* PMBASE */ |
Duncan Laurie | 7922b46 | 2013-03-08 16:34:33 -0800 | [diff] [blame] | 702 | pch_lpc_add_io_resource(dev, get_pmbase(), 256, PMBASE); |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 703 | |
| 704 | /* LPC Generic IO Decode range. */ |
| 705 | pch_lpc_add_gen_io_resources(dev, config->gen1_dec, LPC_GEN1_DEC); |
| 706 | pch_lpc_add_gen_io_resources(dev, config->gen2_dec, LPC_GEN2_DEC); |
| 707 | pch_lpc_add_gen_io_resources(dev, config->gen3_dec, LPC_GEN3_DEC); |
| 708 | pch_lpc_add_gen_io_resources(dev, config->gen4_dec, LPC_GEN4_DEC); |
| 709 | } |
| 710 | |
| 711 | static void pch_lpc_read_resources(device_t dev) |
| 712 | { |
Duncan Laurie | 9c07c8f | 2013-03-22 11:08:39 -0700 | [diff] [blame] | 713 | global_nvs_t *gnvs; |
| 714 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 715 | /* Get the normal PCI resources of this device. */ |
| 716 | pci_dev_read_resources(dev); |
| 717 | |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 718 | /* Add non-standard MMIO resources. */ |
| 719 | pch_lpc_add_mmio_resources(dev); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 720 | |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 721 | /* Add IO resources. */ |
| 722 | pch_lpc_add_io_resources(dev); |
Duncan Laurie | 9c07c8f | 2013-03-22 11:08:39 -0700 | [diff] [blame] | 723 | |
| 724 | /* Allocate ACPI NVS in CBMEM */ |
| 725 | gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); |
Kyösti Mälkki | c3ed886 | 2014-06-19 19:50:51 +0300 | [diff] [blame] | 726 | if (!acpi_is_wakeup_s3() && gnvs) |
Duncan Laurie | 9c07c8f | 2013-03-22 11:08:39 -0700 | [diff] [blame] | 727 | memset(gnvs, 0, sizeof(global_nvs_t)); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 728 | } |
| 729 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 730 | static void pch_lpc_enable(device_t dev) |
| 731 | { |
| 732 | /* Enable PCH Display Port */ |
| 733 | RCBA16(DISPBDF) = 0x0010; |
| 734 | RCBA32_OR(FD2, PCH_ENABLE_DBDF); |
| 735 | |
| 736 | pch_enable(dev); |
| 737 | } |
| 738 | |
| 739 | static void set_subsystem(device_t dev, unsigned vendor, unsigned device) |
| 740 | { |
| 741 | if (!vendor || !device) { |
| 742 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 743 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 744 | } else { |
| 745 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 746 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 747 | } |
| 748 | } |
| 749 | |
Alexander Couzens | a90dad1 | 2015-04-12 21:49:46 +0200 | [diff] [blame] | 750 | static void southbridge_inject_dsdt(device_t dev) |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 751 | { |
Vladimir Serbinenko | 7309c64 | 2014-10-05 11:07:33 +0200 | [diff] [blame] | 752 | global_nvs_t *gnvs; |
| 753 | |
| 754 | gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 755 | if (!gnvs) { |
Elyes HAOUAS | 035df00 | 2016-10-03 21:54:16 +0200 | [diff] [blame] | 756 | gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); |
Vladimir Serbinenko | 7309c64 | 2014-10-05 11:07:33 +0200 | [diff] [blame] | 757 | if (gnvs) |
| 758 | memset(gnvs, 0, sizeof(*gnvs)); |
| 759 | } |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 760 | |
| 761 | if (gnvs) { |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 762 | const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); |
| 763 | |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 764 | acpi_create_gnvs(gnvs); |
Vladimir Serbinenko | 1b409fd | 2014-10-12 00:26:21 +0200 | [diff] [blame] | 765 | |
| 766 | gnvs->apic = 1; |
| 767 | gnvs->mpen = 1; /* Enable Multi Processing */ |
| 768 | gnvs->pcnt = dev_count_cpu(); |
| 769 | |
Martin Roth | 7a1a3ad | 2017-06-24 21:29:38 -0600 | [diff] [blame] | 770 | #if IS_ENABLED(CONFIG_CHROMEOS) |
Vladimir Serbinenko | 1b409fd | 2014-10-12 00:26:21 +0200 | [diff] [blame] | 771 | chromeos_init_vboot(&(gnvs->chromeos)); |
| 772 | #endif |
| 773 | |
| 774 | /* Update the mem console pointer. */ |
| 775 | gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); |
| 776 | |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 777 | gnvs->ndid = gfx->ndid; |
| 778 | memcpy(gnvs->did, gfx->did, sizeof(gnvs->did)); |
| 779 | |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 780 | acpi_save_gnvs((unsigned long)gnvs); |
| 781 | /* And tell SMI about it */ |
| 782 | smm_setup_structures(gnvs, NULL, NULL); |
| 783 | |
Vladimir Serbinenko | 334fd8e | 2014-10-05 11:10:35 +0200 | [diff] [blame] | 784 | /* Add it to DSDT. */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 785 | acpigen_write_scope("\\"); |
| 786 | acpigen_write_name_dword("NVSA", (u32) gnvs); |
| 787 | acpigen_pop_len(); |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 788 | } |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 789 | } |
| 790 | |
Alexander Couzens | 83fc32f | 2015-04-12 22:28:37 +0200 | [diff] [blame] | 791 | static unsigned long southbridge_write_acpi_tables(device_t device, |
| 792 | unsigned long start, |
| 793 | struct acpi_rsdp *rsdp) |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 794 | { |
| 795 | unsigned long current; |
| 796 | acpi_hpet_t *hpet; |
| 797 | acpi_header_t *ssdt; |
| 798 | |
| 799 | current = start; |
| 800 | |
| 801 | /* Align ACPI tables to 16byte */ |
Aaron Durbin | 07a1b28 | 2015-12-10 17:07:38 -0600 | [diff] [blame] | 802 | current = acpi_align_current(current); |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 803 | |
| 804 | /* |
| 805 | * We explicitly add these tables later on: |
| 806 | */ |
| 807 | printk(BIOS_DEBUG, "ACPI: * HPET\n"); |
| 808 | |
| 809 | hpet = (acpi_hpet_t *) current; |
| 810 | current += sizeof(acpi_hpet_t); |
Aaron Durbin | 07a1b28 | 2015-12-10 17:07:38 -0600 | [diff] [blame] | 811 | current = acpi_align_current(current); |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 812 | acpi_create_intel_hpet(hpet); |
| 813 | acpi_add_table(rsdp, hpet); |
| 814 | |
Aaron Durbin | 07a1b28 | 2015-12-10 17:07:38 -0600 | [diff] [blame] | 815 | current = acpi_align_current(current); |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 816 | |
| 817 | printk(BIOS_DEBUG, "ACPI: * SSDT2\n"); |
| 818 | ssdt = (acpi_header_t *)current; |
| 819 | acpi_create_serialio_ssdt(ssdt); |
| 820 | current += ssdt->length; |
| 821 | acpi_add_table(rsdp, ssdt); |
Aaron Durbin | 07a1b28 | 2015-12-10 17:07:38 -0600 | [diff] [blame] | 822 | current = acpi_align_current(current); |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 823 | |
| 824 | printk(BIOS_DEBUG, "current = %lx\n", current); |
| 825 | return current; |
| 826 | } |
| 827 | |
| 828 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 829 | static struct pci_operations pci_ops = { |
| 830 | .set_subsystem = set_subsystem, |
| 831 | }; |
| 832 | |
| 833 | static struct device_operations device_ops = { |
| 834 | .read_resources = pch_lpc_read_resources, |
| 835 | .set_resources = pci_dev_set_resources, |
Duncan Laurie | 8d783b8 | 2013-05-14 11:16:34 -0700 | [diff] [blame] | 836 | .enable_resources = pci_dev_enable_resources, |
Vladimir Serbinenko | 334fd8e | 2014-10-05 11:10:35 +0200 | [diff] [blame] | 837 | .acpi_inject_dsdt_generator = southbridge_inject_dsdt, |
Vladimir Serbinenko | c6e566a | 2014-08-31 17:43:51 +0200 | [diff] [blame] | 838 | .write_acpi_tables = southbridge_write_acpi_tables, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 839 | .init = lpc_init, |
| 840 | .enable = pch_lpc_enable, |
Kyösti Mälkki | d0e212c | 2015-02-26 20:47:47 +0200 | [diff] [blame] | 841 | .scan_bus = scan_lpc_bus, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 842 | .ops_pci = &pci_ops, |
| 843 | }; |
| 844 | |
| 845 | |
Aaron Durbin | c1989c4 | 2012-12-11 17:13:17 -0600 | [diff] [blame] | 846 | /* IDs for LPC device of Intel 8 Series Chipset (Lynx Point) */ |
| 847 | static const unsigned short pci_device_ids[] = { |
| 848 | 0x8c41, /* Mobile Full Featured Engineering Sample. */ |
| 849 | 0x8c42, /* Desktop Full Featured Engineering Sample. */ |
| 850 | 0x8c44, /* Z87 SKU */ |
| 851 | 0x8c46, /* Z85 SKU */ |
| 852 | 0x8c49, /* HM86 SKU */ |
| 853 | 0x8c4a, /* H87 SKU */ |
| 854 | 0x8c4b, /* HM87 SKU */ |
| 855 | 0x8c4c, /* Q85 SKU */ |
| 856 | 0x8c4e, /* Q87 SKU */ |
| 857 | 0x8c4f, /* QM87 SKU */ |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 858 | 0x9c41, /* LP Full Featured Engineering Sample */ |
| 859 | 0x9c43, /* LP Premium SKU */ |
| 860 | 0x9c45, /* LP Mainstream SKU */ |
| 861 | 0x9c47, /* LP Value SKU */ |
Aaron Durbin | c1989c4 | 2012-12-11 17:13:17 -0600 | [diff] [blame] | 862 | 0 }; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 863 | |
| 864 | static const struct pci_driver pch_lpc __pci_driver = { |
| 865 | .ops = &device_ops, |
| 866 | .vendor = PCI_VENDOR_ID_INTEL, |
| 867 | .devices = pci_device_ids, |
| 868 | }; |