Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <console/console.h> |
| 22 | #include <device/device.h> |
| 23 | #include <device/pci.h> |
| 24 | #include <device/pci_ids.h> |
| 25 | #include <pc80/mc146818rtc.h> |
| 26 | #include <pc80/isa-dma.h> |
| 27 | #include <pc80/i8259.h> |
| 28 | #include <arch/io.h> |
| 29 | #include <arch/ioapic.h> |
| 30 | #include <arch/acpi.h> |
| 31 | #include <cpu/cpu.h> |
| 32 | #include <elog.h> |
| 33 | #include "pch.h" |
| 34 | |
| 35 | #define NMI_OFF 0 |
| 36 | |
| 37 | #define ENABLE_ACPI_MODE_IN_COREBOOT 0 |
| 38 | #define TEST_SMM_FLASH_LOCKDOWN 0 |
| 39 | |
| 40 | typedef struct southbridge_intel_lynxpoint_config config_t; |
| 41 | |
| 42 | static void pch_enable_apic(struct device *dev) |
| 43 | { |
| 44 | int i; |
| 45 | u32 reg32; |
| 46 | volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); |
| 47 | volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); |
| 48 | |
| 49 | /* Enable ACPI I/O and power management. |
| 50 | * Set SCI IRQ to IRQ9 |
| 51 | */ |
| 52 | pci_write_config8(dev, ACPI_CNTL, 0x80); |
| 53 | |
| 54 | *ioapic_index = 0; |
| 55 | *ioapic_data = (1 << 25); |
| 56 | |
| 57 | /* affirm full set of redirection table entries ("write once") */ |
| 58 | *ioapic_index = 1; |
| 59 | reg32 = *ioapic_data; |
| 60 | *ioapic_index = 1; |
| 61 | *ioapic_data = reg32; |
| 62 | |
| 63 | *ioapic_index = 0; |
| 64 | reg32 = *ioapic_data; |
| 65 | printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); |
| 66 | if (reg32 != (1 << 25)) |
| 67 | die("APIC Error\n"); |
| 68 | |
| 69 | printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); |
| 70 | for (i=0; i<3; i++) { |
| 71 | *ioapic_index = i; |
| 72 | printk(BIOS_SPEW, " reg 0x%04x:", i); |
| 73 | reg32 = *ioapic_data; |
| 74 | printk(BIOS_SPEW, " 0x%08x\n", reg32); |
| 75 | } |
| 76 | |
| 77 | *ioapic_index = 3; /* Select Boot Configuration register. */ |
| 78 | *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ |
| 79 | } |
| 80 | |
| 81 | static void pch_enable_serial_irqs(struct device *dev) |
| 82 | { |
| 83 | /* Set packet length and toggle silent mode bit for one frame. */ |
| 84 | pci_write_config8(dev, SERIRQ_CNTL, |
| 85 | (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); |
| 86 | #if !CONFIG_SERIRQ_CONTINUOUS_MODE |
| 87 | pci_write_config8(dev, SERIRQ_CNTL, |
| 88 | (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); |
| 89 | #endif |
| 90 | } |
| 91 | |
| 92 | /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control |
| 93 | * 0x00 - 0000 = Reserved |
| 94 | * 0x01 - 0001 = Reserved |
| 95 | * 0x02 - 0010 = Reserved |
| 96 | * 0x03 - 0011 = IRQ3 |
| 97 | * 0x04 - 0100 = IRQ4 |
| 98 | * 0x05 - 0101 = IRQ5 |
| 99 | * 0x06 - 0110 = IRQ6 |
| 100 | * 0x07 - 0111 = IRQ7 |
| 101 | * 0x08 - 1000 = Reserved |
| 102 | * 0x09 - 1001 = IRQ9 |
| 103 | * 0x0A - 1010 = IRQ10 |
| 104 | * 0x0B - 1011 = IRQ11 |
| 105 | * 0x0C - 1100 = IRQ12 |
| 106 | * 0x0D - 1101 = Reserved |
| 107 | * 0x0E - 1110 = IRQ14 |
| 108 | * 0x0F - 1111 = IRQ15 |
| 109 | * PIRQ[n]_ROUT[7] - PIRQ Routing Control |
| 110 | * 0x80 - The PIRQ is not routed. |
| 111 | */ |
| 112 | |
| 113 | static void pch_pirq_init(device_t dev) |
| 114 | { |
| 115 | device_t irq_dev; |
| 116 | /* Get the chip configuration */ |
| 117 | config_t *config = dev->chip_info; |
| 118 | |
| 119 | pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing); |
| 120 | pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing); |
| 121 | pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing); |
| 122 | pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing); |
| 123 | |
| 124 | pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing); |
| 125 | pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing); |
| 126 | pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing); |
| 127 | pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing); |
| 128 | |
| 129 | /* Eric Biederman once said we should let the OS do this. |
| 130 | * I am not so sure anymore he was right. |
| 131 | */ |
| 132 | |
| 133 | for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { |
| 134 | u8 int_pin=0, int_line=0; |
| 135 | |
| 136 | if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) |
| 137 | continue; |
| 138 | |
| 139 | int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); |
| 140 | |
| 141 | switch (int_pin) { |
| 142 | case 1: /* INTA# */ int_line = config->pirqa_routing; break; |
| 143 | case 2: /* INTB# */ int_line = config->pirqb_routing; break; |
| 144 | case 3: /* INTC# */ int_line = config->pirqc_routing; break; |
| 145 | case 4: /* INTD# */ int_line = config->pirqd_routing; break; |
| 146 | } |
| 147 | |
| 148 | if (!int_line) |
| 149 | continue; |
| 150 | |
| 151 | pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); |
| 152 | } |
| 153 | } |
| 154 | |
| 155 | static void pch_gpi_routing(device_t dev) |
| 156 | { |
| 157 | /* Get the chip configuration */ |
| 158 | config_t *config = dev->chip_info; |
| 159 | u32 reg32 = 0; |
| 160 | |
| 161 | /* An array would be much nicer here, or some |
| 162 | * other method of doing this. |
| 163 | */ |
| 164 | reg32 |= (config->gpi0_routing & 0x03) << 0; |
| 165 | reg32 |= (config->gpi1_routing & 0x03) << 2; |
| 166 | reg32 |= (config->gpi2_routing & 0x03) << 4; |
| 167 | reg32 |= (config->gpi3_routing & 0x03) << 6; |
| 168 | reg32 |= (config->gpi4_routing & 0x03) << 8; |
| 169 | reg32 |= (config->gpi5_routing & 0x03) << 10; |
| 170 | reg32 |= (config->gpi6_routing & 0x03) << 12; |
| 171 | reg32 |= (config->gpi7_routing & 0x03) << 14; |
| 172 | reg32 |= (config->gpi8_routing & 0x03) << 16; |
| 173 | reg32 |= (config->gpi9_routing & 0x03) << 18; |
| 174 | reg32 |= (config->gpi10_routing & 0x03) << 20; |
| 175 | reg32 |= (config->gpi11_routing & 0x03) << 22; |
| 176 | reg32 |= (config->gpi12_routing & 0x03) << 24; |
| 177 | reg32 |= (config->gpi13_routing & 0x03) << 26; |
| 178 | reg32 |= (config->gpi14_routing & 0x03) << 28; |
| 179 | reg32 |= (config->gpi15_routing & 0x03) << 30; |
| 180 | |
| 181 | pci_write_config32(dev, 0xb8, reg32); |
| 182 | } |
| 183 | |
| 184 | static void pch_power_options(device_t dev) |
| 185 | { |
| 186 | u8 reg8; |
| 187 | u16 reg16, pmbase; |
| 188 | u32 reg32; |
| 189 | const char *state; |
| 190 | /* Get the chip configuration */ |
| 191 | config_t *config = dev->chip_info; |
| 192 | |
| 193 | int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; |
| 194 | int nmi_option; |
| 195 | |
| 196 | /* Which state do we want to goto after g3 (power restored)? |
| 197 | * 0 == S0 Full On |
| 198 | * 1 == S5 Soft Off |
| 199 | * |
| 200 | * If the option is not existent (Laptops), use Kconfig setting. |
| 201 | */ |
| 202 | get_option(&pwr_on, "power_on_after_fail"); |
| 203 | |
| 204 | reg16 = pci_read_config16(dev, GEN_PMCON_3); |
| 205 | reg16 &= 0xfffe; |
| 206 | switch (pwr_on) { |
| 207 | case MAINBOARD_POWER_OFF: |
| 208 | reg16 |= 1; |
| 209 | state = "off"; |
| 210 | break; |
| 211 | case MAINBOARD_POWER_ON: |
| 212 | reg16 &= ~1; |
| 213 | state = "on"; |
| 214 | break; |
| 215 | case MAINBOARD_POWER_KEEP: |
| 216 | reg16 &= ~1; |
| 217 | state = "state keep"; |
| 218 | break; |
| 219 | default: |
| 220 | state = "undefined"; |
| 221 | } |
| 222 | |
| 223 | reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */ |
| 224 | reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */ |
| 225 | |
| 226 | reg16 &= ~(1 << 10); |
| 227 | reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */ |
| 228 | |
| 229 | reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */ |
| 230 | |
| 231 | pci_write_config16(dev, GEN_PMCON_3, reg16); |
| 232 | printk(BIOS_INFO, "Set power %s after power failure.\n", state); |
| 233 | |
| 234 | /* Set up NMI on errors. */ |
| 235 | reg8 = inb(0x61); |
| 236 | reg8 &= 0x0f; /* Higher Nibble must be 0 */ |
| 237 | reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */ |
| 238 | // reg8 &= ~(1 << 2); /* PCI SERR# Enable */ |
| 239 | reg8 |= (1 << 2); /* PCI SERR# Disable for now */ |
| 240 | outb(reg8, 0x61); |
| 241 | |
| 242 | reg8 = inb(0x70); |
| 243 | nmi_option = NMI_OFF; |
| 244 | get_option(&nmi_option, "nmi"); |
| 245 | if (nmi_option) { |
| 246 | printk(BIOS_INFO, "NMI sources enabled.\n"); |
| 247 | reg8 &= ~(1 << 7); /* Set NMI. */ |
| 248 | } else { |
| 249 | printk(BIOS_INFO, "NMI sources disabled.\n"); |
| 250 | reg8 |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ |
| 251 | } |
| 252 | outb(reg8, 0x70); |
| 253 | |
| 254 | /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */ |
| 255 | reg16 = pci_read_config16(dev, GEN_PMCON_1); |
| 256 | reg16 &= ~(3 << 0); // SMI# rate 1 minute |
| 257 | reg16 &= ~(1 << 10); // Disable BIOS_PCI_EXP_EN for native PME |
| 258 | #if DEBUG_PERIODIC_SMIS |
| 259 | /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using |
| 260 | * periodic SMIs. |
| 261 | */ |
| 262 | reg16 |= (3 << 0); // Periodic SMI every 8s |
| 263 | #endif |
| 264 | pci_write_config16(dev, GEN_PMCON_1, reg16); |
| 265 | |
| 266 | // Set the board's GPI routing. |
| 267 | pch_gpi_routing(dev); |
| 268 | |
| 269 | pmbase = pci_read_config16(dev, 0x40) & 0xfffe; |
| 270 | |
| 271 | outl(config->gpe0_en, pmbase + GPE0_EN); |
| 272 | outw(config->alt_gp_smi_en, pmbase + ALT_GP_SMI_EN); |
| 273 | |
| 274 | /* Set up power management block and determine sleep mode */ |
| 275 | reg32 = inl(pmbase + 0x04); // PM1_CNT |
| 276 | reg32 &= ~(7 << 10); // SLP_TYP |
| 277 | reg32 |= (1 << 0); // SCI_EN |
| 278 | outl(reg32, pmbase + 0x04); |
| 279 | |
| 280 | /* Clear magic status bits to prevent unexpected wake */ |
| 281 | reg32 = RCBA32(0x3310); |
| 282 | reg32 |= (1 << 4)|(1 << 5)|(1 << 0); |
| 283 | RCBA32(0x3310) = reg32; |
| 284 | |
| 285 | reg32 = RCBA32(0x3f02); |
| 286 | reg32 &= ~0xf; |
| 287 | RCBA32(0x3f02) = reg32; |
| 288 | } |
| 289 | |
| 290 | static void pch_rtc_init(struct device *dev) |
| 291 | { |
| 292 | u8 reg8; |
| 293 | int rtc_failed; |
| 294 | |
| 295 | reg8 = pci_read_config8(dev, GEN_PMCON_3); |
| 296 | rtc_failed = reg8 & RTC_BATTERY_DEAD; |
| 297 | if (rtc_failed) { |
| 298 | reg8 &= ~RTC_BATTERY_DEAD; |
| 299 | pci_write_config8(dev, GEN_PMCON_3, reg8); |
| 300 | #if CONFIG_ELOG |
| 301 | elog_add_event(ELOG_TYPE_RTC_RESET); |
| 302 | #endif |
| 303 | } |
| 304 | printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); |
| 305 | |
| 306 | rtc_init(rtc_failed); |
| 307 | } |
| 308 | |
| 309 | /* CougarPoint PCH Power Management init */ |
| 310 | #if 0 |
| 311 | static void cpt_pm_init(struct device *dev) |
| 312 | { |
| 313 | printk(BIOS_DEBUG, "CougarPoint PM init\n"); |
| 314 | pci_write_config8(dev, 0xa9, 0x47); |
| 315 | RCBA32_AND_OR(0x2238, ~0UL, (1 << 6)|(1 << 0)); |
| 316 | RCBA32_AND_OR(0x228c, ~0UL, (1 << 0)); |
| 317 | RCBA16_AND_OR(0x1100, ~0UL, (1 << 13)|(1 << 14)); |
| 318 | RCBA16_AND_OR(0x0900, ~0UL, (1 << 14)); |
| 319 | RCBA32(0x2304) = 0xc0388400; |
| 320 | RCBA32_AND_OR(0x2314, ~0UL, (1 << 5)|(1 << 18)); |
| 321 | RCBA32_AND_OR(0x2320, ~0UL, (1 << 15)|(1 << 1)); |
| 322 | RCBA32_AND_OR(0x3314, ~0x1f, 0xf); |
| 323 | RCBA32(0x3318) = 0x050f0000; |
| 324 | RCBA32(0x3324) = 0x04000000; |
| 325 | RCBA32_AND_OR(0x3340, ~0UL, 0xfffff); |
| 326 | RCBA32_AND_OR(0x3344, ~0UL, (1 << 1)); |
| 327 | RCBA32(0x3360) = 0x0001c000; |
| 328 | RCBA32(0x3368) = 0x00061100; |
| 329 | RCBA32(0x3378) = 0x7f8fdfff; |
| 330 | RCBA32(0x337c) = 0x000003fc; |
| 331 | RCBA32(0x3388) = 0x00001000; |
| 332 | RCBA32(0x3390) = 0x0001c000; |
| 333 | RCBA32(0x33a0) = 0x00000800; |
| 334 | RCBA32(0x33b0) = 0x00001000; |
| 335 | RCBA32(0x33c0) = 0x00093900; |
| 336 | RCBA32(0x33cc) = 0x24653002; |
| 337 | RCBA32(0x33d0) = 0x062108fe; |
| 338 | RCBA32_AND_OR(0x33d4, 0xf000f000, 0x00670060); |
| 339 | RCBA32(0x3a28) = 0x01010000; |
| 340 | RCBA32(0x3a2c) = 0x01010404; |
| 341 | RCBA32(0x3a80) = 0x01041041; |
| 342 | RCBA32_AND_OR(0x3a84, ~0x0000ffff, 0x00001001); |
| 343 | RCBA32_AND_OR(0x3a84, ~0UL, (1 << 24)); /* SATA 2/3 disabled */ |
| 344 | RCBA32_AND_OR(0x3a88, ~0UL, (1 << 0)); /* SATA 4/5 disabled */ |
| 345 | RCBA32(0x3a6c) = 0x00000001; |
| 346 | RCBA32_AND_OR(0x2344, 0x00ffff00, 0xff00000c); |
| 347 | RCBA32_AND_OR(0x80c, ~(0xff << 20), 0x11 << 20); |
| 348 | RCBA32(0x33c8) = 0; |
| 349 | RCBA32_AND_OR(0x21b0, ~0UL, 0xf); |
| 350 | } |
| 351 | #endif |
| 352 | |
| 353 | static void enable_hpet(void) |
| 354 | { |
| 355 | u32 reg32; |
| 356 | |
| 357 | /* Move HPET to default address 0xfed00000 and enable it */ |
| 358 | reg32 = RCBA32(HPTC); |
| 359 | reg32 |= (1 << 7); // HPET Address Enable |
| 360 | reg32 &= ~(3 << 0); |
| 361 | RCBA32(HPTC) = reg32; |
| 362 | /* Read it back to stick. It's affected by posted write syndrome. */ |
| 363 | reg32 = RCBA32(HPTC); |
| 364 | } |
| 365 | |
| 366 | static void enable_clock_gating(device_t dev) |
| 367 | { |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 368 | #if CONFIG_INTEL_LYNXPOINT_LP |
| 369 | /* LynxPoint LP */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 370 | u32 reg32; |
| 371 | u16 reg16; |
| 372 | |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 373 | /* DMI */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 374 | RCBA32_AND_OR(0x2234, ~0UL, 0xf); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 375 | reg16 = pci_read_config16(dev, GEN_PMCON_1); |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 376 | reg16 &= ~((1 << 11) | (1 << 14)); |
| 377 | reg16 |= (1 << 5) | (1 << 6) | (1 << 7) | (1 << 12) | (1 << 13); |
| 378 | reg16 |= (1 << 2); // PCI CLKRUN# Enable |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 379 | pci_write_config16(dev, GEN_PMCON_1, reg16); |
| 380 | |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 381 | reg32 = pci_read_config32(dev, 0x64); |
| 382 | reg32 |= (1 << 6); |
| 383 | pci_write_config32(dev, 0x64, reg32); |
| 384 | |
| 385 | RCBA32_AND_OR(0x2614, 0x8fffffff, 0x0f006500); |
| 386 | RCBA32_OR(0x900, 0x0000031f); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 387 | |
| 388 | reg32 = RCBA32(CG); |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 389 | reg32 |= (1 << 31); // LPC Dynamic |
| 390 | reg32 |= (1 << 30); // LP LPC |
| 391 | reg32 |= (1 << 28); // GPIO Dynamic |
| 392 | reg32 |= (1 << 27); // HPET Dynamic |
| 393 | reg32 |= (1 << 26); // LP LPC |
| 394 | reg32 |= (1 << 22); // HDA Dynamic |
| 395 | reg32 |= (1 << 16); // PCIe Dynamic |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 396 | RCBA32(CG) = reg32; |
| 397 | |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 398 | RCBA32_OR(0x3434, 0x7); // LP LPC |
| 399 | |
| 400 | RCBA32_AND_OR(0x333c, 0xff0fffff, 0x00800000); // SATA |
| 401 | |
| 402 | RCBA32_OR(0x38c0, 0x3c07); // SPI Dynamic |
| 403 | |
| 404 | pch_iobp_update(0xCF000000, ~0UL, 0x00007001); |
| 405 | pch_iobp_update(0xCE00C000, ~0UL, 0x00000001); |
| 406 | #else |
| 407 | /* LynxPoint Mobile */ |
| 408 | u32 reg32; |
| 409 | u16 reg16; |
| 410 | |
| 411 | /* DMI */ |
| 412 | RCBA32_AND_OR(0x2234, ~0UL, 0xf); |
| 413 | reg16 = pci_read_config16(dev, GEN_PMCON_1); |
| 414 | reg16 |= (1 << 11) | (1 << 12) | (1 << 14); |
| 415 | reg16 |= (1 << 2); // PCI CLKRUN# Enable |
| 416 | pci_write_config16(dev, GEN_PMCON_1, reg16); |
| 417 | RCBA32_OR(0x900, (1 << 14)); |
| 418 | |
| 419 | reg32 = RCBA32(CG); |
| 420 | reg32 |= (1 << 22); // HDA Dynamic |
| 421 | reg32 |= (1 << 31); // LPC Dynamic |
| 422 | reg32 |= (1 << 16); // PCIe Dynamic |
| 423 | reg32 |= (1 << 27); // HPET Dynamic |
| 424 | reg32 |= (1 << 28); // GPIO Dynamic |
| 425 | RCBA32(CG) = reg32; |
| 426 | |
| 427 | RCBA32_OR(0x38c0, 0x7); // SPI Dynamic |
| 428 | #endif |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 429 | } |
| 430 | |
| 431 | #if CONFIG_HAVE_SMI_HANDLER |
| 432 | static void pch_lock_smm(struct device *dev) |
| 433 | { |
| 434 | #if TEST_SMM_FLASH_LOCKDOWN |
| 435 | u8 reg8; |
| 436 | #endif |
| 437 | |
| 438 | if (acpi_slp_type != 3) { |
| 439 | #if ENABLE_ACPI_MODE_IN_COREBOOT |
| 440 | printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); |
| 441 | outb(0xe1, 0xb2); // Enable ACPI mode |
| 442 | printk(BIOS_DEBUG, "done.\n"); |
| 443 | #else |
| 444 | printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); |
| 445 | outb(0x1e, 0xb2); // Disable ACPI mode |
| 446 | printk(BIOS_DEBUG, "done.\n"); |
| 447 | #endif |
| 448 | } |
| 449 | |
| 450 | /* Don't allow evil boot loaders, kernels, or |
| 451 | * userspace applications to deceive us: |
| 452 | */ |
| 453 | smm_lock(); |
| 454 | |
| 455 | #if TEST_SMM_FLASH_LOCKDOWN |
| 456 | /* Now try this: */ |
| 457 | printk(BIOS_DEBUG, "Locking BIOS to RO... "); |
| 458 | reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ |
| 459 | printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", |
| 460 | (reg8&1)?"rw":"ro"); |
| 461 | reg8 &= ~(1 << 0); /* clear BIOSWE */ |
| 462 | pci_write_config8(dev, 0xdc, reg8); |
| 463 | reg8 |= (1 << 1); /* set BLE */ |
| 464 | pci_write_config8(dev, 0xdc, reg8); |
| 465 | printk(BIOS_DEBUG, "ok.\n"); |
| 466 | reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ |
| 467 | printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", |
| 468 | (reg8&1)?"rw":"ro"); |
| 469 | |
| 470 | printk(BIOS_DEBUG, "Writing:\n"); |
| 471 | *(volatile u8 *)0xfff00000 = 0x00; |
| 472 | printk(BIOS_DEBUG, "Testing:\n"); |
| 473 | reg8 |= (1 << 0); /* set BIOSWE */ |
| 474 | pci_write_config8(dev, 0xdc, reg8); |
| 475 | |
| 476 | reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ |
| 477 | printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", |
| 478 | (reg8&1)?"rw":"ro"); |
| 479 | printk(BIOS_DEBUG, "Done.\n"); |
| 480 | #endif |
| 481 | } |
| 482 | #endif |
| 483 | |
| 484 | static void pch_disable_smm_only_flashing(struct device *dev) |
| 485 | { |
| 486 | u8 reg8; |
| 487 | |
| 488 | printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); |
| 489 | reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ |
| 490 | reg8 &= ~(1 << 5); |
| 491 | pci_write_config8(dev, 0xdc, reg8); |
| 492 | } |
| 493 | |
| 494 | static void pch_fixups(struct device *dev) |
| 495 | { |
| 496 | u8 gen_pmcon_2; |
| 497 | |
| 498 | /* Indicate DRAM init done for MRC S3 to know it can resume */ |
| 499 | gen_pmcon_2 = pci_read_config8(dev, GEN_PMCON_2); |
| 500 | gen_pmcon_2 |= (1 << 7); |
| 501 | pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2); |
| 502 | |
| 503 | /* |
| 504 | * Enable DMI ASPM in the PCH |
| 505 | */ |
| 506 | RCBA32_AND_OR(0x2304, ~(1 << 10), 0); |
| 507 | RCBA32_OR(0x21a4, (1 << 11)|(1 << 10)); |
| 508 | RCBA32_OR(0x21a8, 0x3); |
| 509 | } |
| 510 | |
| 511 | static void pch_decode_init(struct device *dev) |
| 512 | { |
| 513 | config_t *config = dev->chip_info; |
| 514 | |
| 515 | printk(BIOS_DEBUG, "pch_decode_init\n"); |
| 516 | |
| 517 | pci_write_config32(dev, LPC_GEN1_DEC, config->gen1_dec); |
| 518 | pci_write_config32(dev, LPC_GEN2_DEC, config->gen2_dec); |
| 519 | pci_write_config32(dev, LPC_GEN3_DEC, config->gen3_dec); |
| 520 | pci_write_config32(dev, LPC_GEN4_DEC, config->gen4_dec); |
| 521 | } |
| 522 | |
| 523 | static void lpc_init(struct device *dev) |
| 524 | { |
| 525 | printk(BIOS_DEBUG, "pch: lpc_init\n"); |
| 526 | |
| 527 | /* Set the value for PCI command register. */ |
| 528 | pci_write_config16(dev, PCI_COMMAND, 0x000f); |
| 529 | |
| 530 | /* IO APIC initialization. */ |
| 531 | pch_enable_apic(dev); |
| 532 | |
| 533 | pch_enable_serial_irqs(dev); |
| 534 | |
| 535 | /* Setup the PIRQ. */ |
| 536 | pch_pirq_init(dev); |
| 537 | |
| 538 | /* Setup power options. */ |
| 539 | pch_power_options(dev); |
| 540 | |
| 541 | /* Initialize power management */ |
| 542 | switch (pch_silicon_type()) { |
| 543 | default: |
| 544 | printk(BIOS_ERR, "Unknown Chipset: 0x%04x\n", dev->device); |
| 545 | } |
| 546 | |
| 547 | /* Set the state of the GPIO lines. */ |
| 548 | //gpio_init(dev); |
| 549 | |
| 550 | /* Initialize the real time clock. */ |
| 551 | pch_rtc_init(dev); |
| 552 | |
| 553 | /* Initialize ISA DMA. */ |
| 554 | isa_dma_init(); |
| 555 | |
| 556 | /* Initialize the High Precision Event Timers, if present. */ |
| 557 | enable_hpet(); |
| 558 | |
| 559 | /* Initialize Clock Gating */ |
| 560 | enable_clock_gating(dev); |
| 561 | |
| 562 | setup_i8259(); |
| 563 | |
| 564 | /* The OS should do this? */ |
| 565 | /* Interrupt 9 should be level triggered (SCI) */ |
| 566 | i8259_configure_irq_trigger(9, 1); |
| 567 | |
| 568 | pch_disable_smm_only_flashing(dev); |
| 569 | |
| 570 | #if CONFIG_HAVE_SMI_HANDLER |
| 571 | pch_lock_smm(dev); |
| 572 | #endif |
| 573 | |
| 574 | pch_fixups(dev); |
| 575 | } |
| 576 | |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame^] | 577 | static void pch_lpc_add_mmio_resources(device_t dev) |
| 578 | { |
| 579 | u32 reg; |
| 580 | struct resource *res; |
| 581 | const u32 default_decode_base = IO_APIC_ADDR; |
| 582 | |
| 583 | /* |
| 584 | * Just report all resources from IO-APIC base to 4GiB. Don't mark |
| 585 | * them reserved as that may upset the OS if this range is marked |
| 586 | * as reserved in the e820. |
| 587 | */ |
| 588 | res = new_resource(dev, OIC); |
| 589 | res->base = default_decode_base; |
| 590 | res->size = 0 - default_decode_base; |
| 591 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 592 | |
| 593 | /* RCBA */ |
| 594 | if (DEFAULT_RCBA < default_decode_base) { |
| 595 | res = new_resource(dev, RCBA); |
| 596 | res->base = DEFAULT_RCBA; |
| 597 | res->size = 16 * 1024; |
| 598 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | |
| 599 | IORESOURCE_FIXED | IORESOURCE_RESERVE; |
| 600 | } |
| 601 | |
| 602 | /* Check LPC Memory Decode register. */ |
| 603 | reg = pci_read_config32(dev, LGMR); |
| 604 | if (reg & 1) { |
| 605 | reg &= ~0xffff; |
| 606 | if (reg < default_decode_base) { |
| 607 | res = new_resource(dev, LGMR); |
| 608 | res->base = reg; |
| 609 | res->size = 16 * 1024; |
| 610 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | |
| 611 | IORESOURCE_FIXED | IORESOURCE_RESERVE; |
| 612 | } |
| 613 | } |
| 614 | } |
| 615 | |
| 616 | /* Default IO range claimed by the LPC device. The upper bound is exclusive. */ |
| 617 | #define LPC_DEFAULT_IO_RANGE_LOWER 0 |
| 618 | #define LPC_DEFAULT_IO_RANGE_UPPER 0x1000 |
| 619 | |
| 620 | static inline int pch_io_range_in_default(u16 base, u16 size) |
| 621 | { |
| 622 | /* Does it start above the range? */ |
| 623 | if (base >= LPC_DEFAULT_IO_RANGE_UPPER) |
| 624 | return 0; |
| 625 | |
| 626 | /* Is it entirely contained? */ |
| 627 | if (base >= LPC_DEFAULT_IO_RANGE_LOWER && |
| 628 | (base + size) < LPC_DEFAULT_IO_RANGE_UPPER) |
| 629 | return 1; |
| 630 | |
| 631 | /* This will return not in range for partial overlaps. */ |
| 632 | return 0; |
| 633 | } |
| 634 | |
| 635 | /* |
| 636 | * Note: this function assumes there is no overlap with the default LPC device's |
| 637 | * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. |
| 638 | */ |
| 639 | static void pch_lpc_add_io_resource(device_t dev, u16 base, u16 size, int index) |
| 640 | { |
| 641 | struct resource *res; |
| 642 | |
| 643 | if (pch_io_range_in_default(base, size)) |
| 644 | return; |
| 645 | |
| 646 | res = new_resource(dev, index); |
| 647 | res->base = base; |
| 648 | res->size = size; |
| 649 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 650 | } |
| 651 | |
| 652 | static void pch_lpc_add_gen_io_resources(device_t dev, int reg_value, int index) |
| 653 | { |
| 654 | /* |
| 655 | * Check if the register is enabled. If so and the base exceeds the |
| 656 | * device's deafult claim range add the resoure. |
| 657 | */ |
| 658 | if (reg_value & 1) { |
| 659 | u16 base = reg_value & 0xfffc; |
| 660 | u16 size = (0x3 | ((reg_value >> 16) & 0xfc)) + 1; |
| 661 | pch_lpc_add_io_resource(dev, base, size, index); |
| 662 | } |
| 663 | } |
| 664 | |
| 665 | static void pch_lpc_add_io_resources(device_t dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 666 | { |
| 667 | struct resource *res; |
| 668 | config_t *config = dev->chip_info; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 669 | |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame^] | 670 | /* Add the default claimed IO range for the LPC device. */ |
| 671 | res = new_resource(dev, 0); |
| 672 | res->base = LPC_DEFAULT_IO_RANGE_LOWER; |
| 673 | res->size = LPC_DEFAULT_IO_RANGE_UPPER - LPC_DEFAULT_IO_RANGE_LOWER; |
| 674 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 675 | |
| 676 | /* GPIOBASE */ |
| 677 | pch_lpc_add_io_resource(dev, DEFAULT_GPIOBASE, DEFAULT_GPIOSIZE, |
| 678 | GPIO_BASE); |
| 679 | |
| 680 | /* PMBASE */ |
| 681 | pch_lpc_add_io_resource(dev, DEFAULT_PMBASE, 128, PMBASE); |
| 682 | |
| 683 | /* LPC Generic IO Decode range. */ |
| 684 | pch_lpc_add_gen_io_resources(dev, config->gen1_dec, LPC_GEN1_DEC); |
| 685 | pch_lpc_add_gen_io_resources(dev, config->gen2_dec, LPC_GEN2_DEC); |
| 686 | pch_lpc_add_gen_io_resources(dev, config->gen3_dec, LPC_GEN3_DEC); |
| 687 | pch_lpc_add_gen_io_resources(dev, config->gen4_dec, LPC_GEN4_DEC); |
| 688 | } |
| 689 | |
| 690 | static void pch_lpc_read_resources(device_t dev) |
| 691 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 692 | /* Get the normal PCI resources of this device. */ |
| 693 | pci_dev_read_resources(dev); |
| 694 | |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame^] | 695 | /* Add non-standard MMIO resources. */ |
| 696 | pch_lpc_add_mmio_resources(dev); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 697 | |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame^] | 698 | /* Add IO resources. */ |
| 699 | pch_lpc_add_io_resources(dev); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 700 | } |
| 701 | |
| 702 | static void pch_lpc_enable_resources(device_t dev) |
| 703 | { |
| 704 | pch_decode_init(dev); |
| 705 | return pci_dev_enable_resources(dev); |
| 706 | } |
| 707 | |
| 708 | static void pch_lpc_enable(device_t dev) |
| 709 | { |
| 710 | /* Enable PCH Display Port */ |
| 711 | RCBA16(DISPBDF) = 0x0010; |
| 712 | RCBA32_OR(FD2, PCH_ENABLE_DBDF); |
| 713 | |
| 714 | pch_enable(dev); |
| 715 | } |
| 716 | |
| 717 | static void set_subsystem(device_t dev, unsigned vendor, unsigned device) |
| 718 | { |
| 719 | if (!vendor || !device) { |
| 720 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 721 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 722 | } else { |
| 723 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 724 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 725 | } |
| 726 | } |
| 727 | |
| 728 | static struct pci_operations pci_ops = { |
| 729 | .set_subsystem = set_subsystem, |
| 730 | }; |
| 731 | |
| 732 | static struct device_operations device_ops = { |
| 733 | .read_resources = pch_lpc_read_resources, |
| 734 | .set_resources = pci_dev_set_resources, |
| 735 | .enable_resources = pch_lpc_enable_resources, |
| 736 | .init = lpc_init, |
| 737 | .enable = pch_lpc_enable, |
| 738 | .scan_bus = scan_static_bus, |
| 739 | .ops_pci = &pci_ops, |
| 740 | }; |
| 741 | |
| 742 | |
Aaron Durbin | c1989c4 | 2012-12-11 17:13:17 -0600 | [diff] [blame] | 743 | /* IDs for LPC device of Intel 8 Series Chipset (Lynx Point) */ |
| 744 | static const unsigned short pci_device_ids[] = { |
| 745 | 0x8c41, /* Mobile Full Featured Engineering Sample. */ |
| 746 | 0x8c42, /* Desktop Full Featured Engineering Sample. */ |
| 747 | 0x8c44, /* Z87 SKU */ |
| 748 | 0x8c46, /* Z85 SKU */ |
| 749 | 0x8c49, /* HM86 SKU */ |
| 750 | 0x8c4a, /* H87 SKU */ |
| 751 | 0x8c4b, /* HM87 SKU */ |
| 752 | 0x8c4c, /* Q85 SKU */ |
| 753 | 0x8c4e, /* Q87 SKU */ |
| 754 | 0x8c4f, /* QM87 SKU */ |
Duncan Laurie | 74c0d05 | 2012-12-17 11:31:40 -0800 | [diff] [blame] | 755 | 0x9c41, /* LP Full Featured Engineering Sample */ |
| 756 | 0x9c43, /* LP Premium SKU */ |
| 757 | 0x9c45, /* LP Mainstream SKU */ |
| 758 | 0x9c47, /* LP Value SKU */ |
Aaron Durbin | c1989c4 | 2012-12-11 17:13:17 -0600 | [diff] [blame] | 759 | 0 }; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 760 | |
| 761 | static const struct pci_driver pch_lpc __pci_driver = { |
| 762 | .ops = &device_ops, |
| 763 | .vendor = PCI_VENDOR_ID_INTEL, |
| 764 | .devices = pci_device_ids, |
| 765 | }; |
| 766 | |
| 767 | |