commit 84fa224b53b726bec2a75dfdedd234bf60b0246e
author Angel Pons <th3fanbus@gmail.com> Sat Oct 24 11:53:47 2020 +0200
committer Nico Huber <nico.h@gmx.de> Sat Oct 24 20:43:15 2020 +0000
tree bff11a3c6904b618407b9f48ef11ee28310d101f
parent 2f30e8ca03602c14fd98527f1ea54d2a80e4fd63

sb/intel/lynxpoint: Use spaces around `|`

Coding style says so.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I72386bbe4b38602a641bf8dc9448d6a3e95d297a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46718
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/southbridge/intel/lynxpoint/lpc.c

diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index a161087..5108fa5 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -265,7 +265,7 @@
 
 	/* Clear magic status bits to prevent unexpected wake */
 	reg32 = RCBA32(0x3310);
-	reg32 |= (1 << 4)|(1 << 5)|(1 << 0);
+	reg32 |= (1 << 4) | (1 << 5) | (1 << 0);
 	RCBA32(0x3310) = reg32;
 
 	reg16 = RCBA16(0x3f02);
@@ -345,10 +345,10 @@
 	/* Set RCBA CIR28 0x3A84 based on SATA port enables */
 	data = 0x00001005;
 	/* Port 3 and 2 disabled */
-	if ((config->sata_port_map & ((1 << 3)|(1 << 2))) == 0)
+	if ((config->sata_port_map & ((1 << 3) | (1 << 2))) == 0)
 		data |= (1 << 24) | (1 << 26);
 	/* Port 1 and 0 disabled */
-	if ((config->sata_port_map & ((1 << 1)|(1 << 0))) == 0)
+	if ((config->sata_port_map & ((1 << 1) | (1 << 0))) == 0)
 		data |= (1 << 20) | (1 << 18);
 	RCBA32(0x3a84) = data;
 
@@ -489,7 +489,7 @@
 	 * Enable DMI ASPM in the PCH
 	 */
 	RCBA32_AND_OR(0x2304, ~(1 << 10), 0);
-	RCBA32_OR(0x21a4, (1 << 11)|(1 << 10));
+	RCBA32_OR(0x21a4, (1 << 11) | (1 << 10));
 	RCBA32_OR(0x21a8, 0x3);
 }