Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007 AMD |
| 5 | * Written by Yinghai Lu <yinghailu@amd.com> for AMD. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
Paul Menzel | a46a712 | 2013-02-23 18:37:27 +0100 | [diff] [blame] | 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 20 | */ |
| 21 | |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 22 | #define FAM10_SCAN_PCI_BUS 0 |
| 23 | #define FAM10_ALLOCATE_IO_RANGE 1 |
| 24 | |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 25 | #include <stdint.h> |
| 26 | #include <string.h> |
| 27 | #include <device/pci_def.h> |
| 28 | #include <device/pci_ids.h> |
| 29 | #include <arch/io.h> |
| 30 | #include <device/pnp_def.h> |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 31 | #include <cpu/x86/lapic.h> |
Patrick Georgi | 12584e2 | 2010-05-08 09:14:51 +0000 | [diff] [blame] | 32 | #include <console/console.h> |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 33 | #include <lib.h> |
Uwe Hermann | 26535d6 | 2010-11-20 20:36:40 +0000 | [diff] [blame] | 34 | #include <spd.h> |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 35 | #include <cpu/amd/model_10xxx_rev.h> |
stepan | 836ae29 | 2010-12-08 05:42:47 +0000 | [diff] [blame] | 36 | #include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 37 | #include "northbridge/amd/amdfam10/raminit.h" |
| 38 | #include "northbridge/amd/amdfam10/amdfam10.h" |
Stefan Reinauer | bcb8c97 | 2010-04-25 18:06:32 +0000 | [diff] [blame] | 39 | #include "lib/delay.c" |
Kyösti Mälkki | c66f1cb | 2013-08-12 16:09:00 +0300 | [diff] [blame] | 40 | #include "cpu/x86/lapic.h" |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 41 | #include "northbridge/amd/amdfam10/reset_test.c" |
stepan | 8301d83 | 2010-12-08 07:07:33 +0000 | [diff] [blame] | 42 | #include "superio/winbond/w83627hf/early_serial.c" |
| 43 | #include "superio/winbond/w83627hf/early_init.c" |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 44 | #include "cpu/x86/bist.h" |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 45 | #include "northbridge/amd/amdfam10/debug.c" |
Stefan Reinauer | 5d3dee8 | 2010-04-14 11:40:34 +0000 | [diff] [blame] | 46 | #include "cpu/x86/mtrr/earlymtrr.c" |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 47 | #include "northbridge/amd/amdfam10/setup_resource_map.c" |
stepan | 836ae29 | 2010-12-08 05:42:47 +0000 | [diff] [blame] | 48 | #include "southbridge/nvidia/mcp55/early_ctrl.c" |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 49 | |
| 50 | #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) |
Uwe Hermann | 9b9791c | 2010-12-06 18:17:01 +0000 | [diff] [blame] | 51 | #define DUMMY_DEV PNP_DEV(0x2e, 0) |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 52 | |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 53 | static inline void activate_spd_rom(const struct mem_controller *ctrl) |
| 54 | { |
Knut Kujat | f7f9e92 | 2010-03-13 12:54:58 +0000 | [diff] [blame] | 55 | #define SMBUS_SWITCH1 0x70 |
| 56 | #define SMBUS_SWITCH2 0x72 |
| 57 | smbus_send_byte(SMBUS_SWITCH1, 5 & 0x0f); |
| 58 | smbus_send_byte(SMBUS_SWITCH2, (5 >> 4) & 0x0f); |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 59 | } |
| 60 | |
| 61 | static inline int spd_read_byte(unsigned device, unsigned address) |
| 62 | { |
| 63 | return smbus_read_byte(device, address); |
| 64 | } |
| 65 | |
| 66 | #include "northbridge/amd/amdfam10/amdfam10.h" |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 67 | #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" |
stepan | 8301d83 | 2010-12-08 07:07:33 +0000 | [diff] [blame] | 68 | #include "northbridge/amd/amdfam10/pci.c" |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 69 | #include "resourcemap.c" |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 70 | #include "cpu/amd/quadcore/quadcore.c" |
stepan | 836ae29 | 2010-12-08 05:42:47 +0000 | [diff] [blame] | 71 | #include "southbridge/nvidia/mcp55/early_setup_ss.h" |
| 72 | #include "southbridge/nvidia/mcp55/early_setup_car.c" |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 73 | #include "cpu/amd/car/post_cache_as_ram.c" |
Kyösti Mälkki | f0a13ce | 2013-12-08 07:20:48 +0200 | [diff] [blame^] | 74 | #include "cpu/amd/microcode.h" |
Xavi Drudis Ferran | 4c28a6f | 2011-02-26 23:29:44 +0000 | [diff] [blame] | 75 | |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 76 | #include "cpu/amd/model_10xxx/init_cpus.c" |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 77 | #include "northbridge/amd/amdfam10/early_ht.c" |
| 78 | |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 79 | static void sio_setup(void) |
| 80 | { |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 81 | uint32_t dword; |
| 82 | uint8_t byte; |
| 83 | enable_smbus(); |
| 84 | // smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */ |
| 85 | smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */ |
| 86 | |
| 87 | byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 88 | byte |= 0x20; |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 89 | pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 90 | |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 91 | dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); |
| 92 | dword |= (1<<0); |
| 93 | pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 94 | |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 95 | dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); |
| 96 | dword |= (1<<16); |
| 97 | pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 98 | } |
| 99 | |
Uwe Hermann | 26535d6 | 2010-11-20 20:36:40 +0000 | [diff] [blame] | 100 | static const u8 spd_addr[] = { |
| 101 | //first node |
| 102 | RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 103 | #if CONFIG_MAX_PHYSICAL_CPUS > 1 |
| 104 | //second node |
| 105 | RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, |
| 106 | #endif |
| 107 | #if CONFIG_MAX_PHYSICAL_CPUS > 2 |
| 108 | //third node |
| 109 | RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 110 | //forth node |
| 111 | RC03, DIMM4, DIMM6,0 , 0, DIMM5, DIMM7, 0, 0, |
| 112 | #endif |
| 113 | }; |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 114 | |
Knut Kujat | f7f9e92 | 2010-03-13 12:54:58 +0000 | [diff] [blame] | 115 | #define GPIO1_DEV PNP_DEV(0x2e, W83627HF_GAME_MIDI_GPIO1) |
| 116 | #define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2) |
| 117 | #define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3) |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 118 | |
Stefan Reinauer | 523ebd9 | 2010-04-14 18:59:42 +0000 | [diff] [blame] | 119 | static void write_GPIO(void) |
Knut Kujat | f7f9e92 | 2010-03-13 12:54:58 +0000 | [diff] [blame] | 120 | { |
| 121 | pnp_enter_ext_func_mode(GPIO1_DEV); |
| 122 | pnp_set_logical_device(GPIO1_DEV); |
| 123 | pnp_write_config(GPIO1_DEV, 0x30, 0x01); |
| 124 | pnp_write_config(GPIO1_DEV, 0x60, 0x00); |
| 125 | pnp_write_config(GPIO1_DEV, 0x61, 0x00); |
| 126 | pnp_write_config(GPIO1_DEV, 0x62, 0x00); |
| 127 | pnp_write_config(GPIO1_DEV, 0x63, 0x00); |
| 128 | pnp_write_config(GPIO1_DEV, 0x70, 0x00); |
| 129 | pnp_write_config(GPIO1_DEV, 0xf0, 0xff); |
| 130 | pnp_write_config(GPIO1_DEV, 0xf1, 0xff); |
| 131 | pnp_write_config(GPIO1_DEV, 0xf2, 0x00); |
| 132 | pnp_exit_ext_func_mode(GPIO1_DEV); |
| 133 | |
| 134 | pnp_enter_ext_func_mode(GPIO2_DEV); |
| 135 | pnp_set_logical_device(GPIO2_DEV); |
| 136 | pnp_write_config(GPIO2_DEV, 0x30, 0x01); |
| 137 | pnp_write_config(GPIO2_DEV, 0xf0, 0xef); |
| 138 | pnp_write_config(GPIO2_DEV, 0xf1, 0xff); |
| 139 | pnp_write_config(GPIO2_DEV, 0xf2, 0x00); |
| 140 | pnp_write_config(GPIO2_DEV, 0xf3, 0x00); |
| 141 | pnp_write_config(GPIO2_DEV, 0xf5, 0x48); |
| 142 | pnp_write_config(GPIO2_DEV, 0xf6, 0x00); |
| 143 | pnp_write_config(GPIO2_DEV, 0xf7, 0xc0); |
| 144 | pnp_exit_ext_func_mode(GPIO2_DEV); |
| 145 | |
| 146 | pnp_enter_ext_func_mode(GPIO3_DEV); |
| 147 | pnp_set_logical_device(GPIO3_DEV); |
| 148 | pnp_write_config(GPIO3_DEV, 0x30, 0x00); |
| 149 | pnp_write_config(GPIO3_DEV, 0xf0, 0xff); |
| 150 | pnp_write_config(GPIO3_DEV, 0xf1, 0xff); |
| 151 | pnp_write_config(GPIO3_DEV, 0xf2, 0xff); |
| 152 | pnp_write_config(GPIO3_DEV, 0xf3, 0x40); |
| 153 | pnp_exit_ext_func_mode(GPIO3_DEV); |
| 154 | } |
| 155 | |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 156 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 157 | { |
Patrick Georgi | bbc880e | 2012-11-20 18:20:56 +0100 | [diff] [blame] | 158 | struct sys_info *sysinfo = &sysinfo_car; |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 159 | u32 bsp_apicid = 0, val, wants_reset; |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 160 | msr_t msr; |
| 161 | |
Patrick Georgi | 2bd9100 | 2010-03-18 16:46:50 +0000 | [diff] [blame] | 162 | if (!cpu_init_detectedx && boot_cpu()) { |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 163 | /* Nothing special needs to be done to find bus 0 */ |
| 164 | /* Allow the HT devices to be found */ |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 165 | set_bsp_node_CHtExtNodeCfgEn(); |
| 166 | enumerate_ht_chain(); |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 167 | sio_setup(); |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 168 | } |
| 169 | |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 170 | post_code(0x30); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 171 | |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 172 | if (bist == 0) |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 173 | bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 174 | |
| 175 | post_code(0x32); |
| 176 | |
Uwe Hermann | 9b9791c | 2010-12-06 18:17:01 +0000 | [diff] [blame] | 177 | w83627hf_set_clksel_48(DUMMY_DEV); |
| 178 | w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 179 | |
Knut Kujat | f7f9e92 | 2010-03-13 12:54:58 +0000 | [diff] [blame] | 180 | console_init(); |
| 181 | write_GPIO(); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 182 | printk(BIOS_DEBUG, "\n"); |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 183 | |
| 184 | /* Halt if there was a built in self test failure */ |
| 185 | report_bist_failure(bist); |
| 186 | |
| 187 | val = cpuid_eax(1); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 188 | printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); |
Myles Watson | 08e0fb8 | 2010-03-22 16:33:25 +0000 | [diff] [blame] | 189 | printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 190 | printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid); |
Myles Watson | 08e0fb8 | 2010-03-22 16:33:25 +0000 | [diff] [blame] | 191 | printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 192 | |
| 193 | /* Setup sysinfo defaults */ |
| 194 | set_sysinfo_in_ram(0); |
| 195 | |
| 196 | update_microcode(val); |
Kyösti Mälkki | f0a13ce | 2013-12-08 07:20:48 +0200 | [diff] [blame^] | 197 | |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 198 | post_code(0x33); |
| 199 | |
| 200 | cpuSetAMDMSR(); |
| 201 | post_code(0x34); |
| 202 | |
| 203 | amd_ht_init(sysinfo); |
| 204 | post_code(0x35); |
| 205 | |
| 206 | /* Setup nodes PCI space and start core 0 AP init. */ |
| 207 | finalize_node_setup(sysinfo); |
| 208 | |
| 209 | /* Setup any mainboard PCI settings etc. */ |
| 210 | setup_mb_resource_map(); |
| 211 | post_code(0x36); |
| 212 | |
| 213 | /* wait for all the APs core0 started by finalize_node_setup. */ |
| 214 | /* FIXME: A bunch of cores are going to start output to serial at once. |
| 215 | * It would be nice to fixup prink spinlocks for ROM XIP mode. |
| 216 | * I think it could be done by putting the spinlock flag in the cache |
| 217 | * of the BSP located right after sysinfo. |
| 218 | */ |
| 219 | |
| 220 | wait_all_core0_started(); |
Patrick Georgi | e166782 | 2012-05-05 15:29:32 +0200 | [diff] [blame] | 221 | #if CONFIG_LOGICAL_CPUS |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 222 | /* Core0 on each node is configured. Now setup any additional cores. */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 223 | printk(BIOS_DEBUG, "start_other_cores()\n"); |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 224 | start_other_cores(); |
| 225 | post_code(0x37); |
| 226 | wait_all_other_cores_started(bsp_apicid); |
| 227 | #endif |
| 228 | |
| 229 | post_code(0x38); |
| 230 | |
Patrick Georgi | 76e8152 | 2010-11-16 21:25:29 +0000 | [diff] [blame] | 231 | #if CONFIG_SET_FIDVID |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 232 | msr = rdmsr(0xc0010071); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 233 | printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 234 | |
| 235 | /* FIXME: The sb fid change may survive the warm reset and only |
| 236 | * need to be done once.*/ |
| 237 | |
| 238 | enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); |
| 239 | post_code(0x39); |
| 240 | |
| 241 | if (!warm_reset_detect(0)) { // BSP is node 0 |
| 242 | init_fidvid_bsp(bsp_apicid, sysinfo->nodes); |
| 243 | } else { |
| 244 | init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 |
| 245 | } |
| 246 | |
| 247 | post_code(0x3A); |
| 248 | |
| 249 | /* show final fid and vid */ |
| 250 | msr=rdmsr(0xc0010071); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 251 | printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 252 | #endif |
| 253 | |
Stefan Reinauer | bcb8c97 | 2010-04-25 18:06:32 +0000 | [diff] [blame] | 254 | init_timer(); // Need to use TMICT to synconize FID/VID |
| 255 | |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 256 | wants_reset = mcp55_early_setup_x(); |
| 257 | |
| 258 | /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ |
| 259 | if (!warm_reset_detect(0)) { |
| 260 | print_info("...WARM RESET...\n\n\n"); |
| 261 | soft_reset(); |
| 262 | die("After soft_reset_x - shouldn't see this message!!!\n"); |
| 263 | } |
| 264 | |
| 265 | if (wants_reset) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 266 | printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n"); |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 267 | |
| 268 | post_code(0x3B); |
| 269 | |
| 270 | /* It's the time to set ctrl in sysinfo now; */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 271 | printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 272 | fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); |
| 273 | |
| 274 | post_code(0x3D); |
| 275 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 276 | //printk(BIOS_DEBUG, "enable_smbus()\n"); |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 277 | // enable_smbus(); /* enable in sio_setup */ |
| 278 | |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 279 | post_code(0x40); |
| 280 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 281 | printk(BIOS_DEBUG, "raminit_amdmct()\n"); |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 282 | raminit_amdmct(sysinfo); |
| 283 | post_code(0x41); |
| 284 | |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 285 | post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. |
| 286 | post_code(0x42); // Should never see this post code. |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 287 | } |
Scott Duplichan | 314dd0b | 2011-03-08 23:01:46 +0000 | [diff] [blame] | 288 | |
| 289 | /** |
| 290 | * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) |
| 291 | * Description: |
| 292 | * This routine is called every time a non-coherent chain is processed. |
| 293 | * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a |
| 294 | * swap list. The first part of the list controls the BUID assignment and the |
| 295 | * second part of the list provides the device to device linking. Device orientation |
| 296 | * can be detected automatically, or explicitly. See documentation for more details. |
| 297 | * |
| 298 | * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially |
| 299 | * based on each device's unit count. |
| 300 | * |
| 301 | * Parameters: |
| 302 | * @param[in] u8 node = The node on which this chain is located |
| 303 | * @param[in] u8 link = The link on the host for this chain |
| 304 | * @param[out] u8** list = supply a pointer to a list |
| 305 | * @param[out] BOOL result = true to use a manual list |
| 306 | * false to initialize the link automatically |
| 307 | */ |
| 308 | BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) |
| 309 | { |
| 310 | static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; |
| 311 | /* If the BUID was adjusted in early_ht we need to do the manual override */ |
| 312 | if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { |
| 313 | printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n"); |
| 314 | if ((node == 0) && (link == 0)) { /* BSP SB link */ |
| 315 | *List = swaplist; |
| 316 | return 1; |
| 317 | } |
| 318 | } |
| 319 | |
| 320 | return 0; |
| 321 | } |