commit 4c28a6f01870e017dbedb4a0bba1e91148077040
author Xavi Drudis Ferran <xdrudis@tinet.cat> Sat Feb 26 23:29:44 2011 +0000
committer Peter Stuge <peter@stuge.se> Sat Feb 26 23:29:44 2011 +0000
tree bf45e9ef2d9d7755cdf70321ae371ab395b631d7
parent 837403dddf7b05b1a2b1a09a2cd57975484c7568

Make AMD Fam10h CPU microcode updates optional in Expert mode

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6385 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/mainboard/supermicro/h8qme_fam10/romstage.c

diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index 1d6bcf4..f3f56c4 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -74,7 +74,11 @@
 #include "southbridge/nvidia/mcp55/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode/microcode.c"
+
+#if CONFIG_UPDATE_CPU_MICROCODE
 #include "cpu/amd/model_10xxx/update_microcode.c"
+#endif
+
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
 
@@ -197,7 +201,9 @@
  /* Setup sysinfo defaults */
  set_sysinfo_in_ram(0);
 
+#if CONFIG_UPDATE_CPU_MICROCODE
  update_microcode(val);
+#endif
  post_code(0x33);
 
  cpuSetAMDMSR();