Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007 AMD |
| 5 | * Written by Yinghai Lu <yinghailu@amd.com> for AMD. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 20 | */ |
| 21 | |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 22 | #define RAMINIT_SYSINFO 1 |
| 23 | |
| 24 | #define FAM10_SCAN_PCI_BUS 0 |
| 25 | #define FAM10_ALLOCATE_IO_RANGE 1 |
| 26 | |
| 27 | #define QRANK_DIMM_SUPPORT 1 |
| 28 | |
| 29 | #if CONFIG_LOGICAL_CPUS==1 |
| 30 | #define SET_NB_CFG_54 1 |
| 31 | #endif |
| 32 | |
Myles Watson | 9b43afd | 2010-04-08 15:09:53 +0000 | [diff] [blame] | 33 | #define SET_FIDVID 1 |
| 34 | #define SET_FIDVID_CORE_RANGE 0 |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 35 | |
| 36 | #include <stdint.h> |
| 37 | #include <string.h> |
| 38 | #include <device/pci_def.h> |
| 39 | #include <device/pci_ids.h> |
| 40 | #include <arch/io.h> |
| 41 | #include <device/pnp_def.h> |
| 42 | #include <arch/romcc_io.h> |
| 43 | #include <cpu/x86/lapic.h> |
| 44 | #include "option_table.h" |
| 45 | #include "pc80/mc146818rtc_early.c" |
| 46 | |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 47 | #include "pc80/serial.c" |
Stefan Reinauer | 5a1f597 | 2010-03-31 14:34:40 +0000 | [diff] [blame] | 48 | #include "console/console.c" |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 49 | #include "lib/ramtest.c" |
| 50 | |
| 51 | #include <cpu/amd/model_10xxx_rev.h> |
| 52 | |
Stefan Reinauer | bcb8c97 | 2010-04-25 18:06:32 +0000 | [diff] [blame^] | 53 | // for enable the FAN |
| 54 | #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 55 | #include "northbridge/amd/amdfam10/raminit.h" |
| 56 | #include "northbridge/amd/amdfam10/amdfam10.h" |
Stefan Reinauer | bcb8c97 | 2010-04-25 18:06:32 +0000 | [diff] [blame^] | 57 | #include "cpu/amd/model_10xxx/apic_timer.c" |
| 58 | #include "lib/delay.c" |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 59 | #include "cpu/x86/lapic/boot_cpu.c" |
| 60 | #include "northbridge/amd/amdfam10/reset_test.c" |
| 61 | #include "superio/winbond/w83627hf/w83627hf_early_serial.c" |
| 62 | #include "superio/winbond/w83627hf/w83627hf_early_init.c" |
| 63 | |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 64 | #include "cpu/x86/bist.h" |
| 65 | |
| 66 | #include "northbridge/amd/amdfam10/debug.c" |
| 67 | |
Stefan Reinauer | 5d3dee8 | 2010-04-14 11:40:34 +0000 | [diff] [blame] | 68 | #include "cpu/x86/mtrr/earlymtrr.c" |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 69 | |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 70 | #include "northbridge/amd/amdfam10/setup_resource_map.c" |
| 71 | |
| 72 | #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) |
| 73 | |
| 74 | #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" |
| 75 | |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 76 | static inline void activate_spd_rom(const struct mem_controller *ctrl) |
| 77 | { |
Knut Kujat | f7f9e92 | 2010-03-13 12:54:58 +0000 | [diff] [blame] | 78 | #define SMBUS_SWITCH1 0x70 |
| 79 | #define SMBUS_SWITCH2 0x72 |
| 80 | smbus_send_byte(SMBUS_SWITCH1, 5 & 0x0f); |
| 81 | smbus_send_byte(SMBUS_SWITCH2, (5 >> 4) & 0x0f); |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 82 | } |
| 83 | |
| 84 | static inline int spd_read_byte(unsigned device, unsigned address) |
| 85 | { |
| 86 | return smbus_read_byte(device, address); |
| 87 | } |
| 88 | |
| 89 | #include "northbridge/amd/amdfam10/amdfam10.h" |
| 90 | #include "northbridge/amd/amdht/ht_wrapper.c" |
| 91 | |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 92 | #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" |
| 93 | #include "northbridge/amd/amdfam10/raminit_amdmct.c" |
| 94 | #include "northbridge/amd/amdfam10/amdfam10_pci.c" |
| 95 | |
| 96 | #include "resourcemap.c" |
| 97 | |
| 98 | #include "cpu/amd/quadcore/quadcore.c" |
| 99 | |
| 100 | #define MCP55_NUM 1 |
Knut Kujat | 4801e32 | 2010-02-24 08:48:35 +0000 | [diff] [blame] | 101 | #define MCP55_USE_NIC 0 |
| 102 | #define MCP55_USE_AZA 0 |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 103 | |
| 104 | #define MCP55_PCI_E_X_0 4 |
| 105 | |
| 106 | #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" |
| 107 | #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" |
| 108 | |
Stefan Reinauer | 853263b | 2010-04-09 10:43:49 +0000 | [diff] [blame] | 109 | |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 110 | |
| 111 | #include "cpu/amd/car/post_cache_as_ram.c" |
| 112 | |
Myles Watson | 075fbe8 | 2010-04-15 05:19:29 +0000 | [diff] [blame] | 113 | #include "cpu/amd/microcode/microcode.c" |
| 114 | #include "cpu/amd/model_10xxx/update_microcode.c" |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 115 | #include "cpu/amd/model_10xxx/init_cpus.c" |
| 116 | |
| 117 | #include "cpu/amd/model_10xxx/fidvid.c" |
| 118 | |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 119 | #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" |
| 120 | #include "northbridge/amd/amdfam10/early_ht.c" |
| 121 | |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 122 | static void sio_setup(void) |
| 123 | { |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 124 | uint32_t dword; |
| 125 | uint8_t byte; |
| 126 | enable_smbus(); |
| 127 | // smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */ |
| 128 | smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */ |
| 129 | |
| 130 | byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); |
| 131 | byte |= 0x20; |
| 132 | pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); |
| 133 | |
| 134 | dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); |
| 135 | dword |= (1<<0); |
| 136 | pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); |
| 137 | |
| 138 | dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); |
| 139 | dword |= (1<<16); |
| 140 | pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); |
| 141 | |
| 142 | } |
| 143 | |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 144 | #include "spd_addr.h" |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 145 | |
Knut Kujat | f7f9e92 | 2010-03-13 12:54:58 +0000 | [diff] [blame] | 146 | #define GPIO1_DEV PNP_DEV(0x2e, W83627HF_GAME_MIDI_GPIO1) |
| 147 | #define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2) |
| 148 | #define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3) |
Stefan Reinauer | 523ebd9 | 2010-04-14 18:59:42 +0000 | [diff] [blame] | 149 | static void write_GPIO(void) |
Knut Kujat | f7f9e92 | 2010-03-13 12:54:58 +0000 | [diff] [blame] | 150 | { |
| 151 | pnp_enter_ext_func_mode(GPIO1_DEV); |
| 152 | pnp_set_logical_device(GPIO1_DEV); |
| 153 | pnp_write_config(GPIO1_DEV, 0x30, 0x01); |
| 154 | pnp_write_config(GPIO1_DEV, 0x60, 0x00); |
| 155 | pnp_write_config(GPIO1_DEV, 0x61, 0x00); |
| 156 | pnp_write_config(GPIO1_DEV, 0x62, 0x00); |
| 157 | pnp_write_config(GPIO1_DEV, 0x63, 0x00); |
| 158 | pnp_write_config(GPIO1_DEV, 0x70, 0x00); |
| 159 | pnp_write_config(GPIO1_DEV, 0xf0, 0xff); |
| 160 | pnp_write_config(GPIO1_DEV, 0xf1, 0xff); |
| 161 | pnp_write_config(GPIO1_DEV, 0xf2, 0x00); |
| 162 | pnp_exit_ext_func_mode(GPIO1_DEV); |
| 163 | |
| 164 | pnp_enter_ext_func_mode(GPIO2_DEV); |
| 165 | pnp_set_logical_device(GPIO2_DEV); |
| 166 | pnp_write_config(GPIO2_DEV, 0x30, 0x01); |
| 167 | pnp_write_config(GPIO2_DEV, 0xf0, 0xef); |
| 168 | pnp_write_config(GPIO2_DEV, 0xf1, 0xff); |
| 169 | pnp_write_config(GPIO2_DEV, 0xf2, 0x00); |
| 170 | pnp_write_config(GPIO2_DEV, 0xf3, 0x00); |
| 171 | pnp_write_config(GPIO2_DEV, 0xf5, 0x48); |
| 172 | pnp_write_config(GPIO2_DEV, 0xf6, 0x00); |
| 173 | pnp_write_config(GPIO2_DEV, 0xf7, 0xc0); |
| 174 | pnp_exit_ext_func_mode(GPIO2_DEV); |
| 175 | |
| 176 | pnp_enter_ext_func_mode(GPIO3_DEV); |
| 177 | pnp_set_logical_device(GPIO3_DEV); |
| 178 | pnp_write_config(GPIO3_DEV, 0x30, 0x00); |
| 179 | pnp_write_config(GPIO3_DEV, 0xf0, 0xff); |
| 180 | pnp_write_config(GPIO3_DEV, 0xf1, 0xff); |
| 181 | pnp_write_config(GPIO3_DEV, 0xf2, 0xff); |
| 182 | pnp_write_config(GPIO3_DEV, 0xf3, 0x40); |
| 183 | pnp_exit_ext_func_mode(GPIO3_DEV); |
| 184 | } |
| 185 | |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 186 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 187 | { |
| 188 | struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); |
| 189 | |
| 190 | u32 bsp_apicid = 0; |
| 191 | u32 val; |
| 192 | u32 wants_reset; |
| 193 | msr_t msr; |
| 194 | |
Patrick Georgi | 2bd9100 | 2010-03-18 16:46:50 +0000 | [diff] [blame] | 195 | if (!cpu_init_detectedx && boot_cpu()) { |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 196 | /* Nothing special needs to be done to find bus 0 */ |
| 197 | /* Allow the HT devices to be found */ |
| 198 | |
| 199 | set_bsp_node_CHtExtNodeCfgEn(); |
| 200 | enumerate_ht_chain(); |
| 201 | |
| 202 | sio_setup(); |
| 203 | |
| 204 | /* Setup the mcp55 */ |
| 205 | mcp55_enable_rom(); |
| 206 | } |
| 207 | |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 208 | post_code(0x30); |
| 209 | |
| 210 | if (bist == 0) { |
| 211 | bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); |
| 212 | } |
| 213 | |
| 214 | post_code(0x32); |
| 215 | |
| 216 | pnp_enter_ext_func_mode(SERIAL_DEV); |
| 217 | pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6)); |
| 218 | w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); |
| 219 | pnp_exit_ext_func_mode(SERIAL_DEV); |
| 220 | |
Knut Kujat | f7f9e92 | 2010-03-13 12:54:58 +0000 | [diff] [blame] | 221 | uart_init(); |
| 222 | console_init(); |
| 223 | write_GPIO(); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 224 | printk(BIOS_DEBUG, "\n"); |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 225 | |
| 226 | /* Halt if there was a built in self test failure */ |
| 227 | report_bist_failure(bist); |
| 228 | |
| 229 | val = cpuid_eax(1); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 230 | printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); |
Myles Watson | 08e0fb8 | 2010-03-22 16:33:25 +0000 | [diff] [blame] | 231 | printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 232 | printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid); |
Myles Watson | 08e0fb8 | 2010-03-22 16:33:25 +0000 | [diff] [blame] | 233 | printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 234 | |
| 235 | /* Setup sysinfo defaults */ |
| 236 | set_sysinfo_in_ram(0); |
| 237 | |
| 238 | update_microcode(val); |
| 239 | post_code(0x33); |
| 240 | |
| 241 | cpuSetAMDMSR(); |
| 242 | post_code(0x34); |
| 243 | |
| 244 | amd_ht_init(sysinfo); |
| 245 | post_code(0x35); |
| 246 | |
| 247 | /* Setup nodes PCI space and start core 0 AP init. */ |
| 248 | finalize_node_setup(sysinfo); |
| 249 | |
| 250 | /* Setup any mainboard PCI settings etc. */ |
| 251 | setup_mb_resource_map(); |
| 252 | post_code(0x36); |
| 253 | |
| 254 | /* wait for all the APs core0 started by finalize_node_setup. */ |
| 255 | /* FIXME: A bunch of cores are going to start output to serial at once. |
| 256 | * It would be nice to fixup prink spinlocks for ROM XIP mode. |
| 257 | * I think it could be done by putting the spinlock flag in the cache |
| 258 | * of the BSP located right after sysinfo. |
| 259 | */ |
| 260 | |
| 261 | wait_all_core0_started(); |
| 262 | #if CONFIG_LOGICAL_CPUS==1 |
| 263 | /* Core0 on each node is configured. Now setup any additional cores. */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 264 | printk(BIOS_DEBUG, "start_other_cores()\n"); |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 265 | start_other_cores(); |
| 266 | post_code(0x37); |
| 267 | wait_all_other_cores_started(bsp_apicid); |
| 268 | #endif |
| 269 | |
| 270 | post_code(0x38); |
| 271 | |
Myles Watson | 9b43afd | 2010-04-08 15:09:53 +0000 | [diff] [blame] | 272 | #if SET_FIDVID == 1 |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 273 | msr = rdmsr(0xc0010071); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 274 | printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 275 | |
| 276 | /* FIXME: The sb fid change may survive the warm reset and only |
| 277 | * need to be done once.*/ |
| 278 | |
| 279 | enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); |
| 280 | post_code(0x39); |
| 281 | |
| 282 | if (!warm_reset_detect(0)) { // BSP is node 0 |
| 283 | init_fidvid_bsp(bsp_apicid, sysinfo->nodes); |
| 284 | } else { |
| 285 | init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 |
| 286 | } |
| 287 | |
| 288 | post_code(0x3A); |
| 289 | |
| 290 | /* show final fid and vid */ |
| 291 | msr=rdmsr(0xc0010071); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 292 | printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 293 | #endif |
| 294 | |
Stefan Reinauer | bcb8c97 | 2010-04-25 18:06:32 +0000 | [diff] [blame^] | 295 | init_timer(); // Need to use TMICT to synconize FID/VID |
| 296 | |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 297 | wants_reset = mcp55_early_setup_x(); |
| 298 | |
| 299 | /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ |
| 300 | if (!warm_reset_detect(0)) { |
| 301 | print_info("...WARM RESET...\n\n\n"); |
| 302 | soft_reset(); |
| 303 | die("After soft_reset_x - shouldn't see this message!!!\n"); |
| 304 | } |
| 305 | |
| 306 | if (wants_reset) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 307 | printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n"); |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 308 | |
| 309 | post_code(0x3B); |
| 310 | |
| 311 | /* It's the time to set ctrl in sysinfo now; */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 312 | printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 313 | fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); |
| 314 | |
| 315 | post_code(0x3D); |
| 316 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 317 | //printk(BIOS_DEBUG, "enable_smbus()\n"); |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 318 | // enable_smbus(); /* enable in sio_setup */ |
| 319 | |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 320 | post_code(0x40); |
| 321 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 322 | printk(BIOS_DEBUG, "raminit_amdmct()\n"); |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 323 | raminit_amdmct(sysinfo); |
| 324 | post_code(0x41); |
| 325 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 326 | // printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 327 | post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. |
| 328 | post_code(0x42); // Should never see this post code. |
| 329 | |
| 330 | } |
| 331 | |