commit f0a13ceb639f7a7d5a6e84a2c89f3deab0de757a
author Kyösti Mälkki <kyosti.malkki@gmail.com> Sun Dec 08 07:20:48 2013 +0200
committer Kyösti Mälkki <kyosti.malkki@gmail.com> Mon Dec 09 23:28:43 2013 +0100
tree a049b25d82afe909b08fa46b4c4ade23f829d29c
parent 299c26510202faa3cf7383040f330d502d224fdf

AMD boards: Fix includes for microcode updates

No ROMCC involved, no need to include .c files in romstage.c.

Change-Id: I8a2aaf84276f2931d0a0557ba29e359fa06e2fba
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4501
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

src/mainboard/supermicro/h8qme_fam10/romstage.c

diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index ed3df3f..e5ac277 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -71,11 +71,7 @@
 #include "southbridge/nvidia/mcp55/early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
-#include "cpu/amd/microcode/microcode.c"
-
-#if CONFIG_UPDATE_CPU_MICROCODE
-#include "cpu/amd/model_10xxx/update_microcode.c"
-#endif
+#include "cpu/amd/microcode.h"
 
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
@@ -197,9 +193,8 @@
  /* Setup sysinfo defaults */
  set_sysinfo_in_ram(0);
 
-#if CONFIG_UPDATE_CPU_MICROCODE
  update_microcode(val);
-#endif
+
  post_code(0x33);
 
  cpuSetAMDMSR();