Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007 AMD |
| 5 | * Written by Yinghai Lu <yinghailu@amd.com> for AMD. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 20 | */ |
| 21 | |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 22 | #define FAM10_SCAN_PCI_BUS 0 |
| 23 | #define FAM10_ALLOCATE_IO_RANGE 1 |
| 24 | |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 25 | #include <stdint.h> |
| 26 | #include <string.h> |
| 27 | #include <device/pci_def.h> |
| 28 | #include <device/pci_ids.h> |
| 29 | #include <arch/io.h> |
| 30 | #include <device/pnp_def.h> |
| 31 | #include <arch/romcc_io.h> |
| 32 | #include <cpu/x86/lapic.h> |
Patrick Georgi | 12584e2 | 2010-05-08 09:14:51 +0000 | [diff] [blame] | 33 | #include <console/console.h> |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 34 | #include <lib.h> |
Uwe Hermann | 26535d6 | 2010-11-20 20:36:40 +0000 | [diff] [blame] | 35 | #include <spd.h> |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 36 | #include <cpu/amd/model_10xxx_rev.h> |
stepan | 836ae29 | 2010-12-08 05:42:47 +0000 | [diff] [blame] | 37 | #include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 38 | #include "northbridge/amd/amdfam10/raminit.h" |
| 39 | #include "northbridge/amd/amdfam10/amdfam10.h" |
Stefan Reinauer | bcb8c97 | 2010-04-25 18:06:32 +0000 | [diff] [blame] | 40 | #include "cpu/amd/model_10xxx/apic_timer.c" |
| 41 | #include "lib/delay.c" |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 42 | #include "cpu/x86/lapic/boot_cpu.c" |
| 43 | #include "northbridge/amd/amdfam10/reset_test.c" |
stepan | 8301d83 | 2010-12-08 07:07:33 +0000 | [diff] [blame] | 44 | #include "superio/winbond/w83627hf/early_serial.c" |
| 45 | #include "superio/winbond/w83627hf/early_init.c" |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 46 | #include "cpu/x86/bist.h" |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 47 | #include "northbridge/amd/amdfam10/debug.c" |
Stefan Reinauer | 5d3dee8 | 2010-04-14 11:40:34 +0000 | [diff] [blame] | 48 | #include "cpu/x86/mtrr/earlymtrr.c" |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 49 | #include "northbridge/amd/amdfam10/setup_resource_map.c" |
stepan | 836ae29 | 2010-12-08 05:42:47 +0000 | [diff] [blame] | 50 | #include "southbridge/nvidia/mcp55/early_ctrl.c" |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 51 | |
| 52 | #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) |
Uwe Hermann | 9b9791c | 2010-12-06 18:17:01 +0000 | [diff] [blame] | 53 | #define DUMMY_DEV PNP_DEV(0x2e, 0) |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 54 | |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 55 | static inline void activate_spd_rom(const struct mem_controller *ctrl) |
| 56 | { |
Knut Kujat | f7f9e92 | 2010-03-13 12:54:58 +0000 | [diff] [blame] | 57 | #define SMBUS_SWITCH1 0x70 |
| 58 | #define SMBUS_SWITCH2 0x72 |
| 59 | smbus_send_byte(SMBUS_SWITCH1, 5 & 0x0f); |
| 60 | smbus_send_byte(SMBUS_SWITCH2, (5 >> 4) & 0x0f); |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 61 | } |
| 62 | |
| 63 | static inline int spd_read_byte(unsigned device, unsigned address) |
| 64 | { |
| 65 | return smbus_read_byte(device, address); |
| 66 | } |
| 67 | |
| 68 | #include "northbridge/amd/amdfam10/amdfam10.h" |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 69 | #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" |
stepan | 8301d83 | 2010-12-08 07:07:33 +0000 | [diff] [blame] | 70 | #include "northbridge/amd/amdfam10/pci.c" |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 71 | #include "resourcemap.c" |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 72 | #include "cpu/amd/quadcore/quadcore.c" |
stepan | 836ae29 | 2010-12-08 05:42:47 +0000 | [diff] [blame] | 73 | #include "southbridge/nvidia/mcp55/early_setup_ss.h" |
| 74 | #include "southbridge/nvidia/mcp55/early_setup_car.c" |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 75 | #include "cpu/amd/car/post_cache_as_ram.c" |
Myles Watson | 075fbe8 | 2010-04-15 05:19:29 +0000 | [diff] [blame] | 76 | #include "cpu/amd/microcode/microcode.c" |
Xavi Drudis Ferran | 4c28a6f | 2011-02-26 23:29:44 +0000 | [diff] [blame] | 77 | |
| 78 | #if CONFIG_UPDATE_CPU_MICROCODE |
Myles Watson | 075fbe8 | 2010-04-15 05:19:29 +0000 | [diff] [blame] | 79 | #include "cpu/amd/model_10xxx/update_microcode.c" |
Xavi Drudis Ferran | 4c28a6f | 2011-02-26 23:29:44 +0000 | [diff] [blame] | 80 | #endif |
| 81 | |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 82 | #include "cpu/amd/model_10xxx/init_cpus.c" |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 83 | #include "northbridge/amd/amdfam10/early_ht.c" |
| 84 | |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 85 | static void sio_setup(void) |
| 86 | { |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 87 | uint32_t dword; |
| 88 | uint8_t byte; |
| 89 | enable_smbus(); |
| 90 | // smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */ |
| 91 | smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */ |
| 92 | |
| 93 | byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 94 | byte |= 0x20; |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 95 | pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 96 | |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 97 | dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); |
| 98 | dword |= (1<<0); |
| 99 | pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 100 | |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 101 | dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); |
| 102 | dword |= (1<<16); |
| 103 | pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 104 | } |
| 105 | |
Uwe Hermann | 26535d6 | 2010-11-20 20:36:40 +0000 | [diff] [blame] | 106 | static const u8 spd_addr[] = { |
| 107 | //first node |
| 108 | RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 109 | #if CONFIG_MAX_PHYSICAL_CPUS > 1 |
| 110 | //second node |
| 111 | RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, |
| 112 | #endif |
| 113 | #if CONFIG_MAX_PHYSICAL_CPUS > 2 |
| 114 | //third node |
| 115 | RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 116 | //forth node |
| 117 | RC03, DIMM4, DIMM6,0 , 0, DIMM5, DIMM7, 0, 0, |
| 118 | #endif |
| 119 | }; |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 120 | |
Knut Kujat | f7f9e92 | 2010-03-13 12:54:58 +0000 | [diff] [blame] | 121 | #define GPIO1_DEV PNP_DEV(0x2e, W83627HF_GAME_MIDI_GPIO1) |
| 122 | #define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2) |
| 123 | #define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3) |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 124 | |
Stefan Reinauer | 523ebd9 | 2010-04-14 18:59:42 +0000 | [diff] [blame] | 125 | static void write_GPIO(void) |
Knut Kujat | f7f9e92 | 2010-03-13 12:54:58 +0000 | [diff] [blame] | 126 | { |
| 127 | pnp_enter_ext_func_mode(GPIO1_DEV); |
| 128 | pnp_set_logical_device(GPIO1_DEV); |
| 129 | pnp_write_config(GPIO1_DEV, 0x30, 0x01); |
| 130 | pnp_write_config(GPIO1_DEV, 0x60, 0x00); |
| 131 | pnp_write_config(GPIO1_DEV, 0x61, 0x00); |
| 132 | pnp_write_config(GPIO1_DEV, 0x62, 0x00); |
| 133 | pnp_write_config(GPIO1_DEV, 0x63, 0x00); |
| 134 | pnp_write_config(GPIO1_DEV, 0x70, 0x00); |
| 135 | pnp_write_config(GPIO1_DEV, 0xf0, 0xff); |
| 136 | pnp_write_config(GPIO1_DEV, 0xf1, 0xff); |
| 137 | pnp_write_config(GPIO1_DEV, 0xf2, 0x00); |
| 138 | pnp_exit_ext_func_mode(GPIO1_DEV); |
| 139 | |
| 140 | pnp_enter_ext_func_mode(GPIO2_DEV); |
| 141 | pnp_set_logical_device(GPIO2_DEV); |
| 142 | pnp_write_config(GPIO2_DEV, 0x30, 0x01); |
| 143 | pnp_write_config(GPIO2_DEV, 0xf0, 0xef); |
| 144 | pnp_write_config(GPIO2_DEV, 0xf1, 0xff); |
| 145 | pnp_write_config(GPIO2_DEV, 0xf2, 0x00); |
| 146 | pnp_write_config(GPIO2_DEV, 0xf3, 0x00); |
| 147 | pnp_write_config(GPIO2_DEV, 0xf5, 0x48); |
| 148 | pnp_write_config(GPIO2_DEV, 0xf6, 0x00); |
| 149 | pnp_write_config(GPIO2_DEV, 0xf7, 0xc0); |
| 150 | pnp_exit_ext_func_mode(GPIO2_DEV); |
| 151 | |
| 152 | pnp_enter_ext_func_mode(GPIO3_DEV); |
| 153 | pnp_set_logical_device(GPIO3_DEV); |
| 154 | pnp_write_config(GPIO3_DEV, 0x30, 0x00); |
| 155 | pnp_write_config(GPIO3_DEV, 0xf0, 0xff); |
| 156 | pnp_write_config(GPIO3_DEV, 0xf1, 0xff); |
| 157 | pnp_write_config(GPIO3_DEV, 0xf2, 0xff); |
| 158 | pnp_write_config(GPIO3_DEV, 0xf3, 0x40); |
| 159 | pnp_exit_ext_func_mode(GPIO3_DEV); |
| 160 | } |
| 161 | |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 162 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 163 | { |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 164 | struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE |
| 165 | + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); |
| 166 | u32 bsp_apicid = 0, val, wants_reset; |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 167 | msr_t msr; |
| 168 | |
Patrick Georgi | 2bd9100 | 2010-03-18 16:46:50 +0000 | [diff] [blame] | 169 | if (!cpu_init_detectedx && boot_cpu()) { |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 170 | /* Nothing special needs to be done to find bus 0 */ |
| 171 | /* Allow the HT devices to be found */ |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 172 | set_bsp_node_CHtExtNodeCfgEn(); |
| 173 | enumerate_ht_chain(); |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 174 | sio_setup(); |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 175 | } |
| 176 | |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 177 | post_code(0x30); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 178 | |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 179 | if (bist == 0) |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 180 | bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 181 | |
| 182 | post_code(0x32); |
| 183 | |
Uwe Hermann | 9b9791c | 2010-12-06 18:17:01 +0000 | [diff] [blame] | 184 | w83627hf_set_clksel_48(DUMMY_DEV); |
| 185 | w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 186 | |
Knut Kujat | f7f9e92 | 2010-03-13 12:54:58 +0000 | [diff] [blame] | 187 | console_init(); |
| 188 | write_GPIO(); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 189 | printk(BIOS_DEBUG, "\n"); |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 190 | |
| 191 | /* Halt if there was a built in self test failure */ |
| 192 | report_bist_failure(bist); |
| 193 | |
| 194 | val = cpuid_eax(1); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 195 | printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); |
Myles Watson | 08e0fb8 | 2010-03-22 16:33:25 +0000 | [diff] [blame] | 196 | printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 197 | printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid); |
Myles Watson | 08e0fb8 | 2010-03-22 16:33:25 +0000 | [diff] [blame] | 198 | printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 199 | |
| 200 | /* Setup sysinfo defaults */ |
| 201 | set_sysinfo_in_ram(0); |
| 202 | |
Xavi Drudis Ferran | 4c28a6f | 2011-02-26 23:29:44 +0000 | [diff] [blame] | 203 | #if CONFIG_UPDATE_CPU_MICROCODE |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 204 | update_microcode(val); |
Xavi Drudis Ferran | 4c28a6f | 2011-02-26 23:29:44 +0000 | [diff] [blame] | 205 | #endif |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 206 | post_code(0x33); |
| 207 | |
| 208 | cpuSetAMDMSR(); |
| 209 | post_code(0x34); |
| 210 | |
| 211 | amd_ht_init(sysinfo); |
| 212 | post_code(0x35); |
| 213 | |
| 214 | /* Setup nodes PCI space and start core 0 AP init. */ |
| 215 | finalize_node_setup(sysinfo); |
| 216 | |
| 217 | /* Setup any mainboard PCI settings etc. */ |
| 218 | setup_mb_resource_map(); |
| 219 | post_code(0x36); |
| 220 | |
| 221 | /* wait for all the APs core0 started by finalize_node_setup. */ |
| 222 | /* FIXME: A bunch of cores are going to start output to serial at once. |
| 223 | * It would be nice to fixup prink spinlocks for ROM XIP mode. |
| 224 | * I think it could be done by putting the spinlock flag in the cache |
| 225 | * of the BSP located right after sysinfo. |
| 226 | */ |
| 227 | |
| 228 | wait_all_core0_started(); |
Patrick Georgi | e166782 | 2012-05-05 15:29:32 +0200 | [diff] [blame^] | 229 | #if CONFIG_LOGICAL_CPUS |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 230 | /* Core0 on each node is configured. Now setup any additional cores. */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 231 | printk(BIOS_DEBUG, "start_other_cores()\n"); |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 232 | start_other_cores(); |
| 233 | post_code(0x37); |
| 234 | wait_all_other_cores_started(bsp_apicid); |
| 235 | #endif |
| 236 | |
| 237 | post_code(0x38); |
| 238 | |
Patrick Georgi | 76e8152 | 2010-11-16 21:25:29 +0000 | [diff] [blame] | 239 | #if CONFIG_SET_FIDVID |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 240 | msr = rdmsr(0xc0010071); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 241 | printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 242 | |
| 243 | /* FIXME: The sb fid change may survive the warm reset and only |
| 244 | * need to be done once.*/ |
| 245 | |
| 246 | enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); |
| 247 | post_code(0x39); |
| 248 | |
| 249 | if (!warm_reset_detect(0)) { // BSP is node 0 |
| 250 | init_fidvid_bsp(bsp_apicid, sysinfo->nodes); |
| 251 | } else { |
| 252 | init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 |
| 253 | } |
| 254 | |
| 255 | post_code(0x3A); |
| 256 | |
| 257 | /* show final fid and vid */ |
| 258 | msr=rdmsr(0xc0010071); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 259 | printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 260 | #endif |
| 261 | |
Stefan Reinauer | bcb8c97 | 2010-04-25 18:06:32 +0000 | [diff] [blame] | 262 | init_timer(); // Need to use TMICT to synconize FID/VID |
| 263 | |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 264 | wants_reset = mcp55_early_setup_x(); |
| 265 | |
| 266 | /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ |
| 267 | if (!warm_reset_detect(0)) { |
| 268 | print_info("...WARM RESET...\n\n\n"); |
| 269 | soft_reset(); |
| 270 | die("After soft_reset_x - shouldn't see this message!!!\n"); |
| 271 | } |
| 272 | |
| 273 | if (wants_reset) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 274 | printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n"); |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 275 | |
| 276 | post_code(0x3B); |
| 277 | |
| 278 | /* It's the time to set ctrl in sysinfo now; */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 279 | printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 280 | fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); |
| 281 | |
| 282 | post_code(0x3D); |
| 283 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 284 | //printk(BIOS_DEBUG, "enable_smbus()\n"); |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 285 | // enable_smbus(); /* enable in sio_setup */ |
| 286 | |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 287 | post_code(0x40); |
| 288 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 289 | printk(BIOS_DEBUG, "raminit_amdmct()\n"); |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 290 | raminit_amdmct(sysinfo); |
| 291 | post_code(0x41); |
| 292 | |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 293 | post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. |
| 294 | post_code(0x42); // Should never see this post code. |
Knut Kujat | 081c897 | 2010-02-03 16:04:40 +0000 | [diff] [blame] | 295 | } |
Scott Duplichan | 314dd0b | 2011-03-08 23:01:46 +0000 | [diff] [blame] | 296 | |
| 297 | /** |
| 298 | * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) |
| 299 | * Description: |
| 300 | * This routine is called every time a non-coherent chain is processed. |
| 301 | * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a |
| 302 | * swap list. The first part of the list controls the BUID assignment and the |
| 303 | * second part of the list provides the device to device linking. Device orientation |
| 304 | * can be detected automatically, or explicitly. See documentation for more details. |
| 305 | * |
| 306 | * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially |
| 307 | * based on each device's unit count. |
| 308 | * |
| 309 | * Parameters: |
| 310 | * @param[in] u8 node = The node on which this chain is located |
| 311 | * @param[in] u8 link = The link on the host for this chain |
| 312 | * @param[out] u8** list = supply a pointer to a list |
| 313 | * @param[out] BOOL result = true to use a manual list |
| 314 | * false to initialize the link automatically |
| 315 | */ |
| 316 | BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) |
| 317 | { |
| 318 | static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; |
| 319 | /* If the BUID was adjusted in early_ht we need to do the manual override */ |
| 320 | if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { |
| 321 | printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n"); |
| 322 | if ((node == 0) && (link == 0)) { /* BSP SB link */ |
| 323 | *List = swaplist; |
| 324 | return 1; |
| 325 | } |
| 326 | } |
| 327 | |
| 328 | return 0; |
| 329 | } |