Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 2 | |
| 3 | #ifndef SOUTHBRIDGE_INTEL_BD82X6X_PCH_H |
| 4 | #define SOUTHBRIDGE_INTEL_BD82X6X_PCH_H |
| 5 | |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 6 | #include <acpi/acpi.h> |
Aaron Durbin | 78c6843 | 2016-07-13 23:23:54 -0500 | [diff] [blame] | 7 | |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 8 | /* PCH types */ |
| 9 | #define PCH_TYPE_CPT 0x1c /* CougarPoint */ |
| 10 | #define PCH_TYPE_PPT 0x1e /* IvyBridge */ |
| 11 | #define PCH_TYPE_MOBILE5 0x3b |
| 12 | |
| 13 | /* PCH stepping values for LPC device */ |
| 14 | #define PCH_STEP_A0 0 |
| 15 | #define PCH_STEP_A1 1 |
| 16 | #define PCH_STEP_B0 2 |
| 17 | #define PCH_STEP_B1 3 |
| 18 | #define PCH_STEP_B2 4 |
| 19 | #define PCH_STEP_B3 5 |
| 20 | |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 21 | #define SMBUS_SLAVE_ADDR 0x24 |
| 22 | /* TODO Make sure these don't get changed by stage2 */ |
| 23 | #define DEFAULT_GPIOBASE 0x0480 |
| 24 | #define DEFAULT_PMBASE 0x0500 |
Angel Pons | e2531ff | 2022-02-14 13:04:34 +0100 | [diff] [blame^] | 25 | #define DEFAULT_HECIBAR ((u8 *)0xfed17000) |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 26 | |
Arthur Heymans | 1f2ae91 | 2018-06-12 23:48:30 +0200 | [diff] [blame] | 27 | #include <southbridge/intel/common/rcba.h> |
Arthur Heymans | 58a8953 | 2018-06-12 22:58:19 +0200 | [diff] [blame] | 28 | |
| 29 | #ifndef __ACPI__ |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 30 | |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 31 | void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 32 | void enable_usb_bar(void); |
Kyösti Mälkki | 12b121c | 2019-08-18 16:33:39 +0300 | [diff] [blame] | 33 | |
Angel Pons | e4c0555 | 2020-07-22 00:40:21 +0200 | [diff] [blame] | 34 | void ibexpeak_setup_bars(void); |
Arthur Heymans | 3b452e0 | 2019-10-03 09:16:10 +0200 | [diff] [blame] | 35 | void early_pch_init(void); |
| 36 | |
Vladimir Serbinenko | 1cd937b | 2014-01-09 23:41:48 +0100 | [diff] [blame] | 37 | void early_thermal_init(void); |
Vladimir Serbinenko | 33b535f | 2014-10-19 10:13:14 +0200 | [diff] [blame] | 38 | void southbridge_configure_default_intmap(void); |
Arthur Heymans | f503b60 | 2019-09-16 21:00:22 +0200 | [diff] [blame] | 39 | void pch_setup_cir(int chipset_type); |
Kyösti Mälkki | 12b121c | 2019-08-18 16:33:39 +0300 | [diff] [blame] | 40 | |
Arthur Heymans | 39f8a1a | 2019-10-02 17:13:02 +0200 | [diff] [blame] | 41 | enum current_lookup_idx { |
| 42 | IF1_F57 = 0, |
| 43 | IF1_F5F, |
| 44 | IF1_753, |
| 45 | IF1_75F, |
| 46 | IF1_14B, |
| 47 | IF1_74B, |
| 48 | IF1_557, |
| 49 | IF1_757, |
| 50 | IF1_55F, |
| 51 | IF1_54B, |
| 52 | }; |
| 53 | |
| 54 | struct southbridge_usb_port { |
| 55 | int enabled; |
| 56 | enum current_lookup_idx current; |
| 57 | int oc_pin; |
| 58 | }; |
Arthur Heymans | cea4fd9 | 2019-10-03 08:54:35 +0200 | [diff] [blame] | 59 | |
Arthur Heymans | 39f8a1a | 2019-10-02 17:13:02 +0200 | [diff] [blame] | 60 | void early_usb_init(const struct southbridge_usb_port *portmap); |
| 61 | |
Arthur Heymans | cea4fd9 | 2019-10-03 08:54:35 +0200 | [diff] [blame] | 62 | extern const struct southbridge_usb_port mainboard_usb_ports[14]; |
Kyösti Mälkki | 12b121c | 2019-08-18 16:33:39 +0300 | [diff] [blame] | 63 | #include <device/device.h> |
| 64 | void pch_enable(struct device *dev); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 65 | |
| 66 | #define MAINBOARD_POWER_OFF 0 |
| 67 | #define MAINBOARD_POWER_ON 1 |
| 68 | #define MAINBOARD_POWER_KEEP 2 |
| 69 | |
Arthur Heymans | 39f8a1a | 2019-10-02 17:13:02 +0200 | [diff] [blame] | 70 | /* PM I/O Space */ |
| 71 | #define UPRWC 0x3c |
| 72 | #define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */ |
| 73 | |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 74 | /* PCI Configuration Space (D30:F0): PCI2PCI */ |
| 75 | #define PSTS 0x06 |
| 76 | #define SMLT 0x1b |
| 77 | #define SECSTS 0x1e |
| 78 | #define INTR 0x3c |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 79 | |
| 80 | #define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0) |
| 81 | #define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0) |
| 82 | #define PCH_XHCI_DEV PCI_DEV(0, 0x14, 0) |
| 83 | #define PCH_ME_DEV PCI_DEV(0, 0x16, 0) |
| 84 | #define PCH_PCIE_DEV_SLOT 28 |
| 85 | |
| 86 | /* PCI Configuration Space (D31:F0): LPC */ |
| 87 | #define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0) |
| 88 | #define SERIRQ_CNTL 0x64 |
| 89 | |
| 90 | #define GEN_PMCON_1 0xa0 |
| 91 | #define GEN_PMCON_2 0xa2 |
| 92 | #define GEN_PMCON_3 0xa4 |
| 93 | #define ETR3 0xac |
| 94 | #define ETR3_CWORWRE (1 << 18) |
| 95 | #define ETR3_CF9GR (1 << 20) |
| 96 | |
Arthur Heymans | f503b60 | 2019-09-16 21:00:22 +0200 | [diff] [blame] | 97 | #define CIR4 0xa9 |
| 98 | #define PMIR 0xac |
| 99 | |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 100 | /* GEN_PMCON_3 bits */ |
| 101 | #define RTC_BATTERY_DEAD (1 << 2) |
| 102 | #define RTC_POWER_FAILED (1 << 1) |
| 103 | #define SLEEP_AFTER_POWER_FAIL (1 << 0) |
| 104 | |
| 105 | #define PMBASE 0x40 |
| 106 | #define ACPI_CNTL 0x44 |
| 107 | #define ACPI_EN (1 << 7) |
| 108 | #define BIOS_CNTL 0xDC |
| 109 | #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ |
| 110 | #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ |
Kyösti Mälkki | b85a87b | 2014-12-29 11:32:27 +0200 | [diff] [blame] | 111 | |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 112 | #define GPIO_ROUT 0xb8 |
Kyösti Mälkki | b85a87b | 2014-12-29 11:32:27 +0200 | [diff] [blame] | 113 | #define GPI_DISABLE 0x00 |
| 114 | #define GPI_IS_SMI 0x01 |
| 115 | #define GPI_IS_SCI 0x02 |
| 116 | #define GPI_IS_NMI 0x03 |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 117 | |
| 118 | #define PIRQA_ROUT 0x60 |
| 119 | #define PIRQB_ROUT 0x61 |
| 120 | #define PIRQC_ROUT 0x62 |
| 121 | #define PIRQD_ROUT 0x63 |
| 122 | #define PIRQE_ROUT 0x68 |
| 123 | #define PIRQF_ROUT 0x69 |
| 124 | #define PIRQG_ROUT 0x6A |
| 125 | #define PIRQH_ROUT 0x6B |
| 126 | |
| 127 | #define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ |
| 128 | #define LPC_EN 0x82 /* LPC IF Enables Register */ |
| 129 | #define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ |
| 130 | #define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ |
| 131 | #define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ |
| 132 | #define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ |
| 133 | #define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ |
| 134 | #define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ |
| 135 | #define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ |
| 136 | #define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ |
| 137 | #define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ |
| 138 | #define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[3:2] */ |
| 139 | #define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ |
| 140 | #define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ |
| 141 | #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ |
| 142 | #define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ |
| 143 | |
Angel Pons | 0b3512b | 2020-08-10 13:02:20 +0200 | [diff] [blame] | 144 | /* PCI Configuration Space (D31:F2): SATA */ |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 145 | #define PCH_SATA_DEV PCI_DEV(0, 0x1f, 2) |
| 146 | #define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5) |
| 147 | #define INTR_LN 0x3c |
| 148 | #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ |
| 149 | #define IDE_DECODE_ENABLE (1 << 15) |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 150 | #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */ |
| 151 | |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 152 | #define SATA_SIRI 0xa0 /* SATA Indexed Register Index */ |
| 153 | #define SATA_SIRD 0xa4 /* SATA Indexed Register Data */ |
| 154 | #define SATA_SP 0xd0 /* Scratchpad */ |
| 155 | |
| 156 | /* SATA IOBP Registers */ |
| 157 | #define SATA_IOBP_SP0G3IR 0xea000151 |
| 158 | #define SATA_IOBP_SP1G3IR 0xea000051 |
| 159 | |
| 160 | /* PCI Configuration Space (D31:F3): SMBus */ |
| 161 | #define PCH_SMBUS_DEV PCI_DEV(0, 0x1f, 3) |
| 162 | #define SMB_BASE 0x20 |
| 163 | #define HOSTC 0x40 |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 164 | |
| 165 | /* HOSTC bits */ |
| 166 | #define I2C_EN (1 << 2) |
| 167 | #define SMB_SMI_EN (1 << 1) |
| 168 | #define HST_EN (1 << 0) |
| 169 | |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 170 | /* Southbridge IO BARs */ |
| 171 | |
| 172 | #define GPIOBASE 0x48 |
| 173 | |
| 174 | #define PMBASE 0x40 |
| 175 | |
Arthur Heymans | 58a8953 | 2018-06-12 22:58:19 +0200 | [diff] [blame] | 176 | #define VCH 0x0000 /* 32bit */ |
| 177 | #define VCAP1 0x0004 /* 32bit */ |
| 178 | #define VCAP2 0x0008 /* 32bit */ |
| 179 | #define PVC 0x000c /* 16bit */ |
| 180 | #define PVS 0x000e /* 16bit */ |
| 181 | |
| 182 | #define V0CAP 0x0010 /* 32bit */ |
| 183 | #define V0CTL 0x0014 /* 32bit */ |
| 184 | #define V0STS 0x001a /* 16bit */ |
| 185 | |
| 186 | #define V1CAP 0x001c /* 32bit */ |
| 187 | #define V1CTL 0x0020 /* 32bit */ |
| 188 | #define V1STS 0x0026 /* 16bit */ |
| 189 | |
| 190 | #define RCTCL 0x0100 /* 32bit */ |
| 191 | #define ESD 0x0104 /* 32bit */ |
| 192 | #define ULD 0x0110 /* 32bit */ |
| 193 | #define ULBA 0x0118 /* 64bit */ |
| 194 | |
| 195 | #define RP1D 0x0120 /* 32bit */ |
| 196 | #define RP1BA 0x0128 /* 64bit */ |
| 197 | #define RP2D 0x0130 /* 32bit */ |
| 198 | #define RP2BA 0x0138 /* 64bit */ |
| 199 | #define RP3D 0x0140 /* 32bit */ |
| 200 | #define RP3BA 0x0148 /* 64bit */ |
| 201 | #define RP4D 0x0150 /* 32bit */ |
| 202 | #define RP4BA 0x0158 /* 64bit */ |
| 203 | #define HDD 0x0160 /* 32bit */ |
| 204 | #define HDBA 0x0168 /* 64bit */ |
| 205 | #define RP5D 0x0170 /* 32bit */ |
| 206 | #define RP5BA 0x0178 /* 64bit */ |
| 207 | #define RP6D 0x0180 /* 32bit */ |
| 208 | #define RP6BA 0x0188 /* 64bit */ |
| 209 | |
| 210 | #define RPC 0x0400 /* 32bit */ |
| 211 | #define RPFN 0x0404 /* 32bit */ |
| 212 | |
| 213 | /* Root Port configuratinon space hide */ |
| 214 | #define RPFN_HIDE(port) (1 << (((port) * 4) + 3)) |
| 215 | /* Get the function number assigned to a Root Port */ |
| 216 | #define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7) |
| 217 | /* Set the function number for a Root Port */ |
| 218 | #define RPFN_FNSET(port,func) (((func) & 7) << ((port) * 4)) |
| 219 | /* Root Port function number mask */ |
| 220 | #define RPFN_FNMASK(port) (7 << ((port) * 4)) |
| 221 | |
| 222 | #define TRSR 0x1e00 /* 8bit */ |
| 223 | #define TRCR 0x1e10 /* 64bit */ |
| 224 | #define TWDR 0x1e18 /* 64bit */ |
| 225 | |
| 226 | #define IOTR0 0x1e80 /* 64bit */ |
| 227 | #define IOTR1 0x1e88 /* 64bit */ |
| 228 | #define IOTR2 0x1e90 /* 64bit */ |
| 229 | #define IOTR3 0x1e98 /* 64bit */ |
| 230 | |
| 231 | #define TCTL 0x3000 /* 8bit */ |
| 232 | |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 233 | #define NOINT 0 |
| 234 | #define INTA 1 |
| 235 | #define INTB 2 |
| 236 | #define INTC 3 |
| 237 | #define INTD 4 |
| 238 | |
| 239 | #define DIR_IDR 12 /* Interrupt D Pin Offset */ |
| 240 | #define DIR_ICR 8 /* Interrupt C Pin Offset */ |
| 241 | #define DIR_IBR 4 /* Interrupt B Pin Offset */ |
| 242 | #define DIR_IAR 0 /* Interrupt A Pin Offset */ |
| 243 | |
| 244 | #define PIRQA 0 |
| 245 | #define PIRQB 1 |
| 246 | #define PIRQC 2 |
| 247 | #define PIRQD 3 |
| 248 | #define PIRQE 4 |
| 249 | #define PIRQF 5 |
| 250 | #define PIRQG 6 |
| 251 | #define PIRQH 7 |
| 252 | |
| 253 | /* IO Buffer Programming */ |
| 254 | #define IOBPIRI 0x2330 |
| 255 | #define IOBPD 0x2334 |
| 256 | #define IOBPS 0x2338 |
| 257 | #define IOBPS_RW_BX ((1 << 9)|(1 << 10)) |
| 258 | #define IOBPS_WRITE_AX ((1 << 9)|(1 << 10)) |
| 259 | #define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10)) |
| 260 | |
Arthur Heymans | 58a8953 | 2018-06-12 22:58:19 +0200 | [diff] [blame] | 261 | #define D31IP 0x3100 /* 32bit */ |
| 262 | #define D31IP_TTIP 24 /* Thermal Throttle Pin */ |
| 263 | #define D31IP_SIP2 20 /* SATA Pin 2 */ |
| 264 | #define D31IP_UNKIP 16 |
| 265 | #define D31IP_SMIP 12 /* SMBUS Pin */ |
| 266 | #define D31IP_SIP 8 /* SATA Pin */ |
| 267 | #define D30IP 0x3104 /* 32bit */ |
| 268 | #define D30IP_PIP 0 /* PCI Bridge Pin */ |
| 269 | #define D29IP 0x3108 /* 32bit */ |
| 270 | #define D29IP_E1P 0 /* EHCI #1 Pin */ |
| 271 | #define D28IP 0x310c /* 32bit */ |
| 272 | #define D28IP_P8IP 28 /* PCI Express Port 8 */ |
| 273 | #define D28IP_P7IP 24 /* PCI Express Port 7 */ |
| 274 | #define D28IP_P6IP 20 /* PCI Express Port 6 */ |
| 275 | #define D28IP_P5IP 16 /* PCI Express Port 5 */ |
| 276 | #define D28IP_P4IP 12 /* PCI Express Port 4 */ |
| 277 | #define D28IP_P3IP 8 /* PCI Express Port 3 */ |
| 278 | #define D28IP_P2IP 4 /* PCI Express Port 2 */ |
| 279 | #define D28IP_P1IP 0 /* PCI Express Port 1 */ |
| 280 | #define D27IP 0x3110 /* 32bit */ |
| 281 | #define D27IP_ZIP 0 /* HD Audio Pin */ |
| 282 | #define D26IP 0x3114 /* 32bit */ |
| 283 | #define D26IP_E2P 0 /* EHCI #2 Pin */ |
| 284 | #define D25IP 0x3118 /* 32bit */ |
| 285 | #define D25IP_LIP 0 /* GbE LAN Pin */ |
| 286 | #define D22IP 0x3124 /* 32bit */ |
| 287 | #define D22IP_KTIP 12 /* KT Pin */ |
| 288 | #define D22IP_IDERIP 8 /* IDE-R Pin */ |
| 289 | #define D22IP_MEI2IP 4 /* MEI #2 Pin */ |
| 290 | #define D22IP_MEI1IP 0 /* MEI #1 Pin */ |
| 291 | #define D20IP 0x3128 /* 32bit */ |
| 292 | #define D20IP_XHCIIP 0 |
| 293 | #define D31IR 0x3140 /* 16bit */ |
| 294 | #define D30IR 0x3142 /* 16bit */ |
| 295 | #define D29IR 0x3144 /* 16bit */ |
| 296 | #define D28IR 0x3146 /* 16bit */ |
| 297 | #define D27IR 0x3148 /* 16bit */ |
| 298 | #define D26IR 0x314c /* 16bit */ |
| 299 | #define D25IR 0x3150 /* 16bit */ |
| 300 | #define D22IR 0x315c /* 16bit */ |
| 301 | #define D20IR 0x3160 /* 16bit */ |
| 302 | #define OIC 0x31fe /* 16bit */ |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 303 | #define SOFT_RESET_CTRL 0x38f4 |
| 304 | #define SOFT_RESET_DATA 0x38f8 |
| 305 | |
Angel Pons | 42b4e4e | 2019-09-18 10:58:53 +0200 | [diff] [blame] | 306 | #define PRSTS 0x3310 |
Arthur Heymans | f503b60 | 2019-09-16 21:00:22 +0200 | [diff] [blame] | 307 | #define CIR6 0x2024 |
| 308 | #define CIR7 0x3314 |
| 309 | #define CIR8 0x3324 |
| 310 | #define CIR9 0x3330 |
| 311 | #define CIR10 0x3340 |
| 312 | #define CIR13 0x3350 |
| 313 | #define CIR14 0x3368 |
| 314 | #define CIR15 0x3378 |
| 315 | #define CIR16 0x3388 |
| 316 | #define CIR17 0x33a0 |
| 317 | #define CIR18 0x33a8 |
| 318 | #define CIR19 0x33c0 |
| 319 | #define CIR20 0x33cc |
| 320 | #define CIR21 0x33d0 |
| 321 | #define CIR22 0x33d4 |
Angel Pons | 42b4e4e | 2019-09-18 10:58:53 +0200 | [diff] [blame] | 322 | |
Arthur Heymans | 58a8953 | 2018-06-12 22:58:19 +0200 | [diff] [blame] | 323 | #define DIR_ROUTE(x,a,b,c,d) \ |
| 324 | RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ |
| 325 | ((b) << DIR_IBR) | ((a) << DIR_IAR)) |
| 326 | |
| 327 | #define RC 0x3400 /* 32bit */ |
| 328 | #define HPTC 0x3404 /* 32bit */ |
| 329 | #define GCS 0x3410 /* 32bit */ |
| 330 | #define BUC 0x3414 /* 32bit */ |
| 331 | #define PCH_DISABLE_GBE (1 << 5) |
| 332 | #define FD 0x3418 /* 32bit */ |
| 333 | #define DISPBDF 0x3424 /* 16bit */ |
| 334 | #define FD2 0x3428 /* 32bit */ |
| 335 | #define CG 0x341c /* 32bit */ |
| 336 | |
| 337 | /* Function Disable 1 RCBA 0x3418 */ |
| 338 | #define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26)) |
| 339 | #define PCH_DISABLE_P2P (1 << 1) |
| 340 | #define PCH_DISABLE_SATA1 (1 << 2) |
| 341 | #define PCH_DISABLE_SMBUS (1 << 3) |
| 342 | #define PCH_DISABLE_HD_AUDIO (1 << 4) |
| 343 | #define PCH_DISABLE_EHCI2 (1 << 13) |
| 344 | #define PCH_DISABLE_LPC (1 << 14) |
| 345 | #define PCH_DISABLE_EHCI1 (1 << 15) |
| 346 | #define PCH_DISABLE_PCIE(x) (1 << (16 + x)) |
| 347 | #define PCH_DISABLE_THERMAL (1 << 24) |
| 348 | #define PCH_DISABLE_SATA2 (1 << 25) |
| 349 | #define PCH_DISABLE_XHCI (1 << 27) |
| 350 | |
| 351 | /* Function Disable 2 RCBA 0x3428 */ |
| 352 | #define PCH_DISABLE_KT (1 << 4) |
| 353 | #define PCH_DISABLE_IDER (1 << 3) |
| 354 | #define PCH_DISABLE_MEI2 (1 << 2) |
| 355 | #define PCH_DISABLE_MEI1 (1 << 1) |
| 356 | #define PCH_ENABLE_DBDF (1 << 0) |
| 357 | |
Arthur Heymans | 39f8a1a | 2019-10-02 17:13:02 +0200 | [diff] [blame] | 358 | /* USB Initialization Registers[13:0] */ |
| 359 | #define USBIR0 0x3500 /* 32bit */ |
| 360 | #define USBIR1 0x3504 /* 32bit */ |
| 361 | #define USBIR2 0x3508 /* 32bit */ |
| 362 | #define USBIR3 0x350c /* 32bit */ |
| 363 | #define USBIR4 0x3510 /* 32bit */ |
| 364 | #define USBIR5 0x3514 /* 32bit */ |
| 365 | #define USBIR6 0x3518 /* 32bit */ |
| 366 | #define USBIR7 0x351c /* 32bit */ |
| 367 | #define USBIR8 0x3520 /* 32bit */ |
| 368 | #define USBIR9 0x3524 /* 32bit */ |
| 369 | #define USBIR10 0x3528 /* 32bit */ |
| 370 | #define USBIR11 0x352c /* 32bit */ |
| 371 | #define USBIR12 0x3530 /* 32bit */ |
| 372 | #define USBIR13 0x3534 /* 32bit */ |
| 373 | |
| 374 | #define USBIRC 0x3564 /* 32bit */ |
| 375 | #define USBIRA 0x3570 /* 32bit */ |
| 376 | #define USBIRB 0x357c /* 32bit */ |
| 377 | |
| 378 | /* Miscellaneous Control Register */ |
| 379 | #define MISCCTL 0x3590 /* 32bit */ |
| 380 | /* USB Port Disable Override */ |
| 381 | #define USBPDO 0x359c /* 32bit */ |
| 382 | /* USB Overcurrent MAP Register */ |
| 383 | #define USBOCM1 0x35a0 /* 32bit */ |
| 384 | #define USBOCM2 0x35a4 /* 32bit */ |
| 385 | /* Rate Matching Hub Wake Control Register */ |
| 386 | #define RMHWKCTL 0x35b0 /* 32bit */ |
| 387 | |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 388 | /* ICH7 PMBASE */ |
| 389 | #define PM1_STS 0x00 |
| 390 | #define WAK_STS (1 << 15) |
| 391 | #define PCIEXPWAK_STS (1 << 14) |
| 392 | #define PRBTNOR_STS (1 << 11) |
| 393 | #define RTC_STS (1 << 10) |
| 394 | #define PWRBTN_STS (1 << 8) |
| 395 | #define GBL_STS (1 << 5) |
| 396 | #define BM_STS (1 << 4) |
| 397 | #define TMROF_STS (1 << 0) |
| 398 | #define PM1_EN 0x02 |
| 399 | #define PCIEXPWAK_DIS (1 << 14) |
| 400 | #define RTC_EN (1 << 10) |
| 401 | #define PWRBTN_EN (1 << 8) |
| 402 | #define GBL_EN (1 << 5) |
| 403 | #define TMROF_EN (1 << 0) |
| 404 | #define PM1_CNT 0x04 |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 405 | #define GBL_RLS (1 << 2) |
| 406 | #define BM_RLD (1 << 1) |
| 407 | #define SCI_EN (1 << 0) |
| 408 | #define PM1_TMR 0x08 |
| 409 | #define PROC_CNT 0x10 |
| 410 | #define LV2 0x14 |
| 411 | #define LV3 0x15 |
| 412 | #define LV4 0x16 |
| 413 | #define PM2_CNT 0x50 // mobile only |
| 414 | #define GPE0_STS 0x20 |
| 415 | #define PME_B0_STS (1 << 13) |
| 416 | #define PME_STS (1 << 11) |
| 417 | #define BATLOW_STS (1 << 10) |
| 418 | #define PCI_EXP_STS (1 << 9) |
| 419 | #define RI_STS (1 << 8) |
| 420 | #define SMB_WAK_STS (1 << 7) |
| 421 | #define TCOSCI_STS (1 << 6) |
| 422 | #define SWGPE_STS (1 << 2) |
| 423 | #define HOT_PLUG_STS (1 << 1) |
| 424 | #define GPE0_EN 0x28 |
| 425 | #define PME_B0_EN (1 << 13) |
| 426 | #define PME_EN (1 << 11) |
| 427 | #define TCOSCI_EN (1 << 6) |
| 428 | #define SMI_EN 0x30 |
| 429 | #define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic |
| 430 | #define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic |
| 431 | #define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS |
| 432 | #define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) |
| 433 | #define MCSMI_EN (1 << 11) // Trap microcontroller range access |
| 434 | #define BIOS_RLS (1 << 7) // asserts SCI on bit set |
| 435 | #define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set |
| 436 | #define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# |
| 437 | #define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# |
| 438 | #define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic |
| 439 | #define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit |
| 440 | #define EOS (1 << 1) // End of SMI (deassert SMI#) |
| 441 | #define GBL_SMI_EN (1 << 0) // SMI# generation at all? |
| 442 | #define SMI_STS 0x34 |
| 443 | #define ALT_GP_SMI_EN 0x38 |
| 444 | #define ALT_GP_SMI_STS 0x3a |
| 445 | #define GPE_CNTL 0x42 |
| 446 | #define DEVACT_STS 0x44 |
| 447 | #define SS_CNT 0x50 |
| 448 | #define C3_RES 0x54 |
| 449 | #define TCO1_STS 0x64 |
| 450 | #define DMISCI_STS (1 << 9) |
| 451 | #define TCO2_STS 0x66 |
| 452 | |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 453 | #define SPIBAR_HSFS 0x3804 /* SPI hardware sequence status */ |
| 454 | #define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ |
| 455 | #define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */ |
| 456 | #define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */ |
| 457 | #define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */ |
| 458 | #define SPIBAR_HSFC 0x3806 /* SPI hardware sequence control */ |
| 459 | #define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8) |
| 460 | #define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */ |
| 461 | #define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */ |
| 462 | #define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */ |
| 463 | #define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */ |
| 464 | #define SPIBAR_FADDR 0x3808 /* SPI flash address */ |
| 465 | #define SPIBAR_FDATA(n) (0x3810 + (4 * n)) /* SPI flash data */ |
| 466 | |
| 467 | #endif /* __ACPI__ */ |
| 468 | #endif /* SOUTHBRIDGE_INTEL_BD82X6X_PCH_H */ |