sb/intel/ibexpeak: Add CIR initialization
This properly sets up the chipset initialization registers, instead of
replaying an RCBA dump.
The information is taken from the EDS and from the thinkpad x201
vendor BIOS disassembly and from an HP UEFI.
TESTED on Thinkpad X201. Seems stable at booting, rebooting and resume
from S3.
Change-Id: I21c2beaf70da27dbe6a56e2612df2c257c05fc62
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h
index f7b2929..f0e469a 100644
--- a/src/southbridge/intel/ibexpeak/pch.h
+++ b/src/southbridge/intel/ibexpeak/pch.h
@@ -67,6 +67,7 @@
void early_thermal_init(void);
void southbridge_configure_default_intmap(void);
+void pch_setup_cir(int chipset_type);
#ifndef __ROMCC__
#include <device/device.h>
@@ -100,6 +101,9 @@
#define ETR3_CWORWRE (1 << 18)
#define ETR3_CF9GR (1 << 20)
+#define CIR4 0xa9
+#define PMIR 0xac
+
/* GEN_PMCON_3 bits */
#define RTC_BATTERY_DEAD (1 << 2)
#define RTC_POWER_FAILED (1 << 1)
@@ -349,6 +353,21 @@
#define SOFT_RESET_DATA 0x38f8
#define PRSTS 0x3310
+#define CIR6 0x2024
+#define CIR7 0x3314
+#define CIR8 0x3324
+#define CIR9 0x3330
+#define CIR10 0x3340
+#define CIR13 0x3350
+#define CIR14 0x3368
+#define CIR15 0x3378
+#define CIR16 0x3388
+#define CIR17 0x33a0
+#define CIR18 0x33a8
+#define CIR19 0x33c0
+#define CIR20 0x33cc
+#define CIR21 0x33d0
+#define CIR22 0x33d4
#define DIR_ROUTE(x,a,b,c,d) \
RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \