blob: 857873a682e94695174ae6f29b3dbb5a2330cae6 [file] [log] [blame]
efdesign987c0c64e2011-06-20 19:56:06 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
efdesign987c0c64e2011-06-20 19:56:06 -070014 */
efdesign984b508342011-07-13 17:16:13 -070015
efdesign987c0c64e2011-06-20 19:56:06 -070016/******************************************************************************
17 * AMD Generic Encapsulated Software Architecture
18 *
19 * $Workfile:: cache_as_ram.inc
20 *
21 * Description: cache_as_ram.inc - AGESA Module Entry Point for GCC complier
22 *
23 ******************************************************************************
efdesign984b508342011-07-13 17:16:13 -070024 */
25
efdesign987c0c64e2011-06-20 19:56:06 -070026#include "gcccar.inc"
Patrick Georgi05e740f2012-03-31 12:52:21 +020027#include <cpu/x86/cache.h>
efdesign987c0c64e2011-06-20 19:56:06 -070028
efdesign987c0c64e2011-06-20 19:56:06 -070029.code32
Kyösti Mälkkiba22e152016-11-23 06:47:15 +020030.globl cache_as_ram_setup, cache_as_ram_setup_out
efdesign987c0c64e2011-06-20 19:56:06 -070031
32cache_as_ram_setup:
efdesign984b508342011-07-13 17:16:13 -070033
Kyösti Mälkki1779d532016-11-23 21:29:26 +020034 /* Preserve BIST. */
35 movl %eax, %ebp
36
efdesign987c0c64e2011-06-20 19:56:06 -070037 post_code(0xa0)
efdesign984b508342011-07-13 17:16:13 -070038
39 /* enable SSE2 128bit instructions */
efdesign987c0c64e2011-06-20 19:56:06 -070040 /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */
efdesign984b508342011-07-13 17:16:13 -070041
efdesign987c0c64e2011-06-20 19:56:06 -070042 movl %cr4, %eax
43 orl $(3<<9), %eax
efdesign984b508342011-07-13 17:16:13 -070044 movl %eax, %cr4
45
efdesign987c0c64e2011-06-20 19:56:06 -070046 post_code(0xa1)
efdesign984b508342011-07-13 17:16:13 -070047
Kyösti Mälkki1779d532016-11-23 21:29:26 +020048 /* NOTE: %ebx, %ebp are preserved in AMD_ENABLE_STACK. */
Kyösti Mälkkif6fe2f12016-11-21 11:26:48 +020049 AMD_ENABLE_STACK
50
Kyösti Mälkki26929bd2016-11-23 20:40:53 +020051 /* Align the stack. */
52 and $0xFFFFFFF0, %esp
53
Stefan Reinauer67b94302015-06-18 01:14:01 -070054#ifdef __x86_64__
55 /* switch to 64 bit long mode */
Patrick Georgi4a30ab92016-01-22 12:26:52 +010056 mov %esi, %ecx
57 add $0, %ecx # core number
58 xor %eax, %eax
59 lea (0x1000+0x23)(%ecx), %edi
60 mov %edi, (%ecx)
61 mov %eax, 4(%ecx)
Stefan Reinauer67b94302015-06-18 01:14:01 -070062
Patrick Georgi4a30ab92016-01-22 12:26:52 +010063 lea 0x1000(%ecx), %edi
64 movl $0x000000e3, 0x00(%edi)
65 movl %eax, 0x04(%edi)
66 movl $0x400000e3, 0x08(%edi)
67 movl %eax, 0x0c(%edi)
68 movl $0x800000e3, 0x10(%edi)
69 movl %eax, 0x14(%edi)
70 movl $0xc00000e3, 0x18(%edi)
71 movl %eax, 0x1c(%edi)
Stefan Reinauer67b94302015-06-18 01:14:01 -070072
Elyes HAOUAS585d1a02016-07-28 19:15:34 +020073 # load ROM based identity mapped page tables
Patrick Georgi4a30ab92016-01-22 12:26:52 +010074 mov %ecx, %eax
75 mov %eax, %cr3
Stefan Reinauer67b94302015-06-18 01:14:01 -070076
77 # enable PAE
Patrick Georgi4a30ab92016-01-22 12:26:52 +010078 mov %cr4, %eax
79 bts $5, %eax
80 mov %eax, %cr4
Stefan Reinauer67b94302015-06-18 01:14:01 -070081
82 # enable long mode
Patrick Georgi4a30ab92016-01-22 12:26:52 +010083 mov $0xC0000080, %ecx
Stefan Reinauer67b94302015-06-18 01:14:01 -070084 rdmsr
Patrick Georgi4a30ab92016-01-22 12:26:52 +010085 bts $8, %eax
Stefan Reinauer67b94302015-06-18 01:14:01 -070086 wrmsr
87
88 # enable paging
Patrick Georgi4a30ab92016-01-22 12:26:52 +010089 mov %cr0, %eax
90 bts $31, %eax
91 mov %eax, %cr0
Stefan Reinauer67b94302015-06-18 01:14:01 -070092
93 # use call far to switch to 64-bit code segment
Patrick Georgi4a30ab92016-01-22 12:26:52 +010094 ljmp $0x18, $1f
951:
Kyösti Mälkki13cf1352016-11-21 07:37:13 +020096
Kyösti Mälkkidf7ff312016-11-25 12:02:00 +020097#endif
efdesign984b508342011-07-13 17:16:13 -070098
Kyösti Mälkki1779d532016-11-23 21:29:26 +020099 /* Calling conventions preserve BIST in %ebp. */
Kyösti Mälkki13cf1352016-11-21 07:37:13 +0200100
Kyösti Mälkki1779d532016-11-23 21:29:26 +0200101 call early_all_cores
efdesign984b508342011-07-13 17:16:13 -0700102
Kyösti Mälkki26929bd2016-11-23 20:40:53 +0200103 /* Must maintain 16-byte stack alignment here. */
104 pushl $0x0
105 pushl $0x0
Kyösti Mälkkidf7ff312016-11-25 12:02:00 +0200106 pushl $0x0
Kyösti Mälkki1779d532016-11-23 21:29:26 +0200107 pushl %ebp
Kyösti Mälkkidf7ff312016-11-25 12:02:00 +0200108 call romstage_main
Kyösti Mälkkiba22e152016-11-23 06:47:15 +0200109 movl %eax, %ebx
efdesign984b508342011-07-13 17:16:13 -0700110
Kyösti Mälkkiba22e152016-11-23 06:47:15 +0200111/* Register %ebx is new stacktop for remaining of romstage.
112 * It is the only register preserved in AMD_DISABLE_STACK.
113 */
efdesign987c0c64e2011-06-20 19:56:06 -0700114
115disable_cache_as_ram:
zbaof7223732012-04-13 13:42:15 +0800116 /* Disable cache */
117 movl %cr0, %eax
Patrick Georgi05e740f2012-03-31 12:52:21 +0200118 orl $CR0_CacheDisable, %eax
zbaof7223732012-04-13 13:42:15 +0800119 movl %eax, %cr0
120
efdesign987c0c64e2011-06-20 19:56:06 -0700121 AMD_DISABLE_STACK
efdesign984b508342011-07-13 17:16:13 -0700122
Siyuan Wangf3b86b32012-11-01 18:51:15 +0800123 /* enable cache */
124 movl %cr0, %eax
125 andl $0x9fffffff, %eax
126 movl %eax, %cr0
Siyuan Wangf3b86b32012-11-01 18:51:15 +0800127
Kyösti Mälkkiba22e152016-11-23 06:47:15 +0200128 movl %ebx, %esp
129 call romstage_after_car
130
131 /* Should never see this postcode */
132 post_code(0xaf)
133stop:
134 jmp stop
efdesign984b508342011-07-13 17:16:13 -0700135
efdesign987c0c64e2011-06-20 19:56:06 -0700136cache_as_ram_setup_out: