efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
Patrick Georgi | b890a12 | 2015-03-26 15:17:45 +0100 | [diff] [blame] | 17 | * Foundation, Inc. |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 18 | */ |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 19 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 20 | /****************************************************************************** |
| 21 | * AMD Generic Encapsulated Software Architecture |
| 22 | * |
| 23 | * $Workfile:: cache_as_ram.inc |
| 24 | * |
| 25 | * Description: cache_as_ram.inc - AGESA Module Entry Point for GCC complier |
| 26 | * |
| 27 | ****************************************************************************** |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 28 | */ |
| 29 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 30 | #include "gcccar.inc" |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 31 | #include <cpu/x86/cache.h> |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 32 | |
| 33 | /* |
| 34 | * XMM map: |
| 35 | * xmm0: BIST |
| 36 | * xmm1: backup ebx -- cpu_init_detected |
| 37 | */ |
| 38 | |
| 39 | .code32 |
| 40 | .globl cache_as_ram_setup, disable_cache_as_ram, cache_as_ram_setup_out |
| 41 | |
| 42 | cache_as_ram_setup: |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 43 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 44 | post_code(0xa0) |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 45 | |
| 46 | /* enable SSE2 128bit instructions */ |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 47 | /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */ |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 48 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 49 | movl %cr4, %eax |
| 50 | orl $(3<<9), %eax |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 51 | movl %eax, %cr4 |
| 52 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 53 | /* Get the cpu_init_detected */ |
| 54 | mov $1, %eax |
| 55 | cpuid |
| 56 | shr $24, %ebx |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 57 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 58 | /* Save the BIST result */ |
| 59 | cvtsi2sd %ebp, %xmm0 |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 60 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 61 | /* for normal part %ebx already contain cpu_init_detected from fallback call */ |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 62 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 63 | /* Save the cpu_init_detected */ |
| 64 | cvtsi2sd %ebx, %xmm1 |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 65 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 66 | post_code(0xa1) |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 67 | |
Stefan Reinauer | 67b9430 | 2015-06-18 01:14:01 -0700 | [diff] [blame^] | 68 | #ifdef __x86_64__ |
| 69 | /* switch to 64 bit long mode */ |
| 70 | .intel_syntax noprefix |
| 71 | |
| 72 | mov ecx, esi |
| 73 | add ecx, 0 # core number |
| 74 | xor eax, eax |
| 75 | lea edi, [ecx+0x1000+0x23] |
| 76 | mov dword ptr [ecx+0], edi |
| 77 | mov dword ptr [ecx+4], eax |
| 78 | |
| 79 | lea edi, [ecx+0x1000] |
| 80 | mov dword ptr [edi+0x00], 0x000000e3 |
| 81 | mov dword ptr [edi+0x04], eax |
| 82 | mov dword ptr [edi+0x08], 0x400000e3 |
| 83 | mov dword ptr [edi+0x0c], eax |
| 84 | mov dword ptr [edi+0x10], 0x800000e3 |
| 85 | mov dword ptr [edi+0x14], eax |
| 86 | mov dword ptr [edi+0x18], 0xc00000e3 |
| 87 | mov dword ptr [edi+0x1c], eax |
| 88 | |
| 89 | # load rom based identity mapped page tables |
| 90 | mov eax, ecx |
| 91 | mov cr3,eax |
| 92 | |
| 93 | # enable PAE |
| 94 | mov eax, cr4 |
| 95 | bts eax, 5 |
| 96 | mov cr4, eax |
| 97 | |
| 98 | # enable long mode |
| 99 | mov ecx, 0xC0000080 |
| 100 | rdmsr |
| 101 | bts eax, 8 |
| 102 | wrmsr |
| 103 | |
| 104 | # enable paging |
| 105 | mov eax, cr0 |
| 106 | bts eax, 31 |
| 107 | mov cr0, eax |
| 108 | |
| 109 | # use call far to switch to 64-bit code segment |
| 110 | jmp 0x18,.+7 |
| 111 | |
| 112 | /* Pass the BIST result */ |
| 113 | cvtsd2si esi, xmm1 |
| 114 | |
| 115 | /* Pass the cpu_init_detected */ |
| 116 | cvtsd2si edi, xmm0 |
| 117 | |
| 118 | /* align the stack */ |
| 119 | and esp, 0xFFFFFFF0 |
| 120 | |
| 121 | .code64 |
| 122 | call cache_as_ram_main |
| 123 | .code32 |
| 124 | |
| 125 | .att_syntax prefix |
| 126 | #else |
| 127 | AMD_ENABLE_STACK |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 128 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 129 | /* Restore the BIST result */ |
| 130 | cvtsd2si %xmm0, %edx |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 131 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 132 | /* Restore the cpu_init_detected */ |
| 133 | cvtsd2si %xmm1, %ebx |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 134 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 135 | pushl %ebx /* init detected */ |
| 136 | pushl %edx /* bist */ |
| 137 | call cache_as_ram_main |
Stefan Reinauer | 67b9430 | 2015-06-18 01:14:01 -0700 | [diff] [blame^] | 138 | #endif |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 139 | |
| 140 | /* Should never see this postcode */ |
| 141 | post_code(0xaf) |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 142 | stop: |
| 143 | jmp stop |
| 144 | |
| 145 | disable_cache_as_ram: |
| 146 | /* Save return stack */ |
Bruce Griffith | 59c3a06 | 2013-08-12 01:53:13 -0600 | [diff] [blame] | 147 | movd 0(%esp), %xmm1 |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 148 | movd %esp, %xmm0 |
| 149 | |
zbao | f722373 | 2012-04-13 13:42:15 +0800 | [diff] [blame] | 150 | /* Disable cache */ |
| 151 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 152 | orl $CR0_CacheDisable, %eax |
zbao | f722373 | 2012-04-13 13:42:15 +0800 | [diff] [blame] | 153 | movl %eax, %cr0 |
| 154 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 155 | AMD_DISABLE_STACK |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 156 | |
Siyuan Wang | f3b86b3 | 2012-11-01 18:51:15 +0800 | [diff] [blame] | 157 | /* enable cache */ |
| 158 | movl %cr0, %eax |
| 159 | andl $0x9fffffff, %eax |
| 160 | movl %eax, %cr0 |
| 161 | xorl %eax, %eax |
| 162 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 163 | /* Restore the return stack */ |
Bruce Griffith | 59c3a06 | 2013-08-12 01:53:13 -0600 | [diff] [blame] | 164 | wbinvd |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 165 | movd %xmm0, %esp |
Bruce Griffith | 59c3a06 | 2013-08-12 01:53:13 -0600 | [diff] [blame] | 166 | movd %xmm1, (%esp) |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 167 | ret |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 168 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 169 | cache_as_ram_setup_out: |
Stefan Reinauer | 67b9430 | 2015-06-18 01:14:01 -0700 | [diff] [blame^] | 170 | #ifdef __x86_64__ |
| 171 | .code64 |
| 172 | #endif |