efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 19 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 20 | /****************************************************************************** |
| 21 | * AMD Generic Encapsulated Software Architecture |
| 22 | * |
| 23 | * $Workfile:: cache_as_ram.inc |
| 24 | * |
| 25 | * Description: cache_as_ram.inc - AGESA Module Entry Point for GCC complier |
| 26 | * |
| 27 | ****************************************************************************** |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 28 | */ |
| 29 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 30 | #include "gcccar.inc" |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 31 | #include <cpu/x86/cache.h> |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 32 | |
| 33 | /* |
| 34 | * XMM map: |
| 35 | * xmm0: BIST |
| 36 | * xmm1: backup ebx -- cpu_init_detected |
| 37 | */ |
| 38 | |
| 39 | .code32 |
| 40 | .globl cache_as_ram_setup, disable_cache_as_ram, cache_as_ram_setup_out |
| 41 | |
| 42 | cache_as_ram_setup: |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 43 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 44 | post_code(0xa0) |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 45 | |
| 46 | /* enable SSE2 128bit instructions */ |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 47 | /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */ |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 48 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 49 | movl %cr4, %eax |
| 50 | orl $(3<<9), %eax |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 51 | movl %eax, %cr4 |
| 52 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 53 | /* Get the cpu_init_detected */ |
| 54 | mov $1, %eax |
| 55 | cpuid |
| 56 | shr $24, %ebx |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 57 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 58 | /* Save the BIST result */ |
| 59 | cvtsi2sd %ebp, %xmm0 |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 60 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 61 | /* for normal part %ebx already contain cpu_init_detected from fallback call */ |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 62 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 63 | /* Save the cpu_init_detected */ |
| 64 | cvtsi2sd %ebx, %xmm1 |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 65 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 66 | post_code(0xa1) |
| 67 | AMD_ENABLE_STACK |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 68 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 69 | post_code(0xa1) |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 70 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 71 | /* Restore the BIST result */ |
| 72 | cvtsd2si %xmm0, %edx |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 73 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 74 | /* Restore the cpu_init_detected */ |
| 75 | cvtsd2si %xmm1, %ebx |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 76 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 77 | pushl %ebx /* init detected */ |
| 78 | pushl %edx /* bist */ |
| 79 | call cache_as_ram_main |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 80 | |
| 81 | /* Should never see this postcode */ |
| 82 | post_code(0xaf) |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 83 | stop: |
| 84 | jmp stop |
| 85 | |
| 86 | disable_cache_as_ram: |
| 87 | /* Save return stack */ |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 88 | movd %esp, %xmm0 |
| 89 | |
zbao | f722373 | 2012-04-13 13:42:15 +0800 | [diff] [blame] | 90 | /* Disable cache */ |
| 91 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 92 | orl $CR0_CacheDisable, %eax |
zbao | f722373 | 2012-04-13 13:42:15 +0800 | [diff] [blame] | 93 | movl %eax, %cr0 |
| 94 | |
| 95 | invd |
| 96 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 97 | AMD_DISABLE_STACK |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 98 | |
Siyuan Wang | f3b86b3 | 2012-11-01 18:51:15 +0800 | [diff] [blame^] | 99 | /* enable cache */ |
| 100 | movl %cr0, %eax |
| 101 | andl $0x9fffffff, %eax |
| 102 | movl %eax, %cr0 |
| 103 | xorl %eax, %eax |
| 104 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 105 | /* Restore the return stack */ |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 106 | movd %xmm0, %esp |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 107 | ret |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 108 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 109 | cache_as_ram_setup_out: |