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review.coreboot.org / coreboot / 4b508341bcf11687be98d20f8178b5cc542a0842 / . / src / cpu / amd / agesa / cache_as_ram.inc
blob: f328db405e4540a76cb8430b6f928fd1d1d3355d [file] [log] [blame]
efdesign987c0c64e2011-06-20 19:56:06 -0700[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
efdesign984b508342011-07-13 17:16:13 -0700[diff] [blame^]19
efdesign987c0c64e2011-06-20 19:56:06 -0700[diff] [blame]20/******************************************************************************
21 * AMD Generic Encapsulated Software Architecture
22 *
23 * $Workfile:: cache_as_ram.inc
24 *
25 * Description: cache_as_ram.inc - AGESA Module Entry Point for GCC complier
26 *
27 ******************************************************************************
efdesign984b508342011-07-13 17:16:13 -0700[diff] [blame^]28 */
29
efdesign987c0c64e2011-06-20 19:56:06 -0700[diff] [blame]30#include "gcccar.inc"
31
32/*
33 * XMM map:
34 * xmm0: BIST
35 * xmm1: backup ebx -- cpu_init_detected
36 */
37
38.code32
39.globl cache_as_ram_setup, disable_cache_as_ram, cache_as_ram_setup_out
40
41cache_as_ram_setup:
efdesign984b508342011-07-13 17:16:13 -0700[diff] [blame^]42
efdesign987c0c64e2011-06-20 19:56:06 -0700[diff] [blame]43 post_code(0xa0)
efdesign984b508342011-07-13 17:16:13 -0700[diff] [blame^]44
45 /* enable SSE2 128bit instructions */
efdesign987c0c64e2011-06-20 19:56:06 -0700[diff] [blame]46 /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */
efdesign984b508342011-07-13 17:16:13 -0700[diff] [blame^]47
efdesign987c0c64e2011-06-20 19:56:06 -0700[diff] [blame]48 movl %cr4, %eax
49 orl $(3<<9), %eax
efdesign984b508342011-07-13 17:16:13 -0700[diff] [blame^]50 movl %eax, %cr4
51
efdesign987c0c64e2011-06-20 19:56:06 -0700[diff] [blame]52 /* Get the cpu_init_detected */
53 mov $1, %eax
54 cpuid
55 shr $24, %ebx
efdesign984b508342011-07-13 17:16:13 -0700[diff] [blame^]56
efdesign987c0c64e2011-06-20 19:56:06 -0700[diff] [blame]57 /* Save the BIST result */
58 cvtsi2sd %ebp, %xmm0
efdesign984b508342011-07-13 17:16:13 -0700[diff] [blame^]59
efdesign987c0c64e2011-06-20 19:56:06 -0700[diff] [blame]60 /* for normal part %ebx already contain cpu_init_detected from fallback call */
efdesign984b508342011-07-13 17:16:13 -0700[diff] [blame^]61
efdesign987c0c64e2011-06-20 19:56:06 -0700[diff] [blame]62 /* Save the cpu_init_detected */
63 cvtsi2sd %ebx, %xmm1
efdesign984b508342011-07-13 17:16:13 -0700[diff] [blame^]64
efdesign987c0c64e2011-06-20 19:56:06 -0700[diff] [blame]65 post_code(0xa1)
66 AMD_ENABLE_STACK
efdesign984b508342011-07-13 17:16:13 -0700[diff] [blame^]67
efdesign987c0c64e2011-06-20 19:56:06 -0700[diff] [blame]68 post_code(0xa1)
efdesign984b508342011-07-13 17:16:13 -0700[diff] [blame^]69
efdesign987c0c64e2011-06-20 19:56:06 -0700[diff] [blame]70 /* Restore the BIST result */
71 cvtsd2si %xmm0, %edx
efdesign984b508342011-07-13 17:16:13 -0700[diff] [blame^]72
efdesign987c0c64e2011-06-20 19:56:06 -0700[diff] [blame]73 /* Restore the cpu_init_detected */
74 cvtsd2si %xmm1, %ebx
efdesign984b508342011-07-13 17:16:13 -0700[diff] [blame^]75
efdesign987c0c64e2011-06-20 19:56:06 -0700[diff] [blame]76 pushl %ebx /* init detected */
77 pushl %edx /* bist */
78 call cache_as_ram_main
efdesign984b508342011-07-13 17:16:13 -0700[diff] [blame^]79
80 /* Should never see this postcode */
81 post_code(0xaf)
efdesign987c0c64e2011-06-20 19:56:06 -0700[diff] [blame]82stop:
83 jmp stop
84
85disable_cache_as_ram:
86 /* Save return stack */
efdesign984b508342011-07-13 17:16:13 -0700[diff] [blame^]87 movd %esp, %xmm0
88
efdesign987c0c64e2011-06-20 19:56:06 -0700[diff] [blame]89 AMD_DISABLE_STACK
efdesign984b508342011-07-13 17:16:13 -0700[diff] [blame^]90
efdesign987c0c64e2011-06-20 19:56:06 -0700[diff] [blame]91 /* Restore the return stack */
efdesign984b508342011-07-13 17:16:13 -0700[diff] [blame^]92 movd %xmm0, %esp
efdesign987c0c64e2011-06-20 19:56:06 -0700[diff] [blame]93 ret
efdesign984b508342011-07-13 17:16:13 -0700[diff] [blame^]94
efdesign987c0c64e2011-06-20 19:56:06 -0700[diff] [blame]95cache_as_ram_setup_out:
96
97