efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 14 | */ |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 15 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 16 | /****************************************************************************** |
| 17 | * AMD Generic Encapsulated Software Architecture |
| 18 | * |
| 19 | * $Workfile:: cache_as_ram.inc |
| 20 | * |
| 21 | * Description: cache_as_ram.inc - AGESA Module Entry Point for GCC complier |
| 22 | * |
| 23 | ****************************************************************************** |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 24 | */ |
| 25 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 26 | #include "gcccar.inc" |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 27 | #include <cpu/x86/cache.h> |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 28 | |
| 29 | /* |
| 30 | * XMM map: |
| 31 | * xmm0: BIST |
| 32 | * xmm1: backup ebx -- cpu_init_detected |
| 33 | */ |
| 34 | |
| 35 | .code32 |
| 36 | .globl cache_as_ram_setup, disable_cache_as_ram, cache_as_ram_setup_out |
| 37 | |
| 38 | cache_as_ram_setup: |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 39 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 40 | post_code(0xa0) |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 41 | |
| 42 | /* enable SSE2 128bit instructions */ |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 43 | /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */ |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 44 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 45 | movl %cr4, %eax |
| 46 | orl $(3<<9), %eax |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 47 | movl %eax, %cr4 |
| 48 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 49 | /* Get the cpu_init_detected */ |
| 50 | mov $1, %eax |
| 51 | cpuid |
| 52 | shr $24, %ebx |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 53 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 54 | /* Save the BIST result */ |
| 55 | cvtsi2sd %ebp, %xmm0 |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 56 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 57 | /* for normal part %ebx already contain cpu_init_detected from fallback call */ |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 58 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 59 | /* Save the cpu_init_detected */ |
| 60 | cvtsi2sd %ebx, %xmm1 |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 61 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 62 | post_code(0xa1) |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 63 | |
Stefan Reinauer | 67b9430 | 2015-06-18 01:14:01 -0700 | [diff] [blame] | 64 | #ifdef __x86_64__ |
| 65 | /* switch to 64 bit long mode */ |
Patrick Georgi | 4a30ab9 | 2016-01-22 12:26:52 +0100 | [diff] [blame] | 66 | mov %esi, %ecx |
| 67 | add $0, %ecx # core number |
| 68 | xor %eax, %eax |
| 69 | lea (0x1000+0x23)(%ecx), %edi |
| 70 | mov %edi, (%ecx) |
| 71 | mov %eax, 4(%ecx) |
Stefan Reinauer | 67b9430 | 2015-06-18 01:14:01 -0700 | [diff] [blame] | 72 | |
Patrick Georgi | 4a30ab9 | 2016-01-22 12:26:52 +0100 | [diff] [blame] | 73 | lea 0x1000(%ecx), %edi |
| 74 | movl $0x000000e3, 0x00(%edi) |
| 75 | movl %eax, 0x04(%edi) |
| 76 | movl $0x400000e3, 0x08(%edi) |
| 77 | movl %eax, 0x0c(%edi) |
| 78 | movl $0x800000e3, 0x10(%edi) |
| 79 | movl %eax, 0x14(%edi) |
| 80 | movl $0xc00000e3, 0x18(%edi) |
| 81 | movl %eax, 0x1c(%edi) |
Stefan Reinauer | 67b9430 | 2015-06-18 01:14:01 -0700 | [diff] [blame] | 82 | |
Elyes HAOUAS | 585d1a0 | 2016-07-28 19:15:34 +0200 | [diff] [blame^] | 83 | # load ROM based identity mapped page tables |
Patrick Georgi | 4a30ab9 | 2016-01-22 12:26:52 +0100 | [diff] [blame] | 84 | mov %ecx, %eax |
| 85 | mov %eax, %cr3 |
Stefan Reinauer | 67b9430 | 2015-06-18 01:14:01 -0700 | [diff] [blame] | 86 | |
| 87 | # enable PAE |
Patrick Georgi | 4a30ab9 | 2016-01-22 12:26:52 +0100 | [diff] [blame] | 88 | mov %cr4, %eax |
| 89 | bts $5, %eax |
| 90 | mov %eax, %cr4 |
Stefan Reinauer | 67b9430 | 2015-06-18 01:14:01 -0700 | [diff] [blame] | 91 | |
| 92 | # enable long mode |
Patrick Georgi | 4a30ab9 | 2016-01-22 12:26:52 +0100 | [diff] [blame] | 93 | mov $0xC0000080, %ecx |
Stefan Reinauer | 67b9430 | 2015-06-18 01:14:01 -0700 | [diff] [blame] | 94 | rdmsr |
Patrick Georgi | 4a30ab9 | 2016-01-22 12:26:52 +0100 | [diff] [blame] | 95 | bts $8, %eax |
Stefan Reinauer | 67b9430 | 2015-06-18 01:14:01 -0700 | [diff] [blame] | 96 | wrmsr |
| 97 | |
| 98 | # enable paging |
Patrick Georgi | 4a30ab9 | 2016-01-22 12:26:52 +0100 | [diff] [blame] | 99 | mov %cr0, %eax |
| 100 | bts $31, %eax |
| 101 | mov %eax, %cr0 |
Stefan Reinauer | 67b9430 | 2015-06-18 01:14:01 -0700 | [diff] [blame] | 102 | |
| 103 | # use call far to switch to 64-bit code segment |
Patrick Georgi | 4a30ab9 | 2016-01-22 12:26:52 +0100 | [diff] [blame] | 104 | ljmp $0x18, $1f |
| 105 | 1: |
Stefan Reinauer | 67b9430 | 2015-06-18 01:14:01 -0700 | [diff] [blame] | 106 | /* Pass the BIST result */ |
Patrick Georgi | 4a30ab9 | 2016-01-22 12:26:52 +0100 | [diff] [blame] | 107 | cvtsd2si %xmm1, %esi |
Stefan Reinauer | 67b9430 | 2015-06-18 01:14:01 -0700 | [diff] [blame] | 108 | |
| 109 | /* Pass the cpu_init_detected */ |
Patrick Georgi | 4a30ab9 | 2016-01-22 12:26:52 +0100 | [diff] [blame] | 110 | cvtsd2si %xmm0, %edi |
Stefan Reinauer | 67b9430 | 2015-06-18 01:14:01 -0700 | [diff] [blame] | 111 | |
| 112 | /* align the stack */ |
Patrick Georgi | 4a30ab9 | 2016-01-22 12:26:52 +0100 | [diff] [blame] | 113 | and $0xFFFFFFF0, %esp |
Stefan Reinauer | 67b9430 | 2015-06-18 01:14:01 -0700 | [diff] [blame] | 114 | |
| 115 | .code64 |
| 116 | call cache_as_ram_main |
| 117 | .code32 |
| 118 | |
Stefan Reinauer | 67b9430 | 2015-06-18 01:14:01 -0700 | [diff] [blame] | 119 | #else |
| 120 | AMD_ENABLE_STACK |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 121 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 122 | /* Restore the BIST result */ |
| 123 | cvtsd2si %xmm0, %edx |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 124 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 125 | /* Restore the cpu_init_detected */ |
| 126 | cvtsd2si %xmm1, %ebx |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 127 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 128 | pushl %ebx /* init detected */ |
| 129 | pushl %edx /* bist */ |
| 130 | call cache_as_ram_main |
Stefan Reinauer | 67b9430 | 2015-06-18 01:14:01 -0700 | [diff] [blame] | 131 | #endif |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 132 | |
| 133 | /* Should never see this postcode */ |
| 134 | post_code(0xaf) |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 135 | stop: |
| 136 | jmp stop |
| 137 | |
| 138 | disable_cache_as_ram: |
| 139 | /* Save return stack */ |
Bruce Griffith | 59c3a06 | 2013-08-12 01:53:13 -0600 | [diff] [blame] | 140 | movd 0(%esp), %xmm1 |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 141 | movd %esp, %xmm0 |
| 142 | |
zbao | f722373 | 2012-04-13 13:42:15 +0800 | [diff] [blame] | 143 | /* Disable cache */ |
| 144 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 145 | orl $CR0_CacheDisable, %eax |
zbao | f722373 | 2012-04-13 13:42:15 +0800 | [diff] [blame] | 146 | movl %eax, %cr0 |
| 147 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 148 | AMD_DISABLE_STACK |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 149 | |
Siyuan Wang | f3b86b3 | 2012-11-01 18:51:15 +0800 | [diff] [blame] | 150 | /* enable cache */ |
| 151 | movl %cr0, %eax |
| 152 | andl $0x9fffffff, %eax |
| 153 | movl %eax, %cr0 |
| 154 | xorl %eax, %eax |
| 155 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 156 | /* Restore the return stack */ |
Bruce Griffith | 59c3a06 | 2013-08-12 01:53:13 -0600 | [diff] [blame] | 157 | wbinvd |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 158 | movd %xmm0, %esp |
Bruce Griffith | 59c3a06 | 2013-08-12 01:53:13 -0600 | [diff] [blame] | 159 | movd %xmm1, (%esp) |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 160 | ret |
efdesign98 | 4b50834 | 2011-07-13 17:16:13 -0700 | [diff] [blame] | 161 | |
efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame] | 162 | cache_as_ram_setup_out: |
Stefan Reinauer | 67b9430 | 2015-06-18 01:14:01 -0700 | [diff] [blame] | 163 | #ifdef __x86_64__ |
| 164 | .code64 |
| 165 | #endif |