commit 67b9430b367a9f9a884043f14365a55b7ef3c45c
author Stefan Reinauer <stefan.reinauer@coreboot.org> Thu Jun 18 01:14:01 2015 -0700
committer Stefan Reinauer <stefan.reinauer@coreboot.org> Tue Jul 21 23:36:06 2015 +0200
tree 950a1b04563c5471b256a95f10cdc5b9e70628b3
parent 29e6548ac2b720bdccf8367d2a663f128351df38

cpu: port amd/agesa to 64bit

Change-Id: I8644b04f4b57db5fc95ec155d3f78d53c63c9831
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/10579
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>

src/cpu/amd/agesa/cache_as_ram.inc

diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc
index a8dbee8..b19f03b 100644
--- a/src/cpu/amd/agesa/cache_as_ram.inc
+++ b/src/cpu/amd/agesa/cache_as_ram.inc
@@ -64,9 +64,67 @@
   cvtsi2sd  %ebx, %xmm1
 
   post_code(0xa1)
-  AMD_ENABLE_STACK
 
-  post_code(0xa1)
+#ifdef __x86_64__
+  /* switch to 64 bit long mode */
+  .intel_syntax noprefix
+
+  mov     ecx, esi
+  add     ecx, 0 # core number
+  xor     eax, eax
+  lea     edi, [ecx+0x1000+0x23]
+  mov     dword ptr [ecx+0], edi
+  mov     dword ptr [ecx+4], eax
+
+  lea     edi, [ecx+0x1000]
+  mov     dword ptr [edi+0x00], 0x000000e3
+  mov     dword ptr [edi+0x04], eax
+  mov     dword ptr [edi+0x08], 0x400000e3
+  mov     dword ptr [edi+0x0c], eax
+  mov     dword ptr [edi+0x10], 0x800000e3
+  mov     dword ptr [edi+0x14], eax
+  mov     dword ptr [edi+0x18], 0xc00000e3
+  mov     dword ptr [edi+0x1c], eax
+
+  # load rom based identity mapped page tables
+  mov     eax, ecx
+  mov     cr3,eax
+
+  # enable PAE
+  mov     eax, cr4
+  bts     eax, 5
+  mov     cr4, eax
+
+  # enable long mode
+  mov     ecx, 0xC0000080
+  rdmsr
+  bts     eax, 8
+  wrmsr
+
+  # enable paging
+  mov     eax, cr0
+  bts     eax, 31
+  mov     cr0, eax
+
+  # use call far to switch to 64-bit code segment
+  jmp 0x18,.+7
+
+  /* Pass the BIST result */
+  cvtsd2si        esi, xmm1
+
+  /* Pass the cpu_init_detected */
+  cvtsd2si        edi, xmm0
+
+  /* align the stack */
+  and     esp, 0xFFFFFFF0
+
+  .code64
+  call    cache_as_ram_main
+  .code32
+
+  .att_syntax prefix
+#else
+  AMD_ENABLE_STACK
 
   /* Restore the BIST result */
   cvtsd2si  %xmm0, %edx
@@ -77,6 +135,7 @@
   pushl %ebx  /* init detected */
   pushl %edx  /* bist */
   call  cache_as_ram_main
+#endif
 
   /* Should never see this postcode */
   post_code(0xaf)
@@ -108,3 +167,6 @@
   ret
 
 cache_as_ram_setup_out:
+#ifdef __x86_64__
+.code64
+#endif