| efdesign98 | 7c0c64e | 2011-06-20 19:56:06 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | /****************************************************************************** |
| 21 | * AMD Generic Encapsulated Software Architecture |
| 22 | * |
| 23 | * $Workfile:: cache_as_ram.inc |
| 24 | * |
| 25 | * Description: cache_as_ram.inc - AGESA Module Entry Point for GCC complier |
| 26 | * |
| 27 | ****************************************************************************** |
| 28 | */ |
| 29 | |
| 30 | #include "gcccar.inc" |
| 31 | |
| 32 | /* |
| 33 | * XMM map: |
| 34 | * xmm0: BIST |
| 35 | * xmm1: backup ebx -- cpu_init_detected |
| 36 | */ |
| 37 | |
| 38 | .code32 |
| 39 | .globl cache_as_ram_setup, disable_cache_as_ram, cache_as_ram_setup_out |
| 40 | |
| 41 | cache_as_ram_setup: |
| 42 | |
| 43 | post_code(0xa0) |
| 44 | |
| 45 | /* enable SSE2 128bit instructions */ |
| 46 | /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */ |
| 47 | |
| 48 | movl %cr4, %eax |
| 49 | orl $(3<<9), %eax |
| 50 | movl %eax, %cr4 |
| 51 | |
| 52 | /* Get the cpu_init_detected */ |
| 53 | mov $1, %eax |
| 54 | cpuid |
| 55 | shr $24, %ebx |
| 56 | |
| 57 | /* Save the BIST result */ |
| 58 | cvtsi2sd %ebp, %xmm0 |
| 59 | |
| 60 | /* for normal part %ebx already contain cpu_init_detected from fallback call */ |
| 61 | |
| 62 | /* Save the cpu_init_detected */ |
| 63 | cvtsi2sd %ebx, %xmm1 |
| 64 | |
| 65 | post_code(0xa1) |
| 66 | AMD_ENABLE_STACK |
| 67 | |
| 68 | post_code(0xa1) |
| 69 | |
| 70 | /* Restore the BIST result */ |
| 71 | cvtsd2si %xmm0, %edx |
| 72 | |
| 73 | /* Restore the cpu_init_detected */ |
| 74 | cvtsd2si %xmm1, %ebx |
| 75 | |
| 76 | pushl %ebx /* init detected */ |
| 77 | pushl %edx /* bist */ |
| 78 | call cache_as_ram_main |
| 79 | |
| 80 | /* Should never see this postcode */ |
| 81 | post_code(0xaf) |
| 82 | stop: |
| 83 | jmp stop |
| 84 | |
| 85 | disable_cache_as_ram: |
| 86 | /* Save return stack */ |
| 87 | cvtsi2sd %esp, %xmm0 |
| 88 | |
| 89 | AMD_DISABLE_STACK |
| 90 | |
| 91 | /* Restore the return stack */ |
| 92 | cvtsd2si %xmm0, %esp |
| 93 | |
| 94 | ret |
| 95 | |
| 96 | cache_as_ram_setup_out: |
| 97 | |
| 98 | |