Angel Pons | 3bd1e3d | 2020-04-05 15:47:17 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 2 | |
Wim Vervoorn | d137150 | 2019-12-17 14:10:16 +0100 | [diff] [blame] | 3 | #include <cbmem.h> |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 4 | #include <fsp/api.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 5 | #include <acpi/acpi.h> |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 6 | #include <console/console.h> |
| 7 | #include <device/device.h> |
Gaggery Tsai | 711fb81 | 2018-05-22 12:32:48 -0700 | [diff] [blame] | 8 | #include <device/pci_ids.h> |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 9 | #include <fsp/util.h> |
Kyösti Mälkki | 32d47eb | 2019-09-28 00:00:30 +0300 | [diff] [blame] | 10 | #include <intelblocks/cfg.h> |
Subrata Banik | 46caf09 | 2018-09-28 19:54:30 +0530 | [diff] [blame] | 11 | #include <intelblocks/itss.h> |
Nico Huber | 44e89af | 2019-02-23 19:24:51 +0100 | [diff] [blame] | 12 | #include <intelblocks/lpc_lib.h> |
Subrata Banik | cf32fd1 | 2018-12-19 18:02:17 +0530 | [diff] [blame] | 13 | #include <intelblocks/mp_init.h> |
Nico Huber | ad91b18 | 2019-10-12 15:16:33 +0200 | [diff] [blame] | 14 | #include <intelblocks/pcie_rp.h> |
Sumeet R Pawnikar | 97c5464 | 2020-05-10 01:24:11 +0530 | [diff] [blame] | 15 | #include <intelblocks/power_limit.h> |
Duncan Laurie | f511695 | 2018-03-26 02:24:18 -0700 | [diff] [blame] | 16 | #include <intelblocks/xdci.h> |
Patrick Rudolph | 5199e82 | 2019-09-26 14:00:14 +0200 | [diff] [blame] | 17 | #include <intelblocks/p2sb.h> |
Subrata Banik | 9cd99a1 | 2018-05-28 16:12:03 +0530 | [diff] [blame] | 18 | #include <intelpch/lockdown.h> |
Brandon Breitenstein | c6ec8dd | 2016-11-17 12:23:04 -0800 | [diff] [blame] | 19 | #include <romstage_handoff.h> |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 20 | #include <soc/acpi.h> |
Patrick Georgi | c6a0050 | 2017-10-05 18:19:29 +0200 | [diff] [blame] | 21 | #include <soc/intel/common/vbt.h> |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 22 | #include <soc/interrupt.h> |
Nico Huber | 2afe4dc | 2017-09-19 09:36:03 +0200 | [diff] [blame] | 23 | #include <soc/iomap.h> |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 24 | #include <soc/irq.h> |
Subrata Banik | 46caf09 | 2018-09-28 19:54:30 +0530 | [diff] [blame] | 25 | #include <soc/itss.h> |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 26 | #include <soc/pci_devs.h> |
| 27 | #include <soc/ramstage.h> |
Nico Huber | 2afe4dc | 2017-09-19 09:36:03 +0200 | [diff] [blame] | 28 | #include <soc/systemagent.h> |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 29 | #include <string.h> |
| 30 | |
Elyes HAOUAS | c338507 | 2019-03-21 15:38:06 +0100 | [diff] [blame] | 31 | #include "chip.h" |
| 32 | |
Nico Huber | ad91b18 | 2019-10-12 15:16:33 +0200 | [diff] [blame] | 33 | static const struct pcie_rp_group pch_lp_rp_groups[] = { |
| 34 | { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, |
| 35 | { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4 }, |
| 36 | { 0 } |
Gaggery Tsai | 711fb81 | 2018-05-22 12:32:48 -0700 | [diff] [blame] | 37 | }; |
| 38 | |
Nico Huber | ad91b18 | 2019-10-12 15:16:33 +0200 | [diff] [blame] | 39 | static const struct pcie_rp_group pch_h_rp_groups[] = { |
| 40 | { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, |
| 41 | { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8 }, |
| 42 | /* Sunrise Point PCH-H actually only has 4 ports in the |
| 43 | third group. But that would require a runtime check |
| 44 | and probing 4 non-existent ports shouldn't hurt. */ |
| 45 | { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8 }, |
| 46 | { 0 } |
Gaggery Tsai | 711fb81 | 2018-05-22 12:32:48 -0700 | [diff] [blame] | 47 | }; |
| 48 | |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 49 | void soc_init_pre_device(void *chip_info) |
| 50 | { |
Subrata Banik | 46caf09 | 2018-09-28 19:54:30 +0530 | [diff] [blame] | 51 | /* Snapshot the current GPIO IRQ polarities. FSP is setting a |
| 52 | * default policy that doesn't honor boards' requirements. */ |
| 53 | itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); |
| 54 | |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 55 | /* Perform silicon specific init. */ |
Aaron Durbin | 6c191d8 | 2016-11-29 21:22:42 -0600 | [diff] [blame] | 56 | fsp_silicon_init(romstage_handoff_is_resume()); |
Subrata Banik | 46caf09 | 2018-09-28 19:54:30 +0530 | [diff] [blame] | 57 | |
Patrick Rudolph | 5199e82 | 2019-09-26 14:00:14 +0200 | [diff] [blame] | 58 | /* |
| 59 | * Keep the P2SB device visible so it and the other devices are |
| 60 | * visible in coreboot for driver support and PCI resource allocation. |
| 61 | * There is no UPD setting for this. |
| 62 | */ |
| 63 | p2sb_unhide(); |
| 64 | |
Subrata Banik | 46caf09 | 2018-09-28 19:54:30 +0530 | [diff] [blame] | 65 | /* Restore GPIO IRQ polarities back to previous settings. */ |
| 66 | itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); |
| 67 | |
Gaggery Tsai | 711fb81 | 2018-05-22 12:32:48 -0700 | [diff] [blame] | 68 | /* swap enabled PCI ports in device tree if needed */ |
Nico Huber | ad91b18 | 2019-10-12 15:16:33 +0200 | [diff] [blame] | 69 | if (CONFIG(SKYLAKE_SOC_PCH_H)) |
| 70 | pcie_rp_update_devicetree(pch_h_rp_groups); |
| 71 | else |
| 72 | pcie_rp_update_devicetree(pch_lp_rp_groups); |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 73 | } |
| 74 | |
Furquan Shaikh | c248044 | 2017-02-20 13:41:56 -0800 | [diff] [blame] | 75 | void soc_fsp_load(void) |
| 76 | { |
| 77 | fsps_load(romstage_handoff_is_resume()); |
| 78 | } |
| 79 | |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 80 | static struct device_operations pci_domain_ops = { |
| 81 | .read_resources = &pci_domain_read_resources, |
| 82 | .set_resources = &pci_domain_set_resources, |
| 83 | .scan_bus = &pci_domain_scan_bus, |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 84 | #if CONFIG(HAVE_ACPI_TABLES) |
Nico Huber | c37b0e3 | 2017-09-18 20:03:46 +0200 | [diff] [blame] | 85 | .write_acpi_tables = &northbridge_write_acpi_tables, |
| 86 | .acpi_name = &soc_acpi_name, |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 87 | #endif |
| 88 | }; |
| 89 | |
| 90 | static struct device_operations cpu_bus_ops = { |
Nico Huber | 2f8ba69 | 2020-04-05 14:05:24 +0200 | [diff] [blame] | 91 | .read_resources = noop_read_resources, |
| 92 | .set_resources = noop_set_resources, |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 93 | #if CONFIG(HAVE_ACPI_TABLES) |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 94 | .acpi_fill_ssdt = generate_cpu_entries, |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 95 | #endif |
| 96 | }; |
| 97 | |
Elyes HAOUAS | 143fb46 | 2018-05-25 12:56:45 +0200 | [diff] [blame] | 98 | static void soc_enable(struct device *dev) |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 99 | { |
| 100 | /* Set the operations if it is a special bus type */ |
Subrata Banik | 3c838c7 | 2017-12-06 18:14:01 +0530 | [diff] [blame] | 101 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 102 | dev->ops = &pci_domain_ops; |
Subrata Banik | 3c838c7 | 2017-12-06 18:14:01 +0530 | [diff] [blame] | 103 | else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 104 | dev->ops = &cpu_bus_ops; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 105 | } |
| 106 | |
| 107 | struct chip_operations soc_intel_skylake_ops = { |
| 108 | CHIP_NAME("Intel 6th Gen") |
| 109 | .enable_dev = &soc_enable, |
| 110 | .init = &soc_init_pre_device, |
| 111 | }; |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 112 | |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 113 | /* UPD parameters to be initialized before SiliconInit */ |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 114 | void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 115 | { |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 116 | FSP_S_CONFIG *params = &supd->FspsConfig; |
| 117 | FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig; |
Kyösti Mälkki | 4af4e7f | 2019-07-14 05:50:20 +0300 | [diff] [blame] | 118 | struct soc_intel_skylake_config *config; |
Kyösti Mälkki | 28dc7dc | 2019-07-12 13:10:19 +0300 | [diff] [blame] | 119 | struct device *dev; |
Patrick Georgi | d2990ff | 2018-05-03 18:06:15 +0200 | [diff] [blame] | 120 | uintptr_t vbt_data = (uintptr_t)vbt_get(); |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 121 | int i; |
| 122 | |
Kyösti Mälkki | d5f645c | 2019-09-28 00:20:27 +0300 | [diff] [blame] | 123 | config = config_of_soc(); |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 124 | |
| 125 | mainboard_silicon_init_params(params); |
Sumeet R Pawnikar | 97c5464 | 2020-05-10 01:24:11 +0530 | [diff] [blame] | 126 | |
| 127 | struct soc_power_limits_config *soc_confg; |
| 128 | config_t *confg = config_of_soc(); |
| 129 | soc_confg = &confg->power_limits_config; |
Gaggery Tsai | da6f4ae | 2018-01-15 15:03:01 +0800 | [diff] [blame] | 130 | /* Set PsysPmax if it is available from DT */ |
Sumeet R Pawnikar | 97c5464 | 2020-05-10 01:24:11 +0530 | [diff] [blame] | 131 | if (soc_confg->psys_pmax) { |
Gaggery Tsai | da6f4ae | 2018-01-15 15:03:01 +0800 | [diff] [blame] | 132 | /* PsysPmax is in unit of 1/8 Watt */ |
Sumeet R Pawnikar | 97c5464 | 2020-05-10 01:24:11 +0530 | [diff] [blame] | 133 | tconfig->PsysPmax = soc_confg->psys_pmax * 8; |
Gaggery Tsai | da6f4ae | 2018-01-15 15:03:01 +0800 | [diff] [blame] | 134 | printk(BIOS_DEBUG, "psys_pmax = %d\n", tconfig->PsysPmax); |
| 135 | } |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 136 | |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 137 | params->GraphicsConfigPtr = (u32) vbt_data; |
| 138 | |
| 139 | for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { |
| 140 | params->PortUsb20Enable[i] = |
| 141 | config->usb2_ports[i].enable; |
| 142 | params->Usb2AfePetxiset[i] = |
| 143 | config->usb2_ports[i].pre_emp_bias; |
| 144 | params->Usb2AfeTxiset[i] = |
| 145 | config->usb2_ports[i].tx_bias; |
| 146 | params->Usb2AfePredeemp[i] = |
| 147 | config->usb2_ports[i].tx_emp_enable; |
| 148 | params->Usb2AfePehalfbit[i] = |
| 149 | config->usb2_ports[i].pre_emp_bit; |
Michael Niewöhner | 056d552 | 2020-09-04 15:40:35 +0200 | [diff] [blame] | 150 | |
| 151 | if (config->usb2_ports[i].enable) |
| 152 | params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; |
| 153 | else |
| 154 | params->Usb2OverCurrentPin[i] = 0xff; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 155 | } |
| 156 | |
| 157 | for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { |
| 158 | params->PortUsb30Enable[i] = config->usb3_ports[i].enable; |
Michael Niewöhner | 056d552 | 2020-09-04 15:40:35 +0200 | [diff] [blame] | 159 | if (config->usb3_ports[i].enable) { |
| 160 | params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; |
| 161 | } else { |
| 162 | params->Usb3OverCurrentPin[i] = 0xff; |
| 163 | } |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 164 | if (config->usb3_ports[i].tx_de_emp) { |
| 165 | params->Usb3HsioTxDeEmphEnable[i] = 1; |
| 166 | params->Usb3HsioTxDeEmph[i] = |
| 167 | config->usb3_ports[i].tx_de_emp; |
| 168 | } |
| 169 | if (config->usb3_ports[i].tx_downscale_amp) { |
| 170 | params->Usb3HsioTxDownscaleAmpEnable[i] = 1; |
| 171 | params->Usb3HsioTxDownscaleAmp[i] = |
| 172 | config->usb3_ports[i].tx_downscale_amp; |
| 173 | } |
| 174 | } |
| 175 | |
Felix Singer | 0901d03 | 2020-07-29 19:57:25 +0200 | [diff] [blame] | 176 | dev = pcidev_path_on_root(PCH_DEVFN_SATA); |
Felix Singer | e104934 | 2020-08-11 06:34:15 +0200 | [diff] [blame] | 177 | params->SataEnable = dev && dev->enabled; |
Felix Singer | 0901d03 | 2020-07-29 19:57:25 +0200 | [diff] [blame] | 178 | if (params->SataEnable) { |
Felix Singer | 4e58ce1 | 2020-07-25 04:39:52 +0200 | [diff] [blame] | 179 | memcpy(params->SataPortsEnable, config->SataPortsEnable, |
| 180 | sizeof(params->SataPortsEnable)); |
| 181 | memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, |
| 182 | sizeof(params->SataPortsDevSlp)); |
| 183 | memcpy(params->SataPortsHotPlug, config->SataPortsHotPlug, |
| 184 | sizeof(params->SataPortsHotPlug)); |
| 185 | memcpy(params->SataPortsSpinUp, config->SataPortsSpinUp, |
| 186 | sizeof(params->SataPortsSpinUp)); |
| 187 | |
| 188 | params->SataSalpSupport = config->SataSalpSupport; |
| 189 | params->SataMode = config->SataMode; |
| 190 | params->SataSpeedLimit = config->SataSpeedLimit; |
| 191 | /* |
| 192 | * For unknown reasons FSP skips writing some essential SATA init registers |
| 193 | * (SIR) when SataPwrOptEnable=0. This results in link errors, "unaligned |
| 194 | * write" errors and others. Enabling this option solves these problems. |
| 195 | */ |
| 196 | params->SataPwrOptEnable = 1; |
| 197 | tconfig->SataTestMode = config->SataTestMode; |
| 198 | } |
| 199 | |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 200 | memcpy(params->PcieRpClkReqSupport, config->PcieRpClkReqSupport, |
| 201 | sizeof(params->PcieRpClkReqSupport)); |
| 202 | memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber, |
| 203 | sizeof(params->PcieRpClkReqNumber)); |
Rizwan Qureshi | 6ab4ed4 | 2017-09-05 14:18:25 +0530 | [diff] [blame] | 204 | memcpy(params->PcieRpAdvancedErrorReporting, |
| 205 | config->PcieRpAdvancedErrorReporting, |
| 206 | sizeof(params->PcieRpAdvancedErrorReporting)); |
Rizwan Qureshi | 0393739 | 2017-09-16 01:54:20 +0530 | [diff] [blame] | 207 | memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable, |
| 208 | sizeof(params->PcieRpLtrEnable)); |
Duncan Laurie | 74ea48e | 2018-01-29 12:00:47 -0800 | [diff] [blame] | 209 | memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, |
| 210 | sizeof(params->PcieRpHotPlug)); |
Wim Vervoorn | 5819eab | 2020-05-07 13:16:32 +0200 | [diff] [blame] | 211 | for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { |
Wim Vervoorn | d6b682c | 2020-05-07 12:41:13 +0200 | [diff] [blame] | 212 | params->PcieRpMaxPayload[i] = config->PcieRpMaxPayload[i]; |
Wim Vervoorn | 5819eab | 2020-05-07 13:16:32 +0200 | [diff] [blame] | 213 | if (config->PcieRpAspm[i]) |
| 214 | params->PcieRpAspm[i] = config->PcieRpAspm[i] - 1; |
Benjamin Doron | adcb870 | 2020-03-14 01:53:25 +0000 | [diff] [blame] | 215 | if (config->pcie_rp_l1substates[i]) |
| 216 | params->PcieRpL1Substates[i] = config->pcie_rp_l1substates[i] - 1; |
Wim Vervoorn | 5819eab | 2020-05-07 13:16:32 +0200 | [diff] [blame] | 217 | } |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 218 | |
Divya Chellap | e7fb7ce | 2017-12-19 20:16:50 +0530 | [diff] [blame] | 219 | /* |
| 220 | * PcieRpClkSrcNumber UPD is set to clock source number(0-6) for |
| 221 | * all the enabled PCIe root ports, invalid(0x1F) is set for |
| 222 | * disabled PCIe root ports. |
| 223 | */ |
| 224 | for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { |
| 225 | if (config->PcieRpClkReqSupport[i]) |
| 226 | params->PcieRpClkSrcNumber[i] = |
| 227 | config->PcieRpClkSrcNumber[i]; |
| 228 | else |
| 229 | params->PcieRpClkSrcNumber[i] = 0x1F; |
| 230 | } |
| 231 | |
Naresh G Solanki | eedf6d8 | 2016-11-16 21:27:38 +0530 | [diff] [blame] | 232 | /* disable Legacy PME */ |
| 233 | memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); |
| 234 | |
Subrata Banik | 10a9432 | 2019-07-08 14:49:22 +0530 | [diff] [blame] | 235 | /* Legacy 8254 timer support */ |
Martin Roth | c25c1eb | 2020-07-24 12:26:21 -0600 | [diff] [blame] | 236 | params->Early8254ClockGatingEnable = !CONFIG(USE_LEGACY_8254_TIMER); |
Subrata Banik | 10a9432 | 2019-07-08 14:49:22 +0530 | [diff] [blame] | 237 | |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 238 | memcpy(params->SerialIoDevMode, config->SerialIoDevMode, |
| 239 | sizeof(params->SerialIoDevMode)); |
| 240 | |
Felix Singer | e218667 | 2020-07-29 23:20:52 +0200 | [diff] [blame] | 241 | dev = pcidev_path_on_root(PCH_DEVFN_CIO); |
| 242 | params->PchCio2Enable = dev && dev->enabled; |
Felix Singer | 4d5c4e0 | 2020-07-29 22:28:37 +0200 | [diff] [blame] | 243 | |
| 244 | dev = pcidev_path_on_root(SA_DEVFN_IMGU); |
| 245 | params->SaImguEnable = dev && dev->enabled; |
Felix Singer | 91dfb92 | 2020-07-25 14:01:52 +0200 | [diff] [blame] | 246 | |
| 247 | dev = pcidev_path_on_root(PCH_DEVFN_CSE_3); |
Felix Singer | e104934 | 2020-08-11 06:34:15 +0200 | [diff] [blame] | 248 | params->Heci3Enabled = dev && dev->enabled; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 249 | |
| 250 | params->LogoPtr = config->LogoPtr; |
| 251 | params->LogoSize = config->LogoSize; |
| 252 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 253 | params->CpuConfig.Bits.VmxEnable = CONFIG(ENABLE_VMX); |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 254 | |
| 255 | params->PchPmWoWlanEnable = config->PchPmWoWlanEnable; |
| 256 | params->PchPmWoWlanDeepSxEnable = config->PchPmWoWlanDeepSxEnable; |
| 257 | params->PchPmLanWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx; |
| 258 | |
Felix Singer | 57c8143 | 2020-07-25 07:50:51 +0200 | [diff] [blame] | 259 | dev = pcidev_path_on_root(PCH_DEVFN_GBE); |
Felix Singer | e104934 | 2020-08-11 06:34:15 +0200 | [diff] [blame] | 260 | params->PchLanEnable = dev && dev->enabled; |
Felix Singer | 57c8143 | 2020-07-25 07:50:51 +0200 | [diff] [blame] | 261 | if (params->PchLanEnable) { |
Duncan Laurie | 14485ef | 2017-12-13 13:58:35 -0800 | [diff] [blame] | 262 | params->PchLanLtrEnable = config->EnableLanLtr; |
| 263 | params->PchLanK1OffEnable = config->EnableLanK1Off; |
| 264 | params->PchLanClkReqSupported = config->LanClkReqSupported; |
| 265 | params->PchLanClkReqNumber = config->LanClkReqNumber; |
| 266 | } |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 267 | params->SsicPortEnable = config->SsicPortEnable; |
Felix Singer | aff69be | 2020-07-25 13:37:17 +0200 | [diff] [blame] | 268 | |
| 269 | dev = pcidev_path_on_root(PCH_DEVFN_EMMC); |
Felix Singer | e104934 | 2020-08-11 06:34:15 +0200 | [diff] [blame] | 270 | params->ScsEmmcEnabled = dev && dev->enabled; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 271 | params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; |
Felix Singer | 5291952 | 2020-07-29 21:44:36 +0200 | [diff] [blame] | 272 | |
| 273 | dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); |
| 274 | params->ScsSdCardEnabled = dev && dev->enabled; |
li feng | 2106638 | 2018-05-22 12:49:53 -0700 | [diff] [blame] | 275 | |
Pratik Prajapati | e072247 | 2018-08-22 18:58:38 -0700 | [diff] [blame] | 276 | if (!!params->ScsEmmcHs400Enabled && !!config->EmmcHs400DllNeed) { |
| 277 | params->PchScsEmmcHs400DllDataValid = |
| 278 | !!config->EmmcHs400DllNeed; |
| 279 | params->PchScsEmmcHs400RxStrobeDll1 = |
| 280 | config->ScsEmmcHs400RxStrobeDll1; |
| 281 | params->PchScsEmmcHs400TxDataDll = |
| 282 | config->ScsEmmcHs400TxDataDll; |
| 283 | } |
| 284 | |
li feng | 2106638 | 2018-05-22 12:49:53 -0700 | [diff] [blame] | 285 | /* If ISH is enabled, enable ISH elements */ |
Kyösti Mälkki | 903b40a | 2019-07-03 07:25:59 +0300 | [diff] [blame] | 286 | dev = pcidev_path_on_root(PCH_DEVFN_ISH); |
Felix Singer | e104934 | 2020-08-11 06:34:15 +0200 | [diff] [blame] | 287 | params->PchIshEnable = dev && dev->enabled; |
li feng | 2106638 | 2018-05-22 12:49:53 -0700 | [diff] [blame] | 288 | |
Felix Singer | 048d9b5 | 2020-07-25 14:31:58 +0200 | [diff] [blame] | 289 | dev = pcidev_path_on_root(PCH_DEVFN_HDA); |
Felix Singer | e104934 | 2020-08-11 06:34:15 +0200 | [diff] [blame] | 290 | params->PchHdaEnable = dev && dev->enabled; |
Felix Singer | 048d9b5 | 2020-07-25 14:31:58 +0200 | [diff] [blame] | 291 | |
Michael Niewöhner | 6238563 | 2019-09-23 14:38:41 +0200 | [diff] [blame] | 292 | params->PchHdaVcType = config->PchHdaVcType; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 293 | params->PchHdaIoBufferOwnership = config->IoBufferOwnership; |
| 294 | params->PchHdaDspEnable = config->DspEnable; |
Felix Singer | 9c1c009 | 2020-07-29 20:48:08 +0200 | [diff] [blame] | 295 | |
| 296 | dev = pcidev_path_on_root(SA_DEVFN_TS); |
| 297 | params->Device4Enable = dev && dev->enabled; |
Naresh G Solanki | 84fbc30 | 2018-10-15 15:37:15 +0530 | [diff] [blame] | 298 | params->EnableTcoTimer = !config->PmTimerDisabled; |
Matt DeVillier | 9e0d69b | 2017-10-10 14:03:36 -0500 | [diff] [blame] | 299 | |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 300 | tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 301 | tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock; |
Praveen hodagatta pranesh | 015b3dc | 2018-11-23 17:41:46 +0800 | [diff] [blame] | 302 | tconfig->PowerLimit4 = config->PowerLimit4; |
Barnali Sarkar | fbf1018 | 2017-08-11 18:38:38 +0530 | [diff] [blame] | 303 | /* |
| 304 | * To disable HECI, the Psf needs to be left unlocked |
| 305 | * by FSP till end of post sequence. Based on the devicetree |
| 306 | * setting, we set the appropriate PsfUnlock policy in FSP, |
| 307 | * do the changes and then lock it back in coreboot during finalize. |
| 308 | */ |
| 309 | tconfig->PchSbAccessUnlock = (config->HeciEnabled == 0) ? 1 : 0; |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 310 | if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { |
Subrata Banik | c204aaa | 2017-08-17 15:49:58 +0530 | [diff] [blame] | 311 | tconfig->PchLockDownBiosInterface = 0; |
| 312 | params->PchLockDownBiosLock = 0; |
| 313 | params->PchLockDownSpiEiss = 0; |
| 314 | /* |
| 315 | * Skip Spi Flash Lockdown from inside FSP. |
| 316 | * Making this config "0" means FSP won't set the FLOCKDN bit |
| 317 | * of SPIBAR + 0x04 (i.e., Bit 15 of BIOS_HSFSTS_CTL). |
| 318 | * So, it becomes coreboot's responsibility to set this bit |
| 319 | * before end of POST for security concerns. |
| 320 | */ |
| 321 | params->SpiFlashCfgLockDown = 0; |
| 322 | } |
Matt Delco | dfffcad | 2018-07-23 12:44:15 -0700 | [diff] [blame] | 323 | /* only replacing preexisting subsys ID defaults when non-zero */ |
Elyes HAOUAS | b58e99d | 2019-01-23 12:04:43 +0100 | [diff] [blame] | 324 | if (CONFIG_SUBSYSTEM_VENDOR_ID != 0) { |
| 325 | params->DefaultSvid = CONFIG_SUBSYSTEM_VENDOR_ID; |
| 326 | params->PchSubSystemVendorId = CONFIG_SUBSYSTEM_VENDOR_ID; |
| 327 | } |
| 328 | |
| 329 | if (CONFIG_SUBSYSTEM_DEVICE_ID != 0) { |
| 330 | params->DefaultSid = CONFIG_SUBSYSTEM_DEVICE_ID; |
| 331 | params->PchSubSystemId = CONFIG_SUBSYSTEM_DEVICE_ID; |
| 332 | } |
| 333 | |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 334 | params->PchPmWolEnableOverride = config->WakeConfigWolEnableOverride; |
| 335 | params->PchPmPcieWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx; |
| 336 | params->PchPmDeepSxPol = config->PmConfigDeepSxPol; |
Duncan Laurie | 25c7d93 | 2017-02-17 17:16:43 -0800 | [diff] [blame] | 337 | params->PchPmSlpS0Enable = config->s0ix_enable; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 338 | params->PchPmSlpS3MinAssert = config->PmConfigSlpS3MinAssert; |
| 339 | params->PchPmSlpS4MinAssert = config->PmConfigSlpS4MinAssert; |
| 340 | params->PchPmSlpSusMinAssert = config->PmConfigSlpSusMinAssert; |
| 341 | params->PchPmSlpAMinAssert = config->PmConfigSlpAMinAssert; |
| 342 | params->PchPmLpcClockRun = config->PmConfigPciClockRun; |
| 343 | params->PchPmSlpStrchSusUp = config->PmConfigSlpStrchSusUp; |
| 344 | params->PchPmPwrBtnOverridePeriod = |
| 345 | config->PmConfigPwrBtnOverridePeriod; |
| 346 | params->PchPmPwrCycDur = config->PmConfigPwrCycDur; |
Rizwan Qureshi | 0da186c | 2017-02-23 14:43:39 +0530 | [diff] [blame] | 347 | |
| 348 | /* Indicate whether platform supports Voltage Margining */ |
| 349 | params->PchPmSlpS0VmEnable = config->PchPmSlpS0VmEnable; |
| 350 | |
Nico Huber | 44e89af | 2019-02-23 19:24:51 +0100 | [diff] [blame] | 351 | params->PchSirqEnable = config->serirq_mode != SERIRQ_OFF; |
| 352 | params->PchSirqMode = config->serirq_mode == SERIRQ_CONTINUOUS; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 353 | |
Martin Roth | c25c1eb | 2020-07-24 12:26:21 -0600 | [diff] [blame] | 354 | params->CpuConfig.Bits.SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT); |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 355 | |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 356 | for (i = 0; i < ARRAY_SIZE(config->i2c_voltage); i++) |
Aaron Durbin | ed14a4e | 2016-11-09 17:04:15 -0600 | [diff] [blame] | 357 | params->SerialIoI2cVoltage[i] = config->i2c_voltage[i]; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 358 | |
| 359 | for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++) |
| 360 | fill_vr_domain_config(params, i, &config->domain_vr_config[i]); |
| 361 | |
| 362 | /* Show SPI controller if enabled in devicetree.cb */ |
Kyösti Mälkki | 903b40a | 2019-07-03 07:25:59 +0300 | [diff] [blame] | 363 | dev = pcidev_path_on_root(PCH_DEVFN_SPI); |
Felix Singer | e104934 | 2020-08-11 06:34:15 +0200 | [diff] [blame] | 364 | params->ShowSpiController = dev && dev->enabled; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 365 | |
Duncan Laurie | f511695 | 2018-03-26 02:24:18 -0700 | [diff] [blame] | 366 | /* Enable xDCI controller if enabled in devicetree and allowed */ |
Kyösti Mälkki | 903b40a | 2019-07-03 07:25:59 +0300 | [diff] [blame] | 367 | dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); |
Angel Pons | c54dcf4 | 2019-08-30 22:14:18 +0200 | [diff] [blame] | 368 | if (dev) { |
| 369 | if (!xdci_can_enable()) |
| 370 | dev->enabled = 0; |
| 371 | params->XdciEnable = dev->enabled; |
| 372 | } else { |
| 373 | params->XdciEnable = 0; |
| 374 | } |
Duncan Laurie | f511695 | 2018-03-26 02:24:18 -0700 | [diff] [blame] | 375 | |
Maxim Polyakov | 03ddd19 | 2019-08-30 18:04:02 +0300 | [diff] [blame] | 376 | /* Enable or disable Gaussian Mixture Model in devicetree */ |
| 377 | dev = pcidev_path_on_root(SA_DEVFN_GMM); |
Felix Singer | e104934 | 2020-08-11 06:34:15 +0200 | [diff] [blame] | 378 | params->GmmEnable = dev && dev->enabled; |
Maxim Polyakov | 03ddd19 | 2019-08-30 18:04:02 +0300 | [diff] [blame] | 379 | |
Rizwan Qureshi | 6467014 | 2016-11-23 15:25:19 +0530 | [diff] [blame] | 380 | /* |
| 381 | * Send VR specific mailbox commands: |
| 382 | * 000b - no VR specific command sent |
| 383 | * 001b - VR mailbox command specifically for the MPS IMPV8 VR |
Lee Leahy | f4c4ab9 | 2017-03-16 17:08:03 -0700 | [diff] [blame] | 384 | * will be sent |
Rizwan Qureshi | 6467014 | 2016-11-23 15:25:19 +0530 | [diff] [blame] | 385 | * 010b - VR specific command sent for PS4 exit issue |
| 386 | * 100b - VR specific command sent for MPS VR decay issue |
| 387 | */ |
| 388 | params->SendVrMbxCmd1 = config->SendVrMbxCmd; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 389 | |
Rizwan Qureshi | b3e18c7 | 2017-09-25 17:35:15 +0530 | [diff] [blame] | 390 | /* |
| 391 | * Activates VR mailbox command for Intersil VR C-state issues. |
| 392 | * 0 - no mailbox command sent. |
| 393 | * 1 - VR mailbox command sent for IA/GT rails only. |
| 394 | * 2 - VR mailbox command sent for IA/GT/SA rails. |
| 395 | */ |
| 396 | params->IslVrCmd = config->IslVrCmd; |
| 397 | |
Duncan Laurie | b2aac85 | 2017-03-07 19:12:02 -0800 | [diff] [blame] | 398 | /* Acoustic Noise Mitigation */ |
| 399 | params->AcousticNoiseMitigation = config->AcousticNoiseMitigation; |
| 400 | params->SlowSlewRateForIa = config->SlowSlewRateForIa; |
| 401 | params->SlowSlewRateForGt = config->SlowSlewRateForGt; |
| 402 | params->SlowSlewRateForSa = config->SlowSlewRateForSa; |
| 403 | params->FastPkgCRampDisableIa = config->FastPkgCRampDisableIa; |
| 404 | params->FastPkgCRampDisableGt = config->FastPkgCRampDisableGt; |
| 405 | params->FastPkgCRampDisableSa = config->FastPkgCRampDisableSa; |
| 406 | |
Rizwan Qureshi | ffe5810 | 2017-02-10 15:58:24 +0530 | [diff] [blame] | 407 | /* Enable PMC XRAM read */ |
| 408 | tconfig->PchPmPmcReadDisable = config->PchPmPmcReadDisable; |
| 409 | |
Subrata Banik | 6b45ee4 | 2017-05-12 11:43:57 +0530 | [diff] [blame] | 410 | /* Enable/Disable EIST */ |
| 411 | tconfig->Eist = config->eist_enable; |
| 412 | |
marxwang | ec5a947 | 2017-12-11 14:57:49 +0800 | [diff] [blame] | 413 | /* Set TccActivationOffset */ |
| 414 | tconfig->TccActivationOffset = config->tcc_offset; |
| 415 | |
Angel Pons | 4ff63d3 | 2019-08-30 20:05:33 +0200 | [diff] [blame] | 416 | /* Already handled in coreboot code, so tell FSP to ignore UPDs */ |
| 417 | params->PchIoApicBdfValid = 0; |
| 418 | |
Nico Huber | 2afe4dc | 2017-09-19 09:36:03 +0200 | [diff] [blame] | 419 | /* Enable VT-d and X2APIC */ |
| 420 | if (!config->ignore_vtd && soc_is_vtd_capable()) { |
| 421 | params->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS; |
| 422 | params->VtdBaseAddress[1] = VTVC0_BASE_ADDRESS; |
| 423 | params->X2ApicOptOut = 0; |
| 424 | tconfig->VtdDisable = 0; |
Nico Huber | 2afe4dc | 2017-09-19 09:36:03 +0200 | [diff] [blame] | 425 | } |
| 426 | |
Michael Niewöhner | d60089b | 2019-10-26 10:44:33 +0200 | [diff] [blame] | 427 | dev = pcidev_path_on_root(SA_DEVFN_IGD); |
| 428 | if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled) |
| 429 | params->PeiGraphicsPeimInit = 1; |
| 430 | else |
| 431 | params->PeiGraphicsPeimInit = 0; |
| 432 | |
Benjamin Doron | bbb8123 | 2020-06-28 02:43:53 +0000 | [diff] [blame] | 433 | params->PavpEnable = CONFIG(PAVP); |
| 434 | |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 435 | soc_irq_settings(params); |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 436 | } |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 437 | |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 438 | /* Mainboard GPIO Configuration */ |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 439 | __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 440 | { |
| 441 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 442 | } |
Wim Vervoorn | d137150 | 2019-12-17 14:10:16 +0100 | [diff] [blame] | 443 | |
| 444 | /* Handle FSP logo params */ |
| 445 | const struct cbmem_entry *soc_load_logo(FSPS_UPD *supd) |
| 446 | { |
| 447 | return fsp_load_logo(&supd->FspsConfig.LogoPtr, &supd->FspsConfig.LogoSize); |
| 448 | } |