soc/intel: Replace uses of dev_find_slot()
To call dev_find_slot(0, xx) in romstage can produce
invalid results since PCI bus enumeration has not
been progressed yet.
Replace this with method that relies on bus topology
that walks the root bus only.
Change-Id: I2883610059bb9fa860bba01179e7d5c58cae00e5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index d179598..08f5d79 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -102,7 +102,7 @@
for (group = 0; group < pci_groups; group++) {
devfn0 = pcie_rp_group[group].devfn;
- func0 = dev_find_slot(0, devfn0);
+ func0 = pcidev_path_on_root(devfn0);
if (func0 == NULL)
continue;
@@ -119,7 +119,7 @@
*/
for (i = 1; i < pcie_rp_group[group].func_count;
i++, devfn += inc) {
- struct device *dev = dev_find_slot(0, devfn);
+ struct device *dev = pcidev_path_on_root(devfn);
if (dev == NULL || !dev->enabled)
continue;
@@ -354,7 +354,7 @@
}
/* If ISH is enabled, enable ISH elements */
- dev = dev_find_slot(0, PCH_DEVFN_ISH);
+ dev = pcidev_path_on_root(PCH_DEVFN_ISH);
if (dev)
params->PchIshEnable = dev->enabled;
else
@@ -433,11 +433,11 @@
fill_vr_domain_config(params, i, &config->domain_vr_config[i]);
/* Show SPI controller if enabled in devicetree.cb */
- dev = dev_find_slot(0, PCH_DEVFN_SPI);
+ dev = pcidev_path_on_root(PCH_DEVFN_SPI);
params->ShowSpiController = dev->enabled;
/* Enable xDCI controller if enabled in devicetree and allowed */
- dev = dev_find_slot(0, PCH_DEVFN_USBOTG);
+ dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
if (!xdci_can_enable())
dev->enabled = 0;
params->XdciEnable = dev->enabled;