Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 4 | * Copyright (C) 2016 Intel Corporation. |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 14 | */ |
| 15 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 16 | #include <chip.h> |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 17 | #include <bootstate.h> |
| 18 | #include <device/pci.h> |
| 19 | #include <fsp/api.h> |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 20 | #include <arch/acpi.h> |
| 21 | #include <chip.h> |
| 22 | #include <bootstate.h> |
| 23 | #include <console/console.h> |
| 24 | #include <device/device.h> |
| 25 | #include <device/pci.h> |
| 26 | #include <fsp/api.h> |
| 27 | #include <fsp/util.h> |
Brandon Breitenstein | c6ec8dd | 2016-11-17 12:23:04 -0800 | [diff] [blame^] | 28 | #include <romstage_handoff.h> |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 29 | #include <soc/acpi.h> |
| 30 | #include <soc/interrupt.h> |
| 31 | #include <soc/irq.h> |
| 32 | #include <soc/pci_devs.h> |
| 33 | #include <soc/ramstage.h> |
| 34 | #include <string.h> |
| 35 | |
| 36 | void soc_init_pre_device(void *chip_info) |
| 37 | { |
Brandon Breitenstein | c6ec8dd | 2016-11-17 12:23:04 -0800 | [diff] [blame^] | 38 | struct romstage_handoff *handoff; |
| 39 | |
| 40 | /* Get S3 status to pass to silicon init. */ |
| 41 | handoff = romstage_handoff_find_or_add(); |
| 42 | |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 43 | /* Perform silicon specific init. */ |
Brandon Breitenstein | c6ec8dd | 2016-11-17 12:23:04 -0800 | [diff] [blame^] | 44 | fsp_silicon_init(handoff->s3_resume); |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 45 | } |
| 46 | |
| 47 | static void pci_domain_set_resources(device_t dev) |
| 48 | { |
| 49 | assign_resources(dev->link_list); |
| 50 | } |
| 51 | |
| 52 | static struct device_operations pci_domain_ops = { |
| 53 | .read_resources = &pci_domain_read_resources, |
| 54 | .set_resources = &pci_domain_set_resources, |
| 55 | .scan_bus = &pci_domain_scan_bus, |
| 56 | .ops_pci_bus = &pci_bus_default_ops, |
| 57 | #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) |
| 58 | .acpi_name = &soc_acpi_name, |
| 59 | #endif |
| 60 | }; |
| 61 | |
| 62 | static struct device_operations cpu_bus_ops = { |
| 63 | .read_resources = DEVICE_NOOP, |
| 64 | .set_resources = DEVICE_NOOP, |
| 65 | .enable_resources = DEVICE_NOOP, |
| 66 | .init = &soc_init_cpus, |
| 67 | #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) |
| 68 | .acpi_fill_ssdt_generator = generate_cpu_entries, |
| 69 | #endif |
| 70 | }; |
| 71 | |
| 72 | static void soc_enable(device_t dev) |
| 73 | { |
| 74 | /* Set the operations if it is a special bus type */ |
| 75 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
| 76 | dev->ops = &pci_domain_ops; |
| 77 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
| 78 | dev->ops = &cpu_bus_ops; |
| 79 | } else if (dev->path.type == DEVICE_PATH_PCI) { |
| 80 | /* Handle PCH device enable */ |
| 81 | if (PCI_SLOT(dev->path.pci.devfn) > SA_DEV_SLOT_IGD && |
| 82 | (dev->ops == NULL || dev->ops->enable == NULL)) { |
| 83 | pch_enable_dev(dev); |
| 84 | } |
| 85 | } |
| 86 | } |
| 87 | |
| 88 | struct chip_operations soc_intel_skylake_ops = { |
| 89 | CHIP_NAME("Intel 6th Gen") |
| 90 | .enable_dev = &soc_enable, |
| 91 | .init = &soc_init_pre_device, |
| 92 | }; |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 93 | |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 94 | /* UPD parameters to be initialized before SiliconInit */ |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 95 | void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 96 | { |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 97 | FSP_S_CONFIG *params = &supd->FspsConfig; |
| 98 | FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig; |
| 99 | static struct soc_intel_skylake_config *config; |
| 100 | uintptr_t vbt_data = 0; |
| 101 | |
| 102 | int i; |
| 103 | |
| 104 | int is_s3_wakeup = acpi_is_wakeup_s3(); |
| 105 | |
| 106 | struct device *dev = SA_DEV_ROOT; |
| 107 | if (!dev || !dev->chip_info) { |
| 108 | printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); |
| 109 | return; |
| 110 | } |
| 111 | config = dev->chip_info; |
| 112 | |
| 113 | mainboard_silicon_init_params(params); |
| 114 | |
| 115 | /* Load VBT */ |
| 116 | if (!is_s3_wakeup) |
| 117 | vbt_data = fsp_load_vbt(); |
| 118 | |
| 119 | params->GraphicsConfigPtr = (u32) vbt_data; |
| 120 | |
| 121 | for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { |
| 122 | params->PortUsb20Enable[i] = |
| 123 | config->usb2_ports[i].enable; |
| 124 | params->Usb2AfePetxiset[i] = |
| 125 | config->usb2_ports[i].pre_emp_bias; |
| 126 | params->Usb2AfeTxiset[i] = |
| 127 | config->usb2_ports[i].tx_bias; |
| 128 | params->Usb2AfePredeemp[i] = |
| 129 | config->usb2_ports[i].tx_emp_enable; |
| 130 | params->Usb2AfePehalfbit[i] = |
| 131 | config->usb2_ports[i].pre_emp_bit; |
| 132 | } |
| 133 | |
| 134 | for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { |
| 135 | params->PortUsb30Enable[i] = config->usb3_ports[i].enable; |
| 136 | if (config->usb3_ports[i].tx_de_emp) { |
| 137 | params->Usb3HsioTxDeEmphEnable[i] = 1; |
| 138 | params->Usb3HsioTxDeEmph[i] = |
| 139 | config->usb3_ports[i].tx_de_emp; |
| 140 | } |
| 141 | if (config->usb3_ports[i].tx_downscale_amp) { |
| 142 | params->Usb3HsioTxDownscaleAmpEnable[i] = 1; |
| 143 | params->Usb3HsioTxDownscaleAmp[i] = |
| 144 | config->usb3_ports[i].tx_downscale_amp; |
| 145 | } |
| 146 | } |
| 147 | |
| 148 | memcpy(params->SataPortsEnable, config->SataPortsEnable, |
| 149 | sizeof(params->SataPortsEnable)); |
| 150 | memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, |
| 151 | sizeof(params->SataPortsDevSlp)); |
| 152 | memcpy(params->PcieRpClkReqSupport, config->PcieRpClkReqSupport, |
| 153 | sizeof(params->PcieRpClkReqSupport)); |
| 154 | memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber, |
| 155 | sizeof(params->PcieRpClkReqNumber)); |
| 156 | |
| 157 | memcpy(params->SerialIoDevMode, config->SerialIoDevMode, |
| 158 | sizeof(params->SerialIoDevMode)); |
| 159 | |
| 160 | params->PchCio2Enable = config->Cio2Enable; |
| 161 | params->Heci3Enabled = config->Heci3Enabled; |
| 162 | |
| 163 | params->LogoPtr = config->LogoPtr; |
| 164 | params->LogoSize = config->LogoSize; |
| 165 | |
| 166 | params->CpuConfig.Bits.VmxEnable = config->VmxEnable; |
| 167 | |
| 168 | params->PchPmWoWlanEnable = config->PchPmWoWlanEnable; |
| 169 | params->PchPmWoWlanDeepSxEnable = config->PchPmWoWlanDeepSxEnable; |
| 170 | params->PchPmLanWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx; |
| 171 | |
| 172 | params->PchLanEnable = config->EnableLan; |
| 173 | params->PchCio2Enable = config->Cio2Enable; |
| 174 | params->SataSalpSupport = config->SataSalpSupport; |
| 175 | params->SsicPortEnable = config->SsicPortEnable; |
| 176 | params->ScsEmmcEnabled = config->ScsEmmcEnabled; |
| 177 | params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; |
| 178 | params->ScsSdCardEnabled = config->ScsSdCardEnabled; |
| 179 | params->PchIshEnable = config->IshEnable; |
| 180 | params->PchHdaEnable = config->EnableAzalia; |
| 181 | params->PchHdaIoBufferOwnership = config->IoBufferOwnership; |
| 182 | params->PchHdaDspEnable = config->DspEnable; |
| 183 | params->XdciEnable = config->XdciEnable; |
| 184 | params->Device4Enable = config->Device4Enable; |
| 185 | params->SataEnable = config->EnableSata; |
| 186 | params->SataMode = config->SataMode; |
| 187 | tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; |
| 188 | tconfig->PchLockDownBiosInterface = config->LockDownConfigBiosInterface; |
| 189 | tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock; |
| 190 | params->PchLockDownBiosLock = config->LockDownConfigBiosLock; |
| 191 | params->PchLockDownSpiEiss = config->LockDownConfigSpiEiss; |
| 192 | params->PchSubSystemVendorId = config->PchConfigSubSystemVendorId; |
| 193 | params->PchSubSystemId = config->PchConfigSubSystemId; |
| 194 | params->PchPmWolEnableOverride = config->WakeConfigWolEnableOverride; |
| 195 | params->PchPmPcieWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx; |
| 196 | params->PchPmDeepSxPol = config->PmConfigDeepSxPol; |
| 197 | params->PchPmSlpS3MinAssert = config->PmConfigSlpS3MinAssert; |
| 198 | params->PchPmSlpS4MinAssert = config->PmConfigSlpS4MinAssert; |
| 199 | params->PchPmSlpSusMinAssert = config->PmConfigSlpSusMinAssert; |
| 200 | params->PchPmSlpAMinAssert = config->PmConfigSlpAMinAssert; |
| 201 | params->PchPmLpcClockRun = config->PmConfigPciClockRun; |
| 202 | params->PchPmSlpStrchSusUp = config->PmConfigSlpStrchSusUp; |
| 203 | params->PchPmPwrBtnOverridePeriod = |
| 204 | config->PmConfigPwrBtnOverridePeriod; |
| 205 | params->PchPmPwrCycDur = config->PmConfigPwrCycDur; |
| 206 | params->PchSirqEnable = config->SerialIrqConfigSirqEnable; |
| 207 | params->PchSirqMode = config->SerialIrqConfigSirqMode; |
| 208 | |
| 209 | params->CpuConfig.Bits.SkipMpInit = config->FspSkipMpInit; |
| 210 | |
| 211 | for (i = 0; i < ARRAY_SIZE(config->i2c); i++) |
Aaron Durbin | ed14a4e | 2016-11-09 17:04:15 -0600 | [diff] [blame] | 212 | params->SerialIoI2cVoltage[i] = config->i2c_voltage[i]; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 213 | |
| 214 | for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++) |
| 215 | fill_vr_domain_config(params, i, &config->domain_vr_config[i]); |
| 216 | |
| 217 | /* Show SPI controller if enabled in devicetree.cb */ |
| 218 | dev = dev_find_slot(0, PCH_DEVFN_SPI); |
| 219 | params->ShowSpiController = dev->enabled; |
| 220 | |
| 221 | params->SendVrMbxCmd = config->SendVrMbxCmd; |
| 222 | |
| 223 | soc_irq_settings(params); |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 224 | } |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 225 | |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 226 | struct pci_operations soc_pci_ops = { |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 227 | .set_subsystem = &pci_dev_set_subsystem |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 228 | }; |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 229 | |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 230 | /* Mainboard GPIO Configuration */ |
| 231 | __attribute__((weak)) void mainboard_silicon_init_params(FSP_S_CONFIG *params) |
| 232 | { |
| 233 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 234 | } |