commit cf32fd172928467ac5bbd4fb372b71230c81cf12
author Subrata Banik <subrata.banik@intel.com> Wed Dec 19 18:02:17 2018 +0530
committer Subrata Banik <subrata.banik@intel.com> Sun Mar 24 04:01:11 2019 +0000
tree 9680154700a8d442e9f41d271ac208a6e28ecedf
parent 10f5ccf9cb26e58aaaf7d77813bf43b235eea4af

soc/intel/common: Remove common chip config use_fsp_mp_init

This patch ensures to make use of common MP Init Kconfig to
choose desire method to peform MP initialization for platform.

Change-Id: I4ee51276026748e8daf154f89e57095e8fe50280
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/soc/intel/skylake/chip_fsp20.c

diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 15eb6b2..c16a913 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -27,6 +27,7 @@
 #include <intelblocks/chip.h>
 #include <intelblocks/itss.h>
 #include <intelblocks/lpc_lib.h>
+#include <intelblocks/mp_init.h>
 #include <intelblocks/xdci.h>
 #include <intelpch/lockdown.h>
 #include <romstage_handoff.h>
@@ -422,7 +423,7 @@
 	params->PchSirqEnable = config->serirq_mode != SERIRQ_OFF;
 	params->PchSirqMode = config->serirq_mode == SERIRQ_CONTINUOUS;
 
-	params->CpuConfig.Bits.SkipMpInit = !chip_get_fsp_mp_init();
+	params->CpuConfig.Bits.SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
 
 	for (i = 0; i < ARRAY_SIZE(config->i2c_voltage); i++)
 		params->SerialIoI2cVoltage[i] = config->i2c_voltage[i];