Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2 | |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 3 | #include <cbmem.h> |
Elyes HAOUAS | 5db9871 | 2019-04-21 18:50:34 +0200 | [diff] [blame] | 4 | #include <cf9_reset.h> |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 5 | #include <console/console.h> |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 6 | #include <device/pci_def.h> |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 7 | #include <device/pci_ops.h> |
| 8 | #include <device/pci.h> |
Kyösti Mälkki | cbf9571 | 2020-01-05 08:05:45 +0200 | [diff] [blame] | 9 | #include <option.h> |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 10 | #include <romstage_handoff.h> |
Elyes HAOUAS | 51401c3 | 2019-05-15 21:09:30 +0200 | [diff] [blame] | 11 | #include <types.h> |
| 12 | |
| 13 | #include "i945.h" |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 14 | |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 15 | int i945_silicon_revision(void) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 16 | { |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 17 | return pci_read_config8(HOST_BRIDGE, PCI_CLASS_REVISION); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 18 | } |
| 19 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 20 | static void i945m_detect_chipset(void) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 21 | { |
| 22 | u8 reg8; |
| 23 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 24 | printk(BIOS_INFO, "\n"); |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 25 | reg8 = (pci_read_config8(HOST_BRIDGE, 0xe7) & 0x70) >> 4; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 26 | switch (reg8) { |
| 27 | case 1: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 28 | printk(BIOS_INFO, "Mobile Intel(R) 82945GM/GME Express"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 29 | break; |
| 30 | case 2: |
Stefan Reinauer | 7981b94 | 2011-04-01 22:33:25 +0200 | [diff] [blame] | 31 | printk(BIOS_INFO, "Mobile Intel(R) 82945GMS/GU/GSE Express"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 32 | break; |
| 33 | case 3: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 34 | printk(BIOS_INFO, "Mobile Intel(R) 82945PM Express"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 35 | break; |
| 36 | case 5: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 37 | printk(BIOS_INFO, "Intel(R) 82945GT Express"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 38 | break; |
| 39 | case 6: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 40 | printk(BIOS_INFO, "Mobile Intel(R) 82943/82940GML Express"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 41 | break; |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 42 | default: /* Others reserved. */ |
| 43 | printk(BIOS_INFO, "Unknown (%02x)", reg8); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 44 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 45 | printk(BIOS_INFO, " Chipset\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 46 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 47 | printk(BIOS_DEBUG, "(G)MCH capable of up to FSB "); |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 48 | reg8 = (pci_read_config8(HOST_BRIDGE, 0xe3) & 0xe0) >> 5; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 49 | switch (reg8) { |
| 50 | case 2: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 51 | printk(BIOS_DEBUG, "800 MHz"); /* According to 965 spec */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 52 | break; |
| 53 | case 3: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 54 | printk(BIOS_DEBUG, "667 MHz"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 55 | break; |
| 56 | case 4: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 57 | printk(BIOS_DEBUG, "533 MHz"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 58 | break; |
| 59 | default: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 60 | printk(BIOS_DEBUG, "N/A MHz (%02x)", reg8); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 61 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 62 | printk(BIOS_DEBUG, "\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 63 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 64 | printk(BIOS_DEBUG, "(G)MCH capable of "); |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 65 | reg8 = (pci_read_config8(HOST_BRIDGE, 0xe4) & 0x07); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 66 | switch (reg8) { |
| 67 | case 2: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 68 | printk(BIOS_DEBUG, "up to DDR2-667"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 69 | break; |
| 70 | case 3: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 71 | printk(BIOS_DEBUG, "up to DDR2-533"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 72 | break; |
| 73 | case 4: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 74 | printk(BIOS_DEBUG, "DDR2-400"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 75 | break; |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 76 | default: /* Others reserved. */ |
| 77 | printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 78 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 79 | printk(BIOS_DEBUG, "\n"); |
Elyes HAOUAS | 6372a0e | 2016-10-30 18:39:53 +0100 | [diff] [blame] | 80 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 81 | if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) |
Elyes HAOUAS | 6372a0e | 2016-10-30 18:39:53 +0100 | [diff] [blame] | 82 | printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 83 | } |
| 84 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 85 | static void i945_detect_chipset(void) |
| 86 | { |
| 87 | u8 reg8; |
| 88 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 89 | printk(BIOS_INFO, "\nIntel(R) "); |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 90 | |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 91 | reg8 = ((pci_read_config8(HOST_BRIDGE, 0xe7) >> 5) & 4) |
| 92 | | ((pci_read_config8(HOST_BRIDGE, 0xe4) >> 4) & 3); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 93 | switch (reg8) { |
| 94 | case 0: |
| 95 | case 1: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 96 | printk(BIOS_INFO, "82945G"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 97 | break; |
| 98 | case 2: |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 99 | case 3: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 100 | printk(BIOS_INFO, "82945P"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 101 | break; |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 102 | case 4: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 103 | printk(BIOS_INFO, "82945GC"); |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 104 | break; |
| 105 | case 5: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 106 | printk(BIOS_INFO, "82945GZ"); |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 107 | break; |
| 108 | case 6: |
| 109 | case 7: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 110 | printk(BIOS_INFO, "82945PL"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 111 | break; |
| 112 | default: |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 113 | break; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 114 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 115 | printk(BIOS_INFO, " Chipset\n"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 116 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 117 | printk(BIOS_DEBUG, "(G)MCH capable of "); |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 118 | reg8 = (pci_read_config8(HOST_BRIDGE, 0xe4) & 0x07); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 119 | switch (reg8) { |
| 120 | case 0: |
Elyes HAOUAS | 5db9450 | 2016-10-30 18:30:21 +0100 | [diff] [blame] | 121 | case 2: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 122 | printk(BIOS_DEBUG, "up to DDR2-667"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 123 | break; |
| 124 | case 3: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 125 | printk(BIOS_DEBUG, "up to DDR2-533"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 126 | break; |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 127 | default: /* Others reserved. */ |
| 128 | printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 129 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 130 | printk(BIOS_DEBUG, "\n"); |
Elyes HAOUAS | 6372a0e | 2016-10-30 18:39:53 +0100 | [diff] [blame] | 131 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 132 | if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) |
Elyes HAOUAS | 6372a0e | 2016-10-30 18:39:53 +0100 | [diff] [blame] | 133 | printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 134 | } |
| 135 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 136 | static void i945_setup_bars(void) |
| 137 | { |
Arthur Heymans | 874a8f9 | 2016-05-19 16:06:09 +0200 | [diff] [blame] | 138 | u8 reg8, gfxsize; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 139 | |
| 140 | /* As of now, we don't have all the A0 workarounds implemented */ |
| 141 | if (i945_silicon_revision() == 0) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 142 | printk(BIOS_INFO, "Warning: i945 silicon revision A0 might not work correctly.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 143 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 144 | printk(BIOS_DEBUG, "Setting up static northbridge registers..."); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 145 | /* Set up all hardcoded northbridge BARs */ |
Angel Pons | 4299cb4 | 2021-01-20 12:32:22 +0100 | [diff] [blame] | 146 | pci_write_config32(HOST_BRIDGE, EPBAR, CONFIG_FIXED_EPBAR_MMIO_BASE | 1); |
| 147 | pci_write_config32(HOST_BRIDGE, MCHBAR, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1); |
| 148 | pci_write_config32(HOST_BRIDGE, DMIBAR, CONFIG_FIXED_DMIBAR_MMIO_BASE | 1); |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 149 | pci_write_config32(HOST_BRIDGE, X60BAR, DEFAULT_X60BAR | 1); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 150 | |
Elyes HAOUAS | 2119d0b | 2020-02-16 10:01:33 +0100 | [diff] [blame] | 151 | /* vram size from CMOS option */ |
Angel Pons | 88dcb31 | 2021-04-26 17:10:28 +0200 | [diff] [blame] | 152 | gfxsize = get_uint_option("gfx_uma_size", 2); /* 2 for 8MB */ |
Arthur Heymans | 874a8f9 | 2016-05-19 16:06:09 +0200 | [diff] [blame] | 153 | /* make sure no invalid setting is used */ |
| 154 | if (gfxsize > 6) |
| 155 | gfxsize = 2; |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 156 | pci_write_config16(HOST_BRIDGE, GGC, ((gfxsize + 1) << 4)); |
Arthur Heymans | d522db0 | 2018-08-06 15:50:54 +0200 | [diff] [blame] | 157 | /* TSEG 2M, This amount can easily be covered by SMRR MTRR's, |
| 158 | which requires to have TSEG_BASE aligned to TSEG_SIZE. */ |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 159 | pci_update_config8(HOST_BRIDGE, ESMRAMC, ~0x07, (1 << 1) | (1 << 0)); |
Arthur Heymans | e07df9d | 2018-04-09 22:03:21 +0200 | [diff] [blame] | 160 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 161 | /* Set C0000-FFFFF to access RAM on both reads and writes */ |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 162 | pci_write_config8(HOST_BRIDGE, PAM0, 0x30); |
| 163 | pci_write_config8(HOST_BRIDGE, PAM1, 0x33); |
| 164 | pci_write_config8(HOST_BRIDGE, PAM2, 0x33); |
| 165 | pci_write_config8(HOST_BRIDGE, PAM3, 0x33); |
| 166 | pci_write_config8(HOST_BRIDGE, PAM4, 0x33); |
| 167 | pci_write_config8(HOST_BRIDGE, PAM5, 0x33); |
| 168 | pci_write_config8(HOST_BRIDGE, PAM6, 0x33); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 169 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 170 | printk(BIOS_DEBUG, " done.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 171 | |
| 172 | /* Wait for MCH BAR to come up */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 173 | printk(BIOS_DEBUG, "Waiting for MCHBAR to come up..."); |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 174 | if ((pci_read_config32(HOST_BRIDGE, 0xe4) & 0x20000) == 0x00) { /* Bit 49 of CAPID0 */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 175 | do { |
| 176 | reg8 = *(volatile u8 *)0xfed40000; |
| 177 | } while (!(reg8 & 0x80)); |
| 178 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 179 | printk(BIOS_DEBUG, "ok\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 180 | } |
| 181 | |
| 182 | static void i945_setup_egress_port(void) |
| 183 | { |
| 184 | u32 reg32; |
| 185 | u32 timeout; |
| 186 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 187 | printk(BIOS_DEBUG, "Setting up Egress Port RCRB\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 188 | |
| 189 | /* Egress Port Virtual Channel 0 Configuration */ |
| 190 | |
| 191 | /* map only TC0 to VC0 */ |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 192 | reg32 = epbar_read32(EPVC0RCTL); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 193 | reg32 &= 0xffffff01; |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 194 | epbar_write32(EPVC0RCTL, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 195 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 196 | reg32 = epbar_read32(EPPVCCAP1); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 197 | reg32 &= ~(7 << 0); |
| 198 | reg32 |= 1; |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 199 | epbar_write32(EPPVCCAP1, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 200 | |
| 201 | /* Egress Port Virtual Channel 1 Configuration */ |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 202 | reg32 = epbar_read32(0x2c); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 203 | reg32 &= 0xffffff00; |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 204 | if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 205 | if ((mchbar_read32(CLKCFG) & 7) == 0) |
Elyes HAOUAS | f7acdf8 | 2016-10-31 18:55:04 +0100 | [diff] [blame] | 206 | reg32 |= 0x1a; /* 1067MHz */ |
| 207 | } |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 208 | if ((mchbar_read32(CLKCFG) & 7) == 1) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 209 | reg32 |= 0x0d; /* 533MHz */ |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 210 | if ((mchbar_read32(CLKCFG) & 7) == 2) |
Elyes HAOUAS | f7acdf8 | 2016-10-31 18:55:04 +0100 | [diff] [blame] | 211 | reg32 |= 0x14; /* 800MHz */ |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 212 | if ((mchbar_read32(CLKCFG) & 7) == 3) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 213 | reg32 |= 0x10; /* 667MHz */ |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 214 | epbar_write32(0x2c, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 215 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 216 | epbar_write32(EPVC1MTS, 0x0a0a0a0a); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 217 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 218 | reg32 = epbar_read32(EPVC1RCAP); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 219 | reg32 &= ~(0x7f << 16); |
| 220 | reg32 |= (0x0a << 16); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 221 | epbar_write32(EPVC1RCAP, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 222 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 223 | if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 224 | if ((mchbar_read32(CLKCFG) & 7) == 0) { /* 1067MHz */ |
| 225 | epbar_write32(EPVC1IST + 0, 0x01380138); |
| 226 | epbar_write32(EPVC1IST + 4, 0x01380138); |
Elyes HAOUAS | f7acdf8 | 2016-10-31 18:55:04 +0100 | [diff] [blame] | 227 | } |
| 228 | } |
| 229 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 230 | if ((mchbar_read32(CLKCFG) & 7) == 1) { /* 533MHz */ |
| 231 | epbar_write32(EPVC1IST + 0, 0x009c009c); |
| 232 | epbar_write32(EPVC1IST + 4, 0x009c009c); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 233 | } |
| 234 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 235 | if ((mchbar_read32(CLKCFG) & 7) == 2) { /* 800MHz */ |
| 236 | epbar_write32(EPVC1IST + 0, 0x00f000f0); |
| 237 | epbar_write32(EPVC1IST + 4, 0x00f000f0); |
Elyes HAOUAS | f7acdf8 | 2016-10-31 18:55:04 +0100 | [diff] [blame] | 238 | } |
| 239 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 240 | if ((mchbar_read32(CLKCFG) & 7) == 3) { /* 667MHz */ |
| 241 | epbar_write32(EPVC1IST + 0, 0x00c000c0); |
| 242 | epbar_write32(EPVC1IST + 4, 0x00c000c0); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 243 | } |
| 244 | |
| 245 | /* Is internal graphics enabled? */ |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 246 | if (pci_read_config8(HOST_BRIDGE, DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 247 | mchbar_setbits32(MMARB1, 1 << 17); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 248 | |
| 249 | /* Assign Virtual Channel ID 1 to VC1 */ |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 250 | reg32 = epbar_read32(EPVC1RCTL); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 251 | reg32 &= ~(7 << 24); |
| 252 | reg32 |= (1 << 24); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 253 | epbar_write32(EPVC1RCTL, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 254 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 255 | reg32 = epbar_read32(EPVC1RCTL); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 256 | reg32 &= 0xffffff01; |
| 257 | reg32 |= (1 << 7); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 258 | epbar_write32(EPVC1RCTL, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 259 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 260 | epbar_write32(PORTARB + 0x00, 0x01000001); |
| 261 | epbar_write32(PORTARB + 0x04, 0x00040000); |
| 262 | epbar_write32(PORTARB + 0x08, 0x00001000); |
| 263 | epbar_write32(PORTARB + 0x0c, 0x00000040); |
| 264 | epbar_write32(PORTARB + 0x10, 0x01000001); |
| 265 | epbar_write32(PORTARB + 0x14, 0x00040000); |
| 266 | epbar_write32(PORTARB + 0x18, 0x00001000); |
| 267 | epbar_write32(PORTARB + 0x1c, 0x00000040); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 268 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 269 | epbar_setbits32(EPVC1RCTL, 1 << 16); |
| 270 | epbar_setbits32(EPVC1RCTL, 1 << 16); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 271 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 272 | printk(BIOS_DEBUG, "Loading port arbitration table ..."); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 273 | /* Loop until bit 0 becomes 0 */ |
| 274 | timeout = 0x7fffff; |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 275 | while ((epbar_read16(EPVC1RSTS) & (1 << 0)) && --timeout) |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 276 | ; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 277 | if (!timeout) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 278 | printk(BIOS_DEBUG, "timeout!\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 279 | else |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 280 | printk(BIOS_DEBUG, "ok\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 281 | |
| 282 | /* Now enable VC1 */ |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 283 | epbar_setbits32(EPVC1RCTL, 1 << 31); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 284 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 285 | printk(BIOS_DEBUG, "Wait for VC1 negotiation ..."); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 286 | /* Wait for VC1 negotiation pending */ |
| 287 | timeout = 0x7fff; |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 288 | while ((epbar_read16(EPVC1RSTS) & (1 << 1)) && --timeout) |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 289 | ; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 290 | if (!timeout) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 291 | printk(BIOS_DEBUG, "timeout!\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 292 | else |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 293 | printk(BIOS_DEBUG, "ok\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 294 | |
| 295 | } |
| 296 | |
| 297 | static void ich7_setup_dmi_rcrb(void) |
| 298 | { |
| 299 | u16 reg16; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 300 | u32 reg32; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 301 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 302 | reg16 = RCBA16(LCTL); |
| 303 | reg16 &= ~(3 << 0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 304 | reg16 |= 3; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 305 | RCBA16(LCTL) = reg16; |
| 306 | |
| 307 | RCBA32(V0CTL) = 0x80000001; |
| 308 | RCBA32(V1CAP) = 0x03128010; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 309 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 310 | pci_write_config16(PCI_DEV(0, 0x1c, 0), 0x42, 0x0141); |
| 311 | pci_write_config16(PCI_DEV(0, 0x1c, 4), 0x42, 0x0141); |
| 312 | pci_write_config16(PCI_DEV(0, 0x1c, 5), 0x42, 0x0141); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 313 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 314 | pci_write_config32(PCI_DEV(0, 0x1c, 4), 0x54, 0x00480ce0); |
| 315 | pci_write_config32(PCI_DEV(0, 0x1c, 5), 0x54, 0x00500ce0); |
| 316 | |
| 317 | reg32 = RCBA32(V1CTL); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 318 | reg32 &= ~((0x7f << 1) | (7 << 17) | (7 << 24)); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 319 | reg32 |= (0x40 << 1) | (4 << 17) | (1 << 24) | (1 << 31); |
| 320 | RCBA32(V1CTL) = reg32; |
| 321 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 322 | RCBA32(LCAP) |= (3 << 10); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 323 | } |
| 324 | |
| 325 | static void i945_setup_dmi_rcrb(void) |
| 326 | { |
| 327 | u32 reg32; |
| 328 | u32 timeout; |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 329 | int activate_aspm = 1; /* hardcode ASPM for now */ |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 330 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 331 | printk(BIOS_DEBUG, "Setting up DMI RCRB\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 332 | |
| 333 | /* Virtual Channel 0 Configuration */ |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 334 | reg32 = dmibar_read32(DMIVC0RCTL0); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 335 | reg32 &= 0xffffff01; |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 336 | dmibar_write32(DMIVC0RCTL0, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 337 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 338 | reg32 = dmibar_read32(DMIPVCCAP1); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 339 | reg32 &= ~(7 << 0); |
| 340 | reg32 |= 1; |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 341 | dmibar_write32(DMIPVCCAP1, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 342 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 343 | reg32 = dmibar_read32(DMIVC1RCTL); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 344 | reg32 &= ~(7 << 24); |
| 345 | reg32 |= (1 << 24); /* NOTE: This ID must match ICH7 side */ |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 346 | dmibar_write32(DMIVC1RCTL, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 347 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 348 | reg32 = dmibar_read32(DMIVC1RCTL); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 349 | reg32 &= 0xffffff01; |
| 350 | reg32 |= (1 << 7); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 351 | dmibar_write32(DMIVC1RCTL, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 352 | |
| 353 | /* Now enable VC1 */ |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 354 | dmibar_setbits32(DMIVC1RCTL, 1 << 31); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 355 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 356 | printk(BIOS_DEBUG, "Wait for VC1 negotiation ..."); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 357 | /* Wait for VC1 negotiation pending */ |
| 358 | timeout = 0x7ffff; |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 359 | while ((dmibar_read16(DMIVC1RSTS) & (1 << 1)) && --timeout) |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 360 | ; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 361 | if (!timeout) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 362 | printk(BIOS_DEBUG, "timeout!\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 363 | else |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 364 | printk(BIOS_DEBUG, "done..\n"); |
Angel Pons | 81c9c27 | 2020-07-07 23:19:38 +0200 | [diff] [blame] | 365 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 366 | /* Enable Active State Power Management (ASPM) L0 state */ |
| 367 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 368 | reg32 = dmibar_read32(DMILCAP); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 369 | reg32 &= ~(7 << 12); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 370 | reg32 |= (2 << 12); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 371 | |
| 372 | reg32 &= ~(7 << 15); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 373 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 374 | reg32 |= (2 << 15); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 375 | dmibar_write32(DMILCAP, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 376 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 377 | reg32 = dmibar_read32(DMICC); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 378 | reg32 &= 0x00ffffff; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 379 | reg32 &= ~(3 << 0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 380 | reg32 |= (1 << 0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 381 | reg32 &= ~(3 << 20); |
| 382 | reg32 |= (1 << 20); |
| 383 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 384 | dmibar_write32(DMICC, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 385 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 386 | if (activate_aspm) |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 387 | dmibar_setbits32(DMILCTL, 3 << 0); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 388 | |
| 389 | /* Last but not least, some additional steps */ |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 390 | reg32 = mchbar_read32(FSBSNPCTL); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 391 | reg32 &= ~(0xff << 2); |
| 392 | reg32 |= (0xaa << 2); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 393 | mchbar_write32(FSBSNPCTL, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 394 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 395 | dmibar_write32(0x2c, 0x86000040); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 396 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 397 | reg32 = dmibar_read32(0x204); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 398 | reg32 &= ~0x3ff; |
| 399 | #if 1 |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 400 | reg32 |= 0x13f; /* for x4 DMI only */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 401 | #else |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 402 | reg32 |= 0x1e4; /* for x2 DMI only */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 403 | #endif |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 404 | dmibar_write32(0x204, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 405 | |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 406 | if (pci_read_config8(HOST_BRIDGE, DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 407 | printk(BIOS_DEBUG, "Internal graphics: enabled\n"); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 408 | dmibar_setbits32(0x200, 1 << 21); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 409 | } else { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 410 | printk(BIOS_DEBUG, "Internal graphics: disabled\n"); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 411 | dmibar_clrbits32(0x200, 1 << 21); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 412 | } |
| 413 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 414 | reg32 = dmibar_read32(0x204); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 415 | reg32 &= ~((1 << 11) | (1 << 10)); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 416 | dmibar_write32(0x204, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 417 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 418 | reg32 = dmibar_read32(0x204); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 419 | reg32 &= ~(0xff << 12); |
| 420 | reg32 |= (0x0d << 12); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 421 | dmibar_write32(0x204, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 422 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 423 | dmibar_setbits32(DMICTL1, 3 << 24); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 424 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 425 | reg32 = dmibar_read32(0x200); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 426 | reg32 &= ~(0x3 << 26); |
| 427 | reg32 |= (0x02 << 26); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 428 | dmibar_write32(0x200, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 429 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 430 | dmibar_clrbits32(DMIDRCCFG, 1 << 31); |
| 431 | dmibar_setbits32(DMICTL2, 1 << 31); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 432 | |
| 433 | if (i945_silicon_revision() >= 3) { |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 434 | reg32 = dmibar_read32(0xec0); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 435 | reg32 &= 0x0fffffff; |
| 436 | reg32 |= (2 << 28); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 437 | dmibar_write32(0xec0, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 438 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 439 | reg32 = dmibar_read32(0xed4); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 440 | reg32 &= 0x0fffffff; |
| 441 | reg32 |= (2 << 28); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 442 | dmibar_write32(0xed4, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 443 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 444 | reg32 = dmibar_read32(0xee8); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 445 | reg32 &= 0x0fffffff; |
| 446 | reg32 |= (2 << 28); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 447 | dmibar_write32(0xee8, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 448 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 449 | reg32 = dmibar_read32(0xefc); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 450 | reg32 &= 0x0fffffff; |
| 451 | reg32 |= (2 << 28); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 452 | dmibar_write32(0xefc, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 453 | } |
| 454 | |
| 455 | /* wait for bit toggle to 0 */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 456 | printk(BIOS_DEBUG, "Waiting for DMI hardware..."); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 457 | timeout = 0x7fffff; |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 458 | while ((dmibar_read8(0x32) & (1 << 1)) && --timeout) |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 459 | ; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 460 | if (!timeout) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 461 | printk(BIOS_DEBUG, "timeout!\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 462 | else |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 463 | printk(BIOS_DEBUG, "ok\n"); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 464 | |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 465 | /* Clear Error Status Bits! */ |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 466 | dmibar_write32(0x1c4, 0xffffffff); |
| 467 | dmibar_write32(0x1d0, 0xffffffff); |
| 468 | dmibar_write32(0x228, 0xffffffff); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 469 | |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 470 | /* Program Read-Only Write-Once Registers */ |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 471 | dmibar_setbits32(0x308, 0); |
| 472 | dmibar_setbits32(0x314, 0); |
| 473 | dmibar_setbits32(0x324, 0); |
| 474 | dmibar_setbits32(0x328, 0); |
| 475 | dmibar_setbits32(0x334, 0); |
| 476 | dmibar_setbits32(0x338, 0); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 477 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 478 | if (i945_silicon_revision() == 1 && (mchbar_read8(DFT_STRAP1) & (1 << 5))) { |
| 479 | if ((mchbar_read32(0x214) & 0xf) != 0x3) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 480 | printk(BIOS_INFO, "DMI link requires A1 stepping workaround. Rebooting.\n"); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 481 | reg32 = dmibar_read32(0x224); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 482 | reg32 &= ~(7 << 0); |
| 483 | reg32 |= (3 << 0); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 484 | dmibar_write32(0x224, reg32); |
Elyes HAOUAS | 5db9871 | 2019-04-21 18:50:34 +0200 | [diff] [blame] | 485 | system_reset(); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 486 | } |
| 487 | } |
| 488 | } |
| 489 | |
| 490 | static void i945_setup_pci_express_x16(void) |
| 491 | { |
| 492 | u32 timeout; |
| 493 | u32 reg32; |
| 494 | u16 reg16; |
Elyes HAOUAS | 961658f | 2020-04-06 09:42:21 +0200 | [diff] [blame] | 495 | const pci_devfn_t p2peg = PCI_DEV(0, 0x01, 0); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 496 | |
Kyösti Mälkki | 2647b6f | 2019-09-29 07:03:55 +0300 | [diff] [blame] | 497 | u8 tmp_secondary = 0x0a; |
Elyes HAOUAS | 961658f | 2020-04-06 09:42:21 +0200 | [diff] [blame] | 498 | const pci_devfn_t peg_plugin = PCI_DEV(tmp_secondary, 0, 0); |
Kyösti Mälkki | 2647b6f | 2019-09-29 07:03:55 +0300 | [diff] [blame] | 499 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 500 | printk(BIOS_DEBUG, "Enabling PCI Express x16 Link\n"); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 501 | |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 502 | pci_or_config16(HOST_BRIDGE, DEVEN, DEVEN_D1F0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 503 | |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 504 | pci_and_config32(p2peg, PEGCC, ~(1 << 8)); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 505 | |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 506 | /* We have no success with querying the usual PCIe registers |
| 507 | * for link setup success on the i945. Hence we assign a temporary |
| 508 | * PCI bus 0x0a and check whether we find a device on 0:a.0 |
| 509 | */ |
| 510 | |
Kyösti Mälkki | ad787e1 | 2019-09-30 04:14:19 +0300 | [diff] [blame] | 511 | /* Force PCIRST# */ |
| 512 | pci_s_assert_secondary_reset(p2peg); |
| 513 | pci_s_deassert_secondary_reset(p2peg); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 514 | |
Kyösti Mälkki | 444d2af | 2019-09-29 07:03:31 +0300 | [diff] [blame] | 515 | reg16 = pci_read_config16(p2peg, SLOTSTS); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 516 | printk(BIOS_DEBUG, "SLOTSTS: %04x\n", reg16); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 517 | if (!(reg16 & 0x48)) |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 518 | goto disable_pciexpress_x16_link; |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 519 | reg16 |= (1 << 4) | (1 << 0); |
Kyösti Mälkki | 444d2af | 2019-09-29 07:03:31 +0300 | [diff] [blame] | 520 | pci_write_config16(p2peg, SLOTSTS, reg16); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 521 | |
Kyösti Mälkki | ad787e1 | 2019-09-30 04:14:19 +0300 | [diff] [blame] | 522 | pci_s_bridge_set_secondary(p2peg, tmp_secondary); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 523 | |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 524 | pci_and_config32(p2peg, 0x224, ~(1 << 8)); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 525 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 526 | mchbar_clrbits16(UPMC1, 1 << 5 | 1 << 0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 527 | |
Martin Roth | 128c104 | 2016-11-18 09:29:03 -0700 | [diff] [blame] | 528 | /* Initialize PEG_CAP */ |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 529 | pci_or_config16(p2peg, PEG_CAP, 1 << 8); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 530 | |
| 531 | /* Setup SLOTCAP */ |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 532 | /* TODO: These values are mainboard dependent and should be set from devicetree.cb. |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 533 | */ |
| 534 | /* NOTE: SLOTCAP becomes RO after the first write! */ |
Kyösti Mälkki | 444d2af | 2019-09-29 07:03:31 +0300 | [diff] [blame] | 535 | reg32 = pci_read_config32(p2peg, SLOTCAP); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 536 | reg32 &= 0x0007ffff; |
| 537 | |
| 538 | reg32 &= 0xfffe007f; |
| 539 | |
Kyösti Mälkki | 444d2af | 2019-09-29 07:03:31 +0300 | [diff] [blame] | 540 | pci_write_config32(p2peg, SLOTCAP, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 541 | |
| 542 | /* Wait for training to succeed */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 543 | printk(BIOS_DEBUG, "PCIe link training ..."); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 544 | timeout = 0x7ffff; |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 545 | while ((((pci_read_config32(p2peg, PEGSTS) >> 16) & 3) != 3) && --timeout) |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 546 | ; |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 547 | |
Kyösti Mälkki | 2647b6f | 2019-09-29 07:03:55 +0300 | [diff] [blame] | 548 | reg32 = pci_read_config32(peg_plugin, PCI_VENDOR_ID); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 549 | if (reg32 != 0x00000000 && reg32 != 0xffffffff) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 550 | printk(BIOS_DEBUG, " Detected PCIe device %04x:%04x\n", |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 551 | reg32 & 0xffff, reg32 >> 16); |
| 552 | } else { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 553 | printk(BIOS_DEBUG, " timeout!\n"); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 554 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 555 | printk(BIOS_DEBUG, "Restrain PCIe port to x1\n"); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 556 | |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 557 | pci_update_config32(p2peg, PEGSTS, ~(0xf << 1), 1); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 558 | |
Kyösti Mälkki | ad787e1 | 2019-09-30 04:14:19 +0300 | [diff] [blame] | 559 | /* Force PCIRST# */ |
| 560 | pci_s_assert_secondary_reset(p2peg); |
| 561 | pci_s_deassert_secondary_reset(p2peg); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 562 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 563 | printk(BIOS_DEBUG, "PCIe link training ..."); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 564 | timeout = 0x7ffff; |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 565 | while ((((pci_read_config32(p2peg, PEGSTS) >> 16) & 3) != 3) && --timeout) |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 566 | ; |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 567 | |
Kyösti Mälkki | 2647b6f | 2019-09-29 07:03:55 +0300 | [diff] [blame] | 568 | reg32 = pci_read_config32(peg_plugin, PCI_VENDOR_ID); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 569 | if (reg32 != 0x00000000 && reg32 != 0xffffffff) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 570 | printk(BIOS_DEBUG, " Detected PCIe x1 device %04x:%04x\n", |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 571 | reg32 & 0xffff, reg32 >> 16); |
| 572 | } else { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 573 | printk(BIOS_DEBUG, " timeout!\n"); |
| 574 | printk(BIOS_DEBUG, "Disabling PCIe x16 port completely.\n"); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 575 | goto disable_pciexpress_x16_link; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 576 | } |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 577 | } |
| 578 | |
Kyösti Mälkki | 444d2af | 2019-09-29 07:03:31 +0300 | [diff] [blame] | 579 | reg16 = pci_read_config16(p2peg, 0xb2); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 580 | reg16 >>= 4; |
| 581 | reg16 &= 0x3f; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 582 | /* reg16 == 1 -> x1; reg16 == 16 -> x16 */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 583 | printk(BIOS_DEBUG, "PCIe x%d link training succeeded.\n", reg16); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 584 | |
Kyösti Mälkki | 444d2af | 2019-09-29 07:03:31 +0300 | [diff] [blame] | 585 | reg32 = pci_read_config32(p2peg, PEGTC); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 586 | reg32 &= 0xfffffc00; /* clear [9:0] */ |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 587 | if (reg16 == 1) |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 588 | reg32 |= 0x32b; |
| 589 | // TODO |
Kyösti Mälkki | 444d2af | 2019-09-29 07:03:31 +0300 | [diff] [blame] | 590 | /* pci_write_config32(p2peg, PEGTC, reg32); */ |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 591 | else if (reg16 == 16) |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 592 | reg32 |= 0x0f4; |
| 593 | // TODO |
Kyösti Mälkki | 444d2af | 2019-09-29 07:03:31 +0300 | [diff] [blame] | 594 | /* pci_write_config32(p2peg, PEGTC, reg32); */ |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 595 | |
Kyösti Mälkki | 2647b6f | 2019-09-29 07:03:55 +0300 | [diff] [blame] | 596 | reg32 = (pci_read_config32(peg_plugin, 0x8) >> 8); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 597 | printk(BIOS_DEBUG, "PCIe device class: %06x\n", reg32); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 598 | if (reg32 == 0x030000) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 599 | printk(BIOS_DEBUG, "PCIe device is VGA. Disabling IGD.\n"); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 600 | reg16 = (1 << 1); |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 601 | pci_write_config16(HOST_BRIDGE, GGC, reg16); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 602 | |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 603 | pci_and_config32(HOST_BRIDGE, DEVEN, ~(DEVEN_D2F0 | DEVEN_D2F1)); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 604 | } |
| 605 | |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 606 | /* Enable GPEs: PMEGPE, HPGPE, GENGPE */ |
| 607 | pci_or_config32(p2peg, PEG_LC, (1 << 2) | (1 << 1) | (1 << 0)); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 608 | |
| 609 | /* Virtual Channel Configuration: Only VC0 on PCIe x16 */ |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 610 | pci_and_config32(p2peg, VC0RCTL, ~0x000000fe); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 611 | |
| 612 | /* Extended VC count */ |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 613 | pci_and_config32(p2peg, PVCCAP1, ~(7 << 0)); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 614 | |
| 615 | /* Active State Power Management ASPM */ |
| 616 | |
| 617 | /* TODO */ |
| 618 | |
| 619 | /* Clear error bits */ |
Kyösti Mälkki | 444d2af | 2019-09-29 07:03:31 +0300 | [diff] [blame] | 620 | pci_write_config16(p2peg, PCISTS1, 0xffff); |
| 621 | pci_write_config16(p2peg, SSTS1, 0xffff); |
| 622 | pci_write_config16(p2peg, DSTS, 0xffff); |
| 623 | pci_write_config32(p2peg, UESTS, 0xffffffff); |
| 624 | pci_write_config32(p2peg, CESTS, 0xffffffff); |
| 625 | pci_write_config32(p2peg, 0x1f0, 0xffffffff); |
| 626 | pci_write_config32(p2peg, 0x228, 0xffffffff); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 627 | |
| 628 | /* Program R/WO registers */ |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 629 | pci_update_config32(p2peg, 0x308, ~0, 0); |
| 630 | pci_update_config32(p2peg, 0x314, ~0, 0); |
| 631 | pci_update_config32(p2peg, 0x324, ~0, 0); |
| 632 | pci_update_config32(p2peg, 0x328, ~0, 0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 633 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 634 | /* Additional PCIe graphics setup */ |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 635 | pci_or_config32(p2peg, 0xf0, 3 << 26); |
| 636 | pci_or_config32(p2peg, 0xf0, 3 << 24); |
| 637 | pci_or_config32(p2peg, 0xf0, 1 << 5); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 638 | |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 639 | pci_update_config32(p2peg, 0x200, ~(3 << 26), 2 << 26); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 640 | |
Kyösti Mälkki | 444d2af | 2019-09-29 07:03:31 +0300 | [diff] [blame] | 641 | reg32 = pci_read_config32(p2peg, 0xe80); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 642 | if (i945_silicon_revision() >= 2) |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 643 | reg32 |= (1 << 12); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 644 | else |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 645 | reg32 &= ~(1 << 12); |
Kyösti Mälkki | 444d2af | 2019-09-29 07:03:31 +0300 | [diff] [blame] | 646 | pci_write_config32(p2peg, 0xe80, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 647 | |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 648 | pci_and_config32(p2peg, 0xeb4, ~(1 << 31)); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 649 | |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 650 | pci_or_config32(p2peg, 0xfc, 1 << 31); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 651 | |
| 652 | if (i945_silicon_revision() >= 3) { |
| 653 | static const u32 reglist[] = { |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 654 | 0xec0, 0xed4, 0xee8, 0xefc, 0xf10, 0xf24, 0xf38, 0xf4c, |
| 655 | 0xf60, 0xf74, 0xf88, 0xf9c, 0xfb0, 0xfc4, 0xfd8, 0xfec |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 656 | }; |
| 657 | |
| 658 | int i; |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 659 | for (i = 0; i < ARRAY_SIZE(reglist); i++) |
| 660 | pci_update_config32(p2peg, reglist[i], ~(0xf << 28), 2 << 28); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 661 | } |
| 662 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 663 | if (i945_silicon_revision() <= 2) { |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 664 | /* Set voltage specific parameters */ |
Kyösti Mälkki | 444d2af | 2019-09-29 07:03:31 +0300 | [diff] [blame] | 665 | reg32 = pci_read_config32(p2peg, 0xe80); |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 666 | reg32 &= (0xf << 4); /* Default case 1.05V */ |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 667 | if ((mchbar_read32(DFT_STRAP1) & (1 << 20)) == 0) { /* 1.50V */ |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 668 | reg32 |= (7 << 4); |
| 669 | } |
Kyösti Mälkki | 444d2af | 2019-09-29 07:03:31 +0300 | [diff] [blame] | 670 | pci_write_config32(p2peg, 0xe80, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 671 | } |
| 672 | |
| 673 | return; |
| 674 | |
| 675 | disable_pciexpress_x16_link: |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 676 | /* For now we just disable the x16 link */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 677 | printk(BIOS_DEBUG, "Disabling PCI Express x16 Link\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 678 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 679 | mchbar_setbits16(UPMC1, 1 << 5 | 1 << 0); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 680 | |
Kyösti Mälkki | ad787e1 | 2019-09-30 04:14:19 +0300 | [diff] [blame] | 681 | /* Toggle PCIRST# */ |
| 682 | pci_s_assert_secondary_reset(p2peg); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 683 | |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 684 | pci_or_config32(p2peg, 0x224, 1 << 8); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 685 | |
Kyösti Mälkki | ad787e1 | 2019-09-30 04:14:19 +0300 | [diff] [blame] | 686 | pci_s_deassert_secondary_reset(p2peg); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 687 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 688 | printk(BIOS_DEBUG, "Wait for link to enter detect state... "); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 689 | timeout = 0x7fffff; |
Kyösti Mälkki | 444d2af | 2019-09-29 07:03:31 +0300 | [diff] [blame] | 690 | for (reg32 = pci_read_config32(p2peg, PEGSTS); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 691 | (reg32 & 0x000f0000) && --timeout;) |
| 692 | ; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 693 | if (!timeout) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 694 | printk(BIOS_DEBUG, "timeout!\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 695 | else |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 696 | printk(BIOS_DEBUG, "ok\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 697 | |
| 698 | /* Finally: Disable the PCI config header */ |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 699 | pci_and_config16(HOST_BRIDGE, DEVEN, ~DEVEN_D1F0); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 700 | } |
| 701 | |
| 702 | static void i945_setup_root_complex_topology(void) |
| 703 | { |
| 704 | u32 reg32; |
Elyes HAOUAS | 961658f | 2020-04-06 09:42:21 +0200 | [diff] [blame] | 705 | const pci_devfn_t p2peg = PCI_DEV(0, 0x01, 0); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 706 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 707 | printk(BIOS_DEBUG, "Setting up Root Complex Topology\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 708 | /* Egress Port Root Topology */ |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 709 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 710 | reg32 = epbar_read32(EPESD); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 711 | reg32 &= 0xff00ffff; |
| 712 | reg32 |= (1 << 16); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 713 | epbar_write32(EPESD, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 714 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 715 | epbar_setbits32(EPLE1D, 1 << 16 | 1 << 0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 716 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 717 | epbar_write32(EPLE1A, CONFIG_FIXED_DMIBAR_MMIO_BASE); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 718 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 719 | epbar_setbits32(EPLE2D, 1 << 16 | 1 << 0); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 720 | |
| 721 | /* DMI Port Root Topology */ |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 722 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 723 | reg32 = dmibar_read32(DMILE1D); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 724 | reg32 &= 0x00ffffff; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 725 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 726 | reg32 &= 0xff00ffff; |
| 727 | reg32 |= (2 << 16); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 728 | |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 729 | reg32 |= (1 << 0); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 730 | dmibar_write32(DMILE1D, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 731 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 732 | dmibar_write32(DMILE1A, CONFIG_FIXED_RCBA_MMIO_BASE); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 733 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 734 | dmibar_setbits32(DMILE2D, 1 << 16 | 1 << 0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 735 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 736 | dmibar_write32(DMILE2A, CONFIG_FIXED_EPBAR_MMIO_BASE); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 737 | |
| 738 | /* PCI Express x16 Port Root Topology */ |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 739 | if (pci_read_config8(HOST_BRIDGE, DEVEN) & DEVEN_D1F0) { |
Angel Pons | 4299cb4 | 2021-01-20 12:32:22 +0100 | [diff] [blame] | 740 | pci_write_config32(p2peg, LE1A, CONFIG_FIXED_EPBAR_MMIO_BASE); |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 741 | pci_or_config32(p2peg, LE1D, 1 << 0); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 742 | } |
| 743 | } |
| 744 | |
| 745 | static void ich7_setup_root_complex_topology(void) |
| 746 | { |
Elyes HAOUAS | b217baa | 2019-01-18 15:32:39 +0100 | [diff] [blame] | 747 | /* Write the R/WO registers */ |
| 748 | |
| 749 | RCBA32(ESD) |= (2 << 16); |
| 750 | |
| 751 | RCBA32(ULD) |= (1 << 24) | (1 << 16); |
| 752 | |
Angel Pons | 4299cb4 | 2021-01-20 12:32:22 +0100 | [diff] [blame] | 753 | RCBA32(ULBA) = CONFIG_FIXED_DMIBAR_MMIO_BASE; |
Elyes HAOUAS | b217baa | 2019-01-18 15:32:39 +0100 | [diff] [blame] | 754 | /* Write ESD.CID to TCID */ |
| 755 | RCBA32(RP1D) |= (2 << 16); |
| 756 | RCBA32(RP2D) |= (2 << 16); |
| 757 | RCBA32(RP3D) |= (2 << 16); |
| 758 | RCBA32(RP4D) |= (2 << 16); |
| 759 | RCBA32(HDD) |= (2 << 16); |
| 760 | RCBA32(RP5D) |= (2 << 16); |
| 761 | RCBA32(RP6D) |= (2 << 16); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 762 | } |
| 763 | |
| 764 | static void ich7_setup_pci_express(void) |
| 765 | { |
Elyes HAOUAS | 1374607 | 2019-12-08 11:34:24 +0100 | [diff] [blame] | 766 | /* Enable PCIe Root Port Clock Gate */ |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 767 | RCBA32(CG) |= (1 << 0); |
| 768 | |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 769 | /* Initialize slot power limit for root ports */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 770 | pci_write_config32(PCI_DEV(0, 0x1c, 0), 0x54, 0x00000060); |
| 771 | |
| 772 | pci_write_config32(PCI_DEV(0, 0x1c, 0), 0xd8, 0x00110000); |
| 773 | } |
| 774 | |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 775 | void i945_early_initialization(void) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 776 | { |
| 777 | /* Print some chipset specific information */ |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 778 | switch (pci_read_config32(HOST_BRIDGE, 0)) { |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 779 | case 0x27708086: /* 82945G/GZ/GC/P/PL */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 780 | i945_detect_chipset(); |
| 781 | break; |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 782 | case 0x27a08086: /* 945GME/GSE */ |
| 783 | case 0x27ac8086: /* 945GM/PM/GMS/GU/GT, 943/940GML */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 784 | i945m_detect_chipset(); |
| 785 | break; |
| 786 | } |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 787 | |
| 788 | /* Setup all BARs required for early PCIe and raminit */ |
| 789 | i945_setup_bars(); |
| 790 | |
| 791 | /* Change port80 to LPC */ |
| 792 | RCBA32(GCS) &= (~0x04); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 793 | |
| 794 | /* Just do it that way */ |
| 795 | RCBA32(0x2010) |= (1 << 10); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 796 | } |
| 797 | |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 798 | static void i945_prepare_resume(int s3resume) |
| 799 | { |
| 800 | int cbmem_was_initted; |
| 801 | |
| 802 | cbmem_was_initted = !cbmem_recovery(s3resume); |
| 803 | |
Kyösti Mälkki | 8183025 | 2016-06-25 11:40:00 +0300 | [diff] [blame] | 804 | romstage_handoff_init(cbmem_was_initted && s3resume); |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 805 | } |
| 806 | |
| 807 | void i945_late_initialization(int s3resume) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 808 | { |
| 809 | i945_setup_egress_port(); |
| 810 | |
| 811 | ich7_setup_root_complex_topology(); |
| 812 | |
| 813 | ich7_setup_pci_express(); |
| 814 | |
| 815 | ich7_setup_dmi_rcrb(); |
| 816 | |
| 817 | i945_setup_dmi_rcrb(); |
| 818 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 819 | if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) |
Arthur Heymans | 2f6b52e | 2017-03-02 23:51:09 +0100 | [diff] [blame] | 820 | i945_setup_pci_express_x16(); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 821 | |
| 822 | i945_setup_root_complex_topology(); |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 823 | |
Kyösti Mälkki | 346d201 | 2019-03-23 10:07:16 +0200 | [diff] [blame] | 824 | if (CONFIG(DEBUG_RAM_SETUP)) |
| 825 | sdram_dump_mchbar_registers(); |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 826 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 827 | mchbar_write16(SSKPD, 0xcafe); |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 828 | |
| 829 | i945_prepare_resume(s3resume); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 830 | } |