Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 4 | * Copyright (C) 2007-2009 coresystems GmbH |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include "i945.h" |
| 21 | #include "pcie_config.c" |
| 22 | |
| 23 | static int i945_silicon_revision(void) |
| 24 | { |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 25 | return pci_read_config8(PCI_DEV(0, 0x00, 0), PCI_CLASS_REVISION); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 26 | } |
| 27 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame^] | 28 | static void i945m_detect_chipset(void) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 29 | { |
| 30 | u8 reg8; |
| 31 | |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 32 | printk_info("\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 33 | reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) & 0x70) >> 4; |
| 34 | switch (reg8) { |
| 35 | case 1: |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame^] | 36 | printk_info("Mobile Intel(R) 82945GM/GME Express"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 37 | break; |
| 38 | case 2: |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame^] | 39 | printk_info("Mobile Intel(R) 82945GMS/GU Express"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 40 | break; |
| 41 | case 3: |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame^] | 42 | printk_info("Mobile Intel(R) 82945PM Express"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 43 | break; |
| 44 | case 5: |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame^] | 45 | printk_info("Intel(R) 82945GT Express"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 46 | break; |
| 47 | case 6: |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame^] | 48 | printk_info("Mobile Intel(R) 82943/82940GML Express"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 49 | break; |
| 50 | default: |
| 51 | printk_info("Unknown (%02x)", reg8); /* Others reserved. */ |
| 52 | } |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 53 | printk_info(" Chipset\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 54 | |
| 55 | printk_debug("(G)MCH capable of up to FSB "); |
| 56 | reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe3) & 0xe0) >> 5; |
| 57 | switch (reg8) { |
| 58 | case 2: |
| 59 | printk_debug("800 MHz"); /* According to 965 spec */ |
| 60 | break; |
| 61 | case 3: |
| 62 | printk_debug("667 MHz"); |
| 63 | break; |
| 64 | case 4: |
| 65 | printk_debug("533 MHz"); |
| 66 | break; |
| 67 | default: |
| 68 | printk_debug("N/A MHz (%02x)", reg8); |
| 69 | } |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 70 | printk_debug("\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 71 | |
| 72 | printk_debug("(G)MCH capable of "); |
| 73 | reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) & 0x07); |
| 74 | switch (reg8) { |
| 75 | case 2: |
| 76 | printk_debug("up to DDR2-667"); |
| 77 | break; |
| 78 | case 3: |
| 79 | printk_debug("up to DDR2-533"); |
| 80 | break; |
| 81 | case 4: |
| 82 | printk_debug("DDR2-400"); |
| 83 | break; |
| 84 | default: |
| 85 | printk_info("unknown max. RAM clock (%02x).", reg8); /* Others reserved. */ |
| 86 | } |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 87 | printk_debug("\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 88 | } |
| 89 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame^] | 90 | static void i945_detect_chipset(void) |
| 91 | { |
| 92 | u8 reg8; |
| 93 | |
| 94 | printk_info("\nIntel(R) "); |
| 95 | reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0x8); |
| 96 | switch (reg8) { |
| 97 | case 0: |
| 98 | case 1: |
| 99 | printk_info("82945G"); |
| 100 | break; |
| 101 | case 2: |
| 102 | printk_info("82945G/GZ/GC"); |
| 103 | break; |
| 104 | case 0x80: |
| 105 | case 0x81: |
| 106 | case 0x82: |
| 107 | printk_info("82945P/PL"); |
| 108 | break; |
| 109 | default: |
| 110 | printk_info("Unknown (%02x)", reg8); /* Others unknown. */ |
| 111 | } |
| 112 | printk_info(" Chipset\n"); |
| 113 | |
| 114 | printk_debug("(G)MCH capable of "); |
| 115 | reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) & 0x07); |
| 116 | switch (reg8) { |
| 117 | case 0: |
| 118 | printk_debug("up to DDR2-667"); |
| 119 | break; |
| 120 | case 3: |
| 121 | printk_debug("up to DDR2-533"); |
| 122 | break; |
| 123 | default: |
| 124 | printk_info("unknown max. RAM clock (%02x).", reg8); /* Others reserved. */ |
| 125 | } |
| 126 | printk_debug("\n"); |
| 127 | } |
| 128 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 129 | static void i945_setup_bars(void) |
| 130 | { |
| 131 | u8 reg8; |
| 132 | |
| 133 | /* As of now, we don't have all the A0 workarounds implemented */ |
| 134 | if (i945_silicon_revision() == 0) |
| 135 | printk_info |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 136 | ("Warning: i945 silicon revision A0 might not work correctly.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 137 | |
| 138 | /* Setting up Southbridge. In the northbridge code. */ |
| 139 | printk_debug("Setting up static southbridge registers..."); |
| 140 | pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, DEFAULT_RCBA | 1); |
| 141 | |
| 142 | pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); |
| 143 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */ |
| 144 | |
| 145 | pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); |
| 146 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10); /* Enable GPIOs */ |
| 147 | setup_ich7_gpios(); |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 148 | printk_debug(" done.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 149 | |
| 150 | printk_debug("Disabling Watchdog reboot..."); |
| 151 | RCBA32(GCS) = (RCBA32(0x3410)) | (1 << 5); /* No reset */ |
| 152 | outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 153 | printk_debug(" done.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 154 | |
| 155 | printk_debug("Setting up static northbridge registers..."); |
| 156 | /* Set up all hardcoded northbridge BARs */ |
| 157 | pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); |
| 158 | pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1); |
| 159 | pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR, DEFAULT_PCIEXBAR | 5); /* 64MB - busses 0-63 */ |
| 160 | pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1); |
| 161 | pci_write_config32(PCI_DEV(0, 0x00, 0), X60BAR, DEFAULT_X60BAR | 1); |
| 162 | |
| 163 | /* Hardware default is 8MB UMA. If someone wants to make this a |
| 164 | * CMOS or compile time option, send a patch. |
| 165 | * pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, 0x30); |
| 166 | */ |
| 167 | |
| 168 | /* Set C0000-FFFFF to access RAM on both reads and writes */ |
| 169 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30); |
| 170 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33); |
| 171 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM2, 0x33); |
| 172 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM3, 0x33); |
| 173 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM4, 0x33); |
| 174 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); |
| 175 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); |
| 176 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 177 | pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 178 | printk_debug(" done.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 179 | |
| 180 | /* Wait for MCH BAR to come up */ |
| 181 | printk_debug("Waiting for MCHBAR to come up..."); |
| 182 | if ((pci_read_config8(PCI_DEV(0, 0x0f, 0), 0xe6) & 0x2) == 0x00) { /* Bit 49 of CAPID0 */ |
| 183 | do { |
| 184 | reg8 = *(volatile u8 *)0xfed40000; |
| 185 | } while (!(reg8 & 0x80)); |
| 186 | } |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 187 | printk_debug("ok\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 188 | } |
| 189 | |
| 190 | static void i945_setup_egress_port(void) |
| 191 | { |
| 192 | u32 reg32; |
| 193 | u32 timeout; |
| 194 | |
| 195 | printk_debug("Setting up Egress Port RCRB\n"); |
| 196 | |
| 197 | /* Egress Port Virtual Channel 0 Configuration */ |
| 198 | |
| 199 | /* map only TC0 to VC0 */ |
| 200 | reg32 = EPBAR32(EPVC0RCTL); |
| 201 | reg32 &= 0xffffff01; |
| 202 | EPBAR32(EPVC0RCTL) = reg32; |
| 203 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 204 | reg32 = EPBAR32(EPPVCCAP1); |
| 205 | reg32 &= ~(7 << 0); |
| 206 | reg32 |= 1; |
| 207 | EPBAR32(EPPVCCAP1) = reg32; |
| 208 | |
| 209 | /* Egress Port Virtual Channel 1 Configuration */ |
| 210 | reg32 = EPBAR32(0x2c); |
| 211 | reg32 &= 0xffffff00; |
| 212 | if ((MCHBAR32(CLKCFG) & 7) == 1) |
| 213 | reg32 |= 0x0d; /* 533MHz */ |
| 214 | if ((MCHBAR32(CLKCFG) & 7) == 3) |
| 215 | reg32 |= 0x10; /* 667MHz */ |
| 216 | EPBAR32(0x2c) = reg32; |
| 217 | |
| 218 | EPBAR32(EPVC1MTS) = 0x0a0a0a0a; |
| 219 | |
| 220 | reg32 = EPBAR32(EPVC1RCAP); |
| 221 | reg32 &= ~(0x7f << 16); |
| 222 | reg32 |= (0x0a << 16); |
| 223 | EPBAR32(EPVC1RCAP) = reg32; |
| 224 | |
| 225 | if ((MCHBAR32(CLKCFG) & 7) == 1) { /* 533MHz */ |
| 226 | EPBAR32(EPVC1IST + 0) = 0x009c009c; |
| 227 | EPBAR32(EPVC1IST + 4) = 0x009c009c; |
| 228 | } |
| 229 | |
| 230 | if ((MCHBAR32(CLKCFG) & 7) == 3) { /* 667MHz */ |
| 231 | EPBAR32(EPVC1IST + 0) = 0x00c000c0; |
| 232 | EPBAR32(EPVC1IST + 4) = 0x00c000c0; |
| 233 | } |
| 234 | |
| 235 | /* Is internal graphics enabled? */ |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 236 | if (pci_read_config8(PCI_DEV(0, 0x0, 0), 0x54) & ((1 << 4) | (1 << 3))) { /* DEVEN */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 237 | MCHBAR32(MMARB1) |= (1 << 17); |
| 238 | } |
| 239 | |
| 240 | /* Assign Virtual Channel ID 1 to VC1 */ |
| 241 | reg32 = EPBAR32(EPVC1RCTL); |
| 242 | reg32 &= ~(7 << 24); |
| 243 | reg32 |= (1 << 24); |
| 244 | EPBAR32(EPVC1RCTL) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 245 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 246 | reg32 = EPBAR32(EPVC1RCTL); |
| 247 | reg32 &= 0xffffff01; |
| 248 | reg32 |= (1 << 7); |
| 249 | EPBAR32(EPVC1RCTL) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 250 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 251 | EPBAR32(PORTARB + 0x00) = 0x01000001; |
| 252 | EPBAR32(PORTARB + 0x04) = 0x00040000; |
| 253 | EPBAR32(PORTARB + 0x08) = 0x00001000; |
| 254 | EPBAR32(PORTARB + 0x0c) = 0x00000040; |
| 255 | EPBAR32(PORTARB + 0x10) = 0x01000001; |
| 256 | EPBAR32(PORTARB + 0x14) = 0x00040000; |
| 257 | EPBAR32(PORTARB + 0x18) = 0x00001000; |
| 258 | EPBAR32(PORTARB + 0x1c) = 0x00000040; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 259 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 260 | EPBAR32(EPVC1RCTL) |= (1 << 16); |
| 261 | EPBAR32(EPVC1RCTL) |= (1 << 16); |
| 262 | |
| 263 | printk_debug("Loading port arbitration table ..."); |
| 264 | /* Loop until bit 0 becomes 0 */ |
| 265 | timeout = 0x7fffff; |
| 266 | while ((EPBAR16(EPVC1RSTS) & 1) && --timeout) ; |
| 267 | if (!timeout) |
| 268 | printk_debug("timeout!\n"); |
| 269 | else |
| 270 | printk_debug("ok\n"); |
| 271 | |
| 272 | /* Now enable VC1 */ |
| 273 | EPBAR32(EPVC1RCTL) |= (1 << 31); |
| 274 | |
| 275 | printk_debug("Wait for VC1 negotiation ..."); |
| 276 | /* Wait for VC1 negotiation pending */ |
| 277 | timeout = 0x7fff; |
| 278 | while ((EPBAR16(EPVC1RSTS) & (1 << 1)) && --timeout) ; |
| 279 | if (!timeout) |
| 280 | printk_debug("timeout!\n"); |
| 281 | else |
| 282 | printk_debug("ok\n"); |
| 283 | |
| 284 | } |
| 285 | |
| 286 | static void ich7_setup_dmi_rcrb(void) |
| 287 | { |
| 288 | u16 reg16; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 289 | u32 reg32; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 290 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 291 | reg16 = RCBA16(LCTL); |
| 292 | reg16 &= ~(3 << 0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 293 | reg16 |= 3; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 294 | RCBA16(LCTL) = reg16; |
| 295 | |
| 296 | RCBA32(V0CTL) = 0x80000001; |
| 297 | RCBA32(V1CAP) = 0x03128010; |
| 298 | RCBA32(ESD) = 0x00000810; |
| 299 | RCBA32(RP1D) = 0x01000003; |
| 300 | RCBA32(RP2D) = 0x02000002; |
| 301 | RCBA32(RP3D) = 0x03000002; |
| 302 | RCBA32(RP4D) = 0x04000002; |
| 303 | RCBA32(HDD) = 0x0f000003; |
| 304 | RCBA32(RP5D) = 0x05000002; |
| 305 | |
| 306 | RCBA32(RPFN) = 0x00543210; |
| 307 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 308 | pci_write_config16(PCI_DEV(0, 0x1c, 0), 0x42, 0x0141); |
| 309 | pci_write_config16(PCI_DEV(0, 0x1c, 4), 0x42, 0x0141); |
| 310 | pci_write_config16(PCI_DEV(0, 0x1c, 5), 0x42, 0x0141); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 311 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 312 | pci_write_config32(PCI_DEV(0, 0x1c, 4), 0x54, 0x00480ce0); |
| 313 | pci_write_config32(PCI_DEV(0, 0x1c, 5), 0x54, 0x00500ce0); |
| 314 | |
| 315 | reg32 = RCBA32(V1CTL); |
| 316 | reg32 &= ~( (0x7f << 1) | (7 << 17) | (7 << 24) ); |
| 317 | reg32 |= (0x40 << 1) | (4 << 17) | (1 << 24) | (1 << 31); |
| 318 | RCBA32(V1CTL) = reg32; |
| 319 | |
| 320 | RCBA32(ESD) |= (2 << 16); |
| 321 | |
| 322 | RCBA32(ULD) |= (1 << 24) | (1 << 16); |
| 323 | |
| 324 | RCBA32(ULBA) = DEFAULT_DMIBAR; |
| 325 | |
| 326 | RCBA32(RP1D) |= (2 << 16); |
| 327 | RCBA32(RP2D) |= (2 << 16); |
| 328 | RCBA32(RP3D) |= (2 << 16); |
| 329 | RCBA32(RP4D) |= (2 << 16); |
| 330 | RCBA32(HDD) |= (2 << 16); |
| 331 | RCBA32(RP5D) |= (2 << 16); |
| 332 | RCBA32(RP6D) |= (2 << 16); |
| 333 | |
| 334 | RCBA32(LCAP) |= (3 << 10); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 335 | } |
| 336 | |
| 337 | static void i945_setup_dmi_rcrb(void) |
| 338 | { |
| 339 | u32 reg32; |
| 340 | u32 timeout; |
| 341 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 342 | int activate_aspm = 1; |
| 343 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 344 | printk_debug("Setting up DMI RCRB\n"); |
| 345 | |
| 346 | /* Virtual Channel 0 Configuration */ |
| 347 | reg32 = DMIBAR32(DMIVC0RCTL0); |
| 348 | reg32 &= 0xffffff01; |
| 349 | DMIBAR32(DMIVC0RCTL0) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 350 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 351 | reg32 = DMIBAR32(DMIPVCCAP1); |
| 352 | reg32 &= ~(7 << 0); |
| 353 | reg32 |= 1; |
| 354 | DMIBAR32(DMIPVCCAP1) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 355 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 356 | reg32 = DMIBAR32(DMIVC1RCTL); |
| 357 | reg32 &= ~(7 << 24); |
| 358 | reg32 |= (1 << 24); /* NOTE: This ID must match ICH7 side */ |
| 359 | DMIBAR32(DMIVC1RCTL) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 360 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 361 | reg32 = DMIBAR32(DMIVC1RCTL); |
| 362 | reg32 &= 0xffffff01; |
| 363 | reg32 |= (1 << 7); |
| 364 | DMIBAR32(DMIVC1RCTL) = reg32; |
| 365 | |
| 366 | /* Now enable VC1 */ |
| 367 | DMIBAR32(DMIVC1RCTL) |= (1 << 31); |
| 368 | |
| 369 | printk_debug("Wait for VC1 negotiation ..."); |
| 370 | /* Wait for VC1 negotiation pending */ |
| 371 | timeout = 0x7ffff; |
| 372 | while ((DMIBAR16(DMIVC1RSTS) & (1 << 1)) && --timeout) ; |
| 373 | if (!timeout) |
| 374 | printk_debug("timeout!\n"); |
| 375 | else |
| 376 | printk_debug("done..\n"); |
| 377 | #if 1 |
| 378 | /* Enable Active State Power Management (ASPM) L0 state */ |
| 379 | |
| 380 | reg32 = DMIBAR32(DMILCAP); |
| 381 | reg32 &= ~(7 << 12); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 382 | reg32 |= (2 << 12); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 383 | |
| 384 | reg32 &= ~(7 << 15); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame^] | 385 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 386 | reg32 |= (2 << 15); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 387 | DMIBAR32(DMILCAP) = reg32; |
| 388 | |
| 389 | reg32 = DMIBAR32(DMICC); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 390 | reg32 &= 0x00ffffff; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 391 | reg32 &= ~(3 << 0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 392 | reg32 |= (1 << 0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 393 | reg32 &= ~(3 << 20); |
| 394 | reg32 |= (1 << 20); |
| 395 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 396 | DMIBAR32(DMICC) = reg32; |
| 397 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 398 | if (activate_aspm) { |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 399 | DMIBAR32(DMILCTL) |= (3 << 0); |
| 400 | } |
| 401 | #endif |
| 402 | |
| 403 | /* Last but not least, some additional steps */ |
| 404 | reg32 = MCHBAR32(FSBSNPCTL); |
| 405 | reg32 &= ~(0xff << 2); |
| 406 | reg32 |= (0xaa << 2); |
| 407 | MCHBAR32(FSBSNPCTL) = reg32; |
| 408 | |
| 409 | DMIBAR32(0x2c) = 0x86000040; |
| 410 | |
| 411 | reg32 = DMIBAR32(0x204); |
| 412 | reg32 &= ~0x3ff; |
| 413 | #if 1 |
| 414 | reg32 |= 0x13f; /* for x4 DMI only */ |
| 415 | #else |
| 416 | reg32 |= 0x1e4; /* for x2 DMI only */ |
| 417 | #endif |
| 418 | DMIBAR32(0x204) = reg32; |
| 419 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 420 | if (pci_read_config8(PCI_DEV(0, 0x0, 0), 0x54) & ((1 << 4) | (1 << 3))) { /* DEVEN */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame^] | 421 | printk_debug("Internal graphics: enabled\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 422 | DMIBAR32(0x200) |= (1 << 21); |
| 423 | } else { |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame^] | 424 | printk_debug("Internal graphics: disabled\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 425 | DMIBAR32(0x200) &= ~(1 << 21); |
| 426 | } |
| 427 | |
| 428 | reg32 = DMIBAR32(0x204); |
| 429 | reg32 &= ~((1 << 11) | (1 << 10)); |
| 430 | DMIBAR32(0x204) = reg32; |
| 431 | |
| 432 | reg32 = DMIBAR32(0x204); |
| 433 | reg32 &= ~(0xff << 12); |
| 434 | reg32 |= (0x0d << 12); |
| 435 | DMIBAR32(0x204) = reg32; |
| 436 | |
| 437 | DMIBAR32(DMICTL1) |= (3 << 24); |
| 438 | |
| 439 | reg32 = DMIBAR32(0x200); |
| 440 | reg32 &= ~(0x3 << 26); |
| 441 | reg32 |= (0x02 << 26); |
| 442 | DMIBAR32(0x200) = reg32; |
| 443 | |
| 444 | DMIBAR32(DMIDRCCFG) &= ~(1 << 31); |
| 445 | DMIBAR32(DMICTL2) |= (1 << 31); |
| 446 | |
| 447 | if (i945_silicon_revision() >= 3) { |
| 448 | reg32 = DMIBAR32(0xec0); |
| 449 | reg32 &= 0x0fffffff; |
| 450 | reg32 |= (2 << 28); |
| 451 | DMIBAR32(0xec0) = reg32; |
| 452 | |
| 453 | reg32 = DMIBAR32(0xed4); |
| 454 | reg32 &= 0x0fffffff; |
| 455 | reg32 |= (2 << 28); |
| 456 | DMIBAR32(0xed4) = reg32; |
| 457 | |
| 458 | reg32 = DMIBAR32(0xee8); |
| 459 | reg32 &= 0x0fffffff; |
| 460 | reg32 |= (2 << 28); |
| 461 | DMIBAR32(0xee8) = reg32; |
| 462 | |
| 463 | reg32 = DMIBAR32(0xefc); |
| 464 | reg32 &= 0x0fffffff; |
| 465 | reg32 |= (2 << 28); |
| 466 | DMIBAR32(0xefc) = reg32; |
| 467 | } |
| 468 | |
| 469 | /* wait for bit toggle to 0 */ |
| 470 | printk_debug("Waiting for DMI hardware..."); |
| 471 | timeout = 0x7fffff; |
| 472 | while ((DMIBAR8(0x32) & (1 << 1)) && --timeout) ; |
| 473 | if (!timeout) |
| 474 | printk_debug("timeout!\n"); |
| 475 | else |
| 476 | printk_debug("ok\n"); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 477 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 478 | DMIBAR32(0x1c4) = 0xffffffff; |
| 479 | DMIBAR32(0x1d0) = 0xffffffff; |
| 480 | DMIBAR32(0x228) = 0xffffffff; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 481 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 482 | DMIBAR32(0x308) = DMIBAR32(0x308); |
| 483 | DMIBAR32(0x314) = DMIBAR32(0x314); |
| 484 | DMIBAR32(0x324) = DMIBAR32(0x324); |
| 485 | DMIBAR32(0x328) = DMIBAR32(0x328); |
| 486 | DMIBAR32(0x338) = DMIBAR32(0x334); |
| 487 | DMIBAR32(0x338) = DMIBAR32(0x338); |
| 488 | |
| 489 | if (i945_silicon_revision() == 1 && ((MCHBAR8(0xe08) & (1 << 5)) == 1)) { |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 490 | if ((MCHBAR32(0x214) & 0xf) != 0x3) { |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 491 | printk_info |
| 492 | ("DMI link requires A1 stepping workaround. Rebooting.\n"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame^] | 493 | reg32 = DMIBAR32(0x224); |
| 494 | reg32 &= ~(7 << 0); |
| 495 | reg32 |= (3 << 0); |
| 496 | DMIBAR32(0x224) = reg32; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 497 | outb(0x06, 0xcf9); |
| 498 | for (;;) ; /* wait for reset */ |
| 499 | } |
| 500 | } |
| 501 | } |
| 502 | |
| 503 | static void i945_setup_pci_express_x16(void) |
| 504 | { |
| 505 | u32 timeout; |
| 506 | u32 reg32; |
| 507 | u16 reg16; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame^] | 508 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 509 | u8 reg8; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 510 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 511 | printk_debug("Enabling PCI Express x16 Link\n"); |
| 512 | |
| 513 | reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DEVEN); |
| 514 | reg16 |= DEVEN_D1F0; |
| 515 | pci_write_config16(PCI_DEV(0, 0x00, 0), DEVEN, reg16); |
| 516 | |
| 517 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x208); |
| 518 | reg32 &= ~(1 << 8); |
| 519 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x208, reg32); |
| 520 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame^] | 521 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x224); |
| 522 | reg32 &= ~(1 << 8); |
| 523 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x224, reg32); |
| 524 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 525 | MCHBAR16(UPMC1) &= ~( (1 << 5) | (1 << 0) ); |
| 526 | |
| 527 | /* Initialze PEG_CAP */ |
| 528 | reg16 = pcie_read_config16(PCI_DEV(0, 0x01, 0), 0xa2); |
| 529 | reg16 |= (1 << 8); |
| 530 | pcie_write_config16(PCI_DEV(0, 0x01, 0), 0xa2, reg16); |
| 531 | |
| 532 | /* Setup SLOTCAP */ |
| 533 | /* TODO: These values are mainboard dependent and should |
| 534 | * be set from Config.lb or Options.lb. |
| 535 | */ |
| 536 | /* NOTE: SLOTCAP becomes RO after the first write! */ |
| 537 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xb4); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame^] | 538 | reg32 &= 0x0007ffff; |
| 539 | |
| 540 | reg32 &= 0xfffe007f; |
| 541 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 542 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xb4, reg32); |
| 543 | |
| 544 | /* Wait for training to succeed */ |
| 545 | printk_debug("Wait for PCIe x16 link training ..."); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame^] | 546 | timeout = 0x7fff; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 547 | while ((((pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214) >> 16) & 4) != 3) && --timeout) ; |
| 548 | if (!timeout) { |
| 549 | printk_debug("timeout!\n"); |
| 550 | |
| 551 | printk_debug("Restrain PCIe port to x1\n"); |
| 552 | |
| 553 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214); |
| 554 | reg32 &= ~(0xf << 1); |
| 555 | reg32 |=1; |
| 556 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x214, reg32); |
| 557 | |
| 558 | reg16 = pcie_read_config16(PCI_DEV(0, 0x01, 0), 0x3e); |
| 559 | |
| 560 | reg16 |= (1 << 6); |
| 561 | pcie_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16); |
| 562 | reg16 &= ~(1 << 6); |
| 563 | pcie_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16); |
| 564 | |
| 565 | printk_debug("Wait for PCIe x1 link training ..."); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame^] | 566 | timeout = 0x7fff; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 567 | while ((((pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214) >> 16) & 4) != 3) && --timeout) ; |
| 568 | if (!timeout) { |
| 569 | printk_debug("timeout!\n"); |
| 570 | printk_debug("Disabling PCIe x16 port completely.\n"); |
| 571 | goto disable_pciexpress_x16_link; |
| 572 | } else { |
| 573 | printk_debug("ok\n"); |
| 574 | } |
| 575 | } else { |
| 576 | printk_debug("ok\n"); |
| 577 | } |
| 578 | |
| 579 | reg16 = pcie_read_config16(PCI_DEV(0, 0x01, 0), 0xb2); |
| 580 | reg16 >>= 4; |
| 581 | reg16 &= 0x3f; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame^] | 582 | /* reg16 == 1 -> x1; reg16 == 16 -> x16 */ |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 583 | printk_debug("PCIe x%d link training succeeded.\n", reg16); |
| 584 | |
| 585 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x204); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame^] | 586 | reg32 &= 0xfffffc00; /* clear [9:0] */ |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 587 | if (reg16 == 1) { |
| 588 | reg32 |= 0x32b; |
| 589 | // TODO |
| 590 | } else if (reg16 == 16) { |
| 591 | reg32 |= 0x0f4; |
| 592 | // TODO |
| 593 | } |
| 594 | |
| 595 | /* Enable GPEs */ |
| 596 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xec); |
| 597 | reg32 |= (1 << 2) | (1 << 1) | (1 << 0); /* PMEGPE, HPGPE, GENGPE */ |
| 598 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x114, reg32); |
| 599 | |
| 600 | /* Virtual Channel Configuration: Only VC0 on PCIe x16 */ |
| 601 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x114); |
| 602 | reg32 &= 0xffffff01; |
| 603 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x114, reg32); |
| 604 | |
| 605 | /* Extended VC count */ |
| 606 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x104); |
| 607 | reg32 &= ~(7 << 0); |
| 608 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x104, reg32); |
| 609 | |
| 610 | /* Active State Power Management ASPM */ |
| 611 | |
| 612 | /* TODO */ |
| 613 | |
| 614 | /* Clear error bits */ |
| 615 | pcie_write_config16(PCI_DEV(0, 0x01, 0), 0x06, 0xffff); |
| 616 | pcie_write_config16(PCI_DEV(0, 0x01, 0), 0x1e, 0xffff); |
| 617 | pcie_write_config16(PCI_DEV(0, 0x01, 0), 0xaa, 0xffff); |
| 618 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x1c4, 0xffffffff); |
| 619 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x1d0, 0xffffffff); |
| 620 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x1f0, 0xffffffff); |
| 621 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x228, 0xffffffff); |
| 622 | |
| 623 | /* Program R/WO registers */ |
| 624 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x308); |
| 625 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x308, reg32); |
| 626 | |
| 627 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x314); |
| 628 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x314, reg32); |
| 629 | |
| 630 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x324); |
| 631 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x324, reg32); |
| 632 | |
| 633 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x328); |
| 634 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x328, reg32); |
| 635 | |
| 636 | reg8 = pcie_read_config8(PCI_DEV(0, 0x01, 0), 0xb4); |
| 637 | pcie_write_config8(PCI_DEV(0, 0x01, 0), 0xb4, reg8); |
| 638 | |
| 639 | /* Additional PCIe graphics setup */ |
| 640 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xf0); |
| 641 | reg32 |= (3 << 26); |
| 642 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32); |
| 643 | |
| 644 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xf0); |
| 645 | reg32 |= (3 << 24); |
| 646 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32); |
| 647 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame^] | 648 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xf0); |
| 649 | reg32 |= (1 << 5); |
| 650 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32); |
| 651 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 652 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x200); |
| 653 | reg32 &= ~(3 << 26); |
| 654 | reg32 |= (2 << 26); |
| 655 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x200, reg32); |
| 656 | |
| 657 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xe80); |
| 658 | if (i945_silicon_revision() >= 2) { |
| 659 | reg32 |= (1 << 12); |
| 660 | } else { |
| 661 | reg32 &= ~(1 << 12); |
| 662 | } |
| 663 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xe80, reg32); |
| 664 | |
| 665 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xeb4); |
| 666 | reg32 &= ~(1 << 31); |
| 667 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xeb4, reg32); |
| 668 | |
| 669 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xfc); |
| 670 | reg32 |= (1 << 31); |
| 671 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xfc, reg32); |
| 672 | |
| 673 | if (i945_silicon_revision() >= 3) { |
| 674 | static const u32 reglist[] = { |
| 675 | 0xec0, 0xed4, 0xee8, 0xefc, 0xf10, 0xf24, |
| 676 | 0xf38, 0xf4c, 0xf60, 0xf74, 0xf88, 0xf9c, |
| 677 | 0xfb0, 0xfc4, 0xfd8, 0xfec |
| 678 | }; |
| 679 | |
| 680 | int i; |
| 681 | for (i=0; i<ARRAY_SIZE(reglist); i++) { |
| 682 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), reglist[i]); |
| 683 | reg32 &= 0x0fffffff; |
| 684 | reg32 |= (2 << 28); |
| 685 | pcie_write_config32(PCI_DEV(0, 0x01, 0), reglist[i], reg32); |
| 686 | } |
| 687 | } |
| 688 | |
| 689 | if (i945_silicon_revision() <= 2 ) { |
| 690 | /* Set voltage specific parameters */ |
| 691 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xe80); |
| 692 | reg32 &= (0xf << 4); |
| 693 | if ((MCHBAR32(0xe08) & (1 << 20)) == 0) { |
| 694 | reg32 |= (7 << 4); |
| 695 | } |
| 696 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xe80, reg32); |
| 697 | } |
| 698 | |
| 699 | return; |
| 700 | |
| 701 | disable_pciexpress_x16_link: |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 702 | /* For now we just disable the x16 link */ |
| 703 | printk_debug("Disabling PCI Express x16 Link\n"); |
| 704 | |
| 705 | MCHBAR16(UPMC1) |= (1 << 5) | (1 << 0); |
| 706 | |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 707 | reg16 = pcie_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1); |
| 708 | reg16 |= (1 << 6); |
| 709 | pcie_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 710 | |
| 711 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x224); |
| 712 | reg32 |= (1 << 8); |
| 713 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x224, reg32); |
| 714 | |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 715 | reg16 = pcie_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1); |
| 716 | reg16 &= ~(1 << 6); |
| 717 | pcie_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 718 | |
| 719 | printk_debug("Wait for link to enter detect state... "); |
| 720 | timeout = 0x7fffff; |
| 721 | for (reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214); |
| 722 | (reg32 & 0x000f0000) && --timeout;) ; |
| 723 | if (!timeout) |
| 724 | printk_debug("timeout!\n"); |
| 725 | else |
| 726 | printk_debug("ok\n"); |
| 727 | |
| 728 | /* Finally: Disable the PCI config header */ |
| 729 | reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DEVEN); |
| 730 | reg16 &= ~DEVEN_D1F0; |
| 731 | pci_write_config16(PCI_DEV(0, 0x00, 0), DEVEN, reg16); |
| 732 | } |
| 733 | |
| 734 | static void i945_setup_root_complex_topology(void) |
| 735 | { |
| 736 | u32 reg32; |
| 737 | |
| 738 | printk_debug("Setting up Root Complex Topology\n"); |
| 739 | /* Egress Port Root Topology */ |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 740 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 741 | reg32 = EPBAR32(EPESD); |
| 742 | reg32 &= 0xff00ffff; |
| 743 | reg32 |= (1 << 16); |
| 744 | EPBAR32(EPESD) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 745 | |
| 746 | EPBAR32(EPLE1D) |= (1 << 16); |
| 747 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 748 | EPBAR32(EPLE1D) |= (1 << 0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 749 | |
| 750 | EPBAR32(EPLE1A) = DEFAULT_DMIBAR; |
| 751 | #if 0 |
| 752 | EPBAR32(EPLE2D) |= (1 << 16); |
| 753 | #endif |
| 754 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 755 | EPBAR32(EPLE2D) |= (1 << 0); |
| 756 | |
| 757 | /* DMI Port Root Topology */ |
| 758 | reg32 = DMIBAR32(DMILE1D); |
| 759 | reg32 &= 0x00ffffff; |
| 760 | DMIBAR32(DMILE1D) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 761 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 762 | reg32 = DMIBAR32(DMILE1D); |
| 763 | reg32 &= 0xff00ffff; |
| 764 | reg32 |= (2 << 16); |
| 765 | DMIBAR32(DMILE1D) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 766 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 767 | DMIBAR32(DMILE1D) |= (1 << 0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 768 | |
| 769 | DMIBAR32(DMILE1A) = DEFAULT_RCBA; |
| 770 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 771 | DMIBAR32(DMILE2D) |= (1 << 0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 772 | |
| 773 | DMIBAR32(DMILE2A) = DEFAULT_EPBAR; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 774 | |
| 775 | /* PCI Express x16 Port Root Topology */ |
| 776 | if (pci_read_config8(PCI_DEV(0, 0x00, 0), DEVEN) & DEVEN_D1F0) { |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 777 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x158, DEFAULT_EPBAR); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 778 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x150); |
| 779 | reg32 |= (1 << 0); |
| 780 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x150, reg32); |
| 781 | } |
| 782 | } |
| 783 | |
| 784 | static void ich7_setup_root_complex_topology(void) |
| 785 | { |
| 786 | RCBA32(0x104) = 0x00000802; |
| 787 | RCBA32(0x110) = 0x00000001; |
| 788 | RCBA32(0x114) = 0x00000000; |
| 789 | RCBA32(0x118) = 0x00000000; |
| 790 | } |
| 791 | |
| 792 | static void ich7_setup_pci_express(void) |
| 793 | { |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 794 | RCBA32(CG) |= (1 << 0); |
| 795 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 796 | pci_write_config32(PCI_DEV(0, 0x1c, 0), 0x54, 0x00000060); |
| 797 | |
| 798 | pci_write_config32(PCI_DEV(0, 0x1c, 0), 0xd8, 0x00110000); |
| 799 | } |
| 800 | |
| 801 | static void i945_early_initialization(void) |
| 802 | { |
| 803 | /* Print some chipset specific information */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame^] | 804 | switch (pci_read_config32(PCI_DEV(0, 0x00, 0), 0)) { |
| 805 | case 0x27708086: |
| 806 | i945_detect_chipset(); |
| 807 | break; |
| 808 | case 0x27a08086: |
| 809 | case 0x27ac8086: |
| 810 | i945m_detect_chipset(); |
| 811 | break; |
| 812 | } |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 813 | |
| 814 | /* Setup all BARs required for early PCIe and raminit */ |
| 815 | i945_setup_bars(); |
| 816 | |
| 817 | /* Change port80 to LPC */ |
| 818 | RCBA32(GCS) &= (~0x04); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 819 | |
| 820 | /* Just do it that way */ |
| 821 | RCBA32(0x2010) |= (1 << 10); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 822 | } |
| 823 | |
| 824 | static void i945_late_initialization(void) |
| 825 | { |
| 826 | i945_setup_egress_port(); |
| 827 | |
| 828 | ich7_setup_root_complex_topology(); |
| 829 | |
| 830 | ich7_setup_pci_express(); |
| 831 | |
| 832 | ich7_setup_dmi_rcrb(); |
| 833 | |
| 834 | i945_setup_dmi_rcrb(); |
| 835 | |
| 836 | i945_setup_pci_express_x16(); |
| 837 | |
| 838 | i945_setup_root_complex_topology(); |
| 839 | } |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame^] | 840 | |