| commit | 13746076e95a611b56dfe37519685ae125172bb4 | [log] [tgz] |
|---|---|---|
| author | Elyes HAOUAS <ehaouas@noos.fr> | Sun Dec 08 11:34:24 2019 +0100 |
| committer | Patrick Georgi <pgeorgi@google.com> | Tue Dec 10 11:16:07 2019 +0000 |
| tree | 3d41161b459454cfc89db62c9412e07f3ed1e8a0 | |
| parent | e86ded841fdb3846b070a9cbe1793f72efe540aa [diff] [blame] |
mainboard/(i945,ich7): Remove commented RCBA32(0x341c) code PCIe root port clock gate is already enabled at i945/early_init.c Also fix comments when only PCIe root port is enabled. Change-Id: Ica38529dbdd5cc51b19b426999a1d9f0b678b4f5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37576 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 13dce61..6629a0e 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c
@@ -837,6 +837,7 @@ static void ich7_setup_pci_express(void) { + /* Enable PCIe Root Port Clock Gate */ RCBA32(CG) |= (1 << 0); /* Initialize slot power limit for root ports */