commit 3dff32c8041bb6d1ee4b2c5a8681ec0259b46bf6
author Elyes HAOUAS <ehaouas@noos.fr> Mon Mar 30 17:16:51 2020 +0200
committer Nico Huber <nico.h@gmx.de> Sat Apr 11 09:19:13 2020 +0000
tree d0207b25eee58f16bb5a8c222f4798278b15fcee
parent fd8de1860df9487cffb62bb2b657bd6e55b20596

nb/i945: Improve code formatting

Change-Id: I8a1eadcdc51dedd1e17eb6ae7847d9209b2bd598
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/northbridge/intel/i945/early_init.c

diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index d7bc1c6..ced635a 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -1,15 +1,15 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /* This file is part of the coreboot project. */
 
+#include <arch/io.h>
+#include <cbmem.h>
 #include <cf9_reset.h>
 #include <console/console.h>
-#include <arch/io.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
 #include <device/pci_def.h>
-#include <cbmem.h>
-#include <romstage_handoff.h>
+#include <device/pci_ops.h>
+#include <device/pci.h>
 #include <option.h>
+#include <romstage_handoff.h>
 #include <types.h>
 
 #include "i945.h"
@@ -41,8 +41,8 @@
 	case 6:
 		printk(BIOS_INFO, "Mobile Intel(R) 82943/82940GML Express");
 		break;
-	default:
-		printk(BIOS_INFO, "Unknown (%02x)", reg8);	/* Others reserved. */
+	default: /* Others reserved. */
+		printk(BIOS_INFO, "Unknown (%02x)", reg8);
 	}
 	printk(BIOS_INFO, " Chipset\n");
 
@@ -75,8 +75,8 @@
 	case 4:
 		printk(BIOS_DEBUG, "DDR2-400");
 		break;
-	default:
-		printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8);	/* Others reserved. */
+	default: /* Others reserved. */
+		printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8);
 	}
 	printk(BIOS_DEBUG, "\n");
 
@@ -90,7 +90,8 @@
 
 	printk(BIOS_INFO, "\nIntel(R) ");
 
-	reg8 = ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) >> 5) & 4) | ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) >> 4) & 3);
+	reg8 = ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) >> 5) & 4)
+	     | ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) >> 4) & 3);
 	switch (reg8) {
 	case 0:
 	case 1:
@@ -125,8 +126,8 @@
 	case 3:
 		printk(BIOS_DEBUG, "up to DDR2-533");
 		break;
-	default:
-		printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8);	/* Others reserved. */
+	default: /* Others reserved. */
+		printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8);
 	}
 	printk(BIOS_DEBUG, "\n");
 
@@ -403,9 +404,9 @@
 	reg32 = DMIBAR32(0x204);
 	reg32 &= ~0x3ff;
 #if 1
-	reg32 |= 0x13f;		/* for x4 DMI only */
+	reg32 |= 0x13f;	/* for x4 DMI only */
 #else
-	reg32 |= 0x1e4; /* for x2 DMI only */
+	reg32 |= 0x1e4;	/* for x2 DMI only */
 #endif
 	DMIBAR32(0x204) = reg32;
 
@@ -543,8 +544,7 @@
 	pci_write_config16(p2peg, PEG_CAP, reg16);
 
 	/* Setup SLOTCAP */
-	/* TODO: These values are mainboard dependent and should
-	 * be set from devicetree.cb.
+	/* TODO: These values are mainboard dependent and should be set from devicetree.cb.
 	 */
 	/* NOTE: SLOTCAP becomes RO after the first write! */
 	reg32 = pci_read_config32(p2peg, SLOTCAP);
@@ -701,9 +701,8 @@
 
 	if (i945_silicon_revision() >= 3) {
 		static const u32 reglist[] = {
-			0xec0, 0xed4, 0xee8, 0xefc, 0xf10, 0xf24,
-			0xf38, 0xf4c, 0xf60, 0xf74, 0xf88, 0xf9c,
-			0xfb0, 0xfc4, 0xfd8, 0xfec
+			0xec0, 0xed4, 0xee8, 0xefc, 0xf10, 0xf24, 0xf38, 0xf4c,
+			0xf60, 0xf74, 0xf88, 0xf9c, 0xfb0, 0xfc4, 0xfd8, 0xfec
 		};
 
 		int i;