Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 4 | * Copyright (C) 2007-2010 coresystems GmbH |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 14 | */ |
| 15 | |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 16 | #include <stdint.h> |
| 17 | #include <stdlib.h> |
| 18 | #include <console/console.h> |
Kyösti Mälkki | a969ed3 | 2016-06-15 06:08:15 +0300 | [diff] [blame] | 19 | #include <arch/acpi.h> |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 20 | #include <arch/io.h> |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 21 | #include <device/pci_def.h> |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 22 | #include <cbmem.h> |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 23 | #include <halt.h> |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 24 | #include <string.h> |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 25 | #include "i945.h" |
Arthur Heymans | 874a8f9 | 2016-05-19 16:06:09 +0200 | [diff] [blame] | 26 | #include <pc80/mc146818rtc.h> |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 27 | |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 28 | int i945_silicon_revision(void) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 29 | { |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 30 | return pci_read_config8(PCI_DEV(0, 0x00, 0), PCI_CLASS_REVISION); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 31 | } |
| 32 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 33 | static void i945m_detect_chipset(void) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 34 | { |
| 35 | u8 reg8; |
| 36 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 37 | printk(BIOS_INFO, "\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 38 | reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) & 0x70) >> 4; |
| 39 | switch (reg8) { |
| 40 | case 1: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 41 | printk(BIOS_INFO, "Mobile Intel(R) 82945GM/GME Express"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 42 | break; |
| 43 | case 2: |
Stefan Reinauer | 7981b94 | 2011-04-01 22:33:25 +0200 | [diff] [blame] | 44 | printk(BIOS_INFO, "Mobile Intel(R) 82945GMS/GU/GSE Express"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 45 | break; |
| 46 | case 3: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 47 | printk(BIOS_INFO, "Mobile Intel(R) 82945PM Express"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 48 | break; |
| 49 | case 5: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 50 | printk(BIOS_INFO, "Intel(R) 82945GT Express"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 51 | break; |
| 52 | case 6: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 53 | printk(BIOS_INFO, "Mobile Intel(R) 82943/82940GML Express"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 54 | break; |
| 55 | default: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 56 | printk(BIOS_INFO, "Unknown (%02x)", reg8); /* Others reserved. */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 57 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 58 | printk(BIOS_INFO, " Chipset\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 59 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 60 | printk(BIOS_DEBUG, "(G)MCH capable of up to FSB "); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 61 | reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe3) & 0xe0) >> 5; |
| 62 | switch (reg8) { |
| 63 | case 2: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 64 | printk(BIOS_DEBUG, "800 MHz"); /* According to 965 spec */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 65 | break; |
| 66 | case 3: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 67 | printk(BIOS_DEBUG, "667 MHz"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 68 | break; |
| 69 | case 4: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 70 | printk(BIOS_DEBUG, "533 MHz"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 71 | break; |
| 72 | default: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 73 | printk(BIOS_DEBUG, "N/A MHz (%02x)", reg8); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 74 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 75 | printk(BIOS_DEBUG, "\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 76 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 77 | printk(BIOS_DEBUG, "(G)MCH capable of "); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 78 | reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) & 0x07); |
| 79 | switch (reg8) { |
| 80 | case 2: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 81 | printk(BIOS_DEBUG, "up to DDR2-667"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 82 | break; |
| 83 | case 3: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 84 | printk(BIOS_DEBUG, "up to DDR2-533"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 85 | break; |
| 86 | case 4: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 87 | printk(BIOS_DEBUG, "DDR2-400"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 88 | break; |
| 89 | default: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 90 | printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); /* Others reserved. */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 91 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 92 | printk(BIOS_DEBUG, "\n"); |
Elyes HAOUAS | 6372a0e | 2016-10-30 18:39:53 +0100 | [diff] [blame] | 93 | |
| 94 | if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) |
| 95 | printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 96 | } |
| 97 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 98 | static void i945_detect_chipset(void) |
| 99 | { |
| 100 | u8 reg8; |
| 101 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 102 | printk(BIOS_INFO, "\nIntel(R) "); |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 103 | |
| 104 | reg8 = ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) >> 5) & 4) | ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) >> 4) & 3); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 105 | switch (reg8) { |
| 106 | case 0: |
| 107 | case 1: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 108 | printk(BIOS_INFO, "82945G"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 109 | break; |
| 110 | case 2: |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 111 | case 3: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 112 | printk(BIOS_INFO, "82945P"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 113 | break; |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 114 | case 4: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 115 | printk(BIOS_INFO, "82945GC"); |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 116 | break; |
| 117 | case 5: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 118 | printk(BIOS_INFO, "82945GZ"); |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 119 | break; |
| 120 | case 6: |
| 121 | case 7: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 122 | printk(BIOS_INFO, "82945PL"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 123 | break; |
| 124 | default: |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 125 | break; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 126 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 127 | printk(BIOS_INFO, " Chipset\n"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 128 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 129 | printk(BIOS_DEBUG, "(G)MCH capable of "); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 130 | reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) & 0x07); |
| 131 | switch (reg8) { |
| 132 | case 0: |
Elyes HAOUAS | 5db9450 | 2016-10-30 18:30:21 +0100 | [diff] [blame] | 133 | case 2: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 134 | printk(BIOS_DEBUG, "up to DDR2-667"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 135 | break; |
| 136 | case 3: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 137 | printk(BIOS_DEBUG, "up to DDR2-533"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 138 | break; |
| 139 | default: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 140 | printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); /* Others reserved. */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 141 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 142 | printk(BIOS_DEBUG, "\n"); |
Elyes HAOUAS | 6372a0e | 2016-10-30 18:39:53 +0100 | [diff] [blame] | 143 | |
| 144 | if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) |
| 145 | printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 146 | } |
| 147 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 148 | static void i945_setup_bars(void) |
| 149 | { |
Arthur Heymans | 874a8f9 | 2016-05-19 16:06:09 +0200 | [diff] [blame] | 150 | u8 reg8, gfxsize; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 151 | |
| 152 | /* As of now, we don't have all the A0 workarounds implemented */ |
| 153 | if (i945_silicon_revision() == 0) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 154 | printk(BIOS_INFO, "Warning: i945 silicon revision A0 might not work correctly.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 155 | |
| 156 | /* Setting up Southbridge. In the northbridge code. */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 157 | printk(BIOS_DEBUG, "Setting up static southbridge registers..."); |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 158 | pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 159 | |
| 160 | pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); |
| 161 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */ |
| 162 | |
| 163 | pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); |
| 164 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10); /* Enable GPIOs */ |
| 165 | setup_ich7_gpios(); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 166 | printk(BIOS_DEBUG, " done.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 167 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 168 | printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 169 | RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 170 | outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 171 | printk(BIOS_DEBUG, " done.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 172 | |
Vladimir Serbinenko | 4aad743 | 2014-11-22 20:36:58 +0100 | [diff] [blame] | 173 | /* Enable upper 128bytes of CMOS */ |
| 174 | RCBA32(0x3400) = (1 << 2); |
| 175 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 176 | printk(BIOS_DEBUG, "Setting up static northbridge registers..."); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 177 | /* Set up all hardcoded northbridge BARs */ |
| 178 | pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 179 | pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); |
| 180 | pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 181 | pci_write_config32(PCI_DEV(0, 0x00, 0), X60BAR, DEFAULT_X60BAR | 1); |
| 182 | |
Arthur Heymans | 874a8f9 | 2016-05-19 16:06:09 +0200 | [diff] [blame] | 183 | /* vram size from cmos option */ |
| 184 | if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) |
| 185 | gfxsize = 2; /* 2 for 8MB */ |
| 186 | /* make sure no invalid setting is used */ |
| 187 | if (gfxsize > 6) |
| 188 | gfxsize = 2; |
| 189 | pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, ((gfxsize + 1) << 4)); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 190 | |
| 191 | /* Set C0000-FFFFF to access RAM on both reads and writes */ |
| 192 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30); |
| 193 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33); |
| 194 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM2, 0x33); |
| 195 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM3, 0x33); |
| 196 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM4, 0x33); |
| 197 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); |
| 198 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); |
| 199 | |
Sven Schnelle | d8c68a9 | 2011-06-15 09:26:34 +0200 | [diff] [blame] | 200 | pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_NORMAL_BOOT_MAGIC); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 201 | printk(BIOS_DEBUG, " done.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 202 | |
| 203 | /* Wait for MCH BAR to come up */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 204 | printk(BIOS_DEBUG, "Waiting for MCHBAR to come up..."); |
Elyes HAOUAS | a3ea1e4 | 2014-11-27 13:23:32 +0100 | [diff] [blame] | 205 | if ((pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4) & 0x20000) == 0x00) { /* Bit 49 of CAPID0 */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 206 | do { |
| 207 | reg8 = *(volatile u8 *)0xfed40000; |
| 208 | } while (!(reg8 & 0x80)); |
| 209 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 210 | printk(BIOS_DEBUG, "ok\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 211 | } |
| 212 | |
| 213 | static void i945_setup_egress_port(void) |
| 214 | { |
| 215 | u32 reg32; |
| 216 | u32 timeout; |
| 217 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 218 | printk(BIOS_DEBUG, "Setting up Egress Port RCRB\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 219 | |
| 220 | /* Egress Port Virtual Channel 0 Configuration */ |
| 221 | |
| 222 | /* map only TC0 to VC0 */ |
| 223 | reg32 = EPBAR32(EPVC0RCTL); |
| 224 | reg32 &= 0xffffff01; |
| 225 | EPBAR32(EPVC0RCTL) = reg32; |
| 226 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 227 | reg32 = EPBAR32(EPPVCCAP1); |
| 228 | reg32 &= ~(7 << 0); |
| 229 | reg32 |= 1; |
| 230 | EPBAR32(EPPVCCAP1) = reg32; |
| 231 | |
| 232 | /* Egress Port Virtual Channel 1 Configuration */ |
| 233 | reg32 = EPBAR32(0x2c); |
| 234 | reg32 &= 0xffffff00; |
| 235 | if ((MCHBAR32(CLKCFG) & 7) == 1) |
| 236 | reg32 |= 0x0d; /* 533MHz */ |
| 237 | if ((MCHBAR32(CLKCFG) & 7) == 3) |
| 238 | reg32 |= 0x10; /* 667MHz */ |
| 239 | EPBAR32(0x2c) = reg32; |
| 240 | |
| 241 | EPBAR32(EPVC1MTS) = 0x0a0a0a0a; |
| 242 | |
| 243 | reg32 = EPBAR32(EPVC1RCAP); |
| 244 | reg32 &= ~(0x7f << 16); |
| 245 | reg32 |= (0x0a << 16); |
| 246 | EPBAR32(EPVC1RCAP) = reg32; |
| 247 | |
| 248 | if ((MCHBAR32(CLKCFG) & 7) == 1) { /* 533MHz */ |
| 249 | EPBAR32(EPVC1IST + 0) = 0x009c009c; |
| 250 | EPBAR32(EPVC1IST + 4) = 0x009c009c; |
| 251 | } |
| 252 | |
| 253 | if ((MCHBAR32(CLKCFG) & 7) == 3) { /* 667MHz */ |
| 254 | EPBAR32(EPVC1IST + 0) = 0x00c000c0; |
| 255 | EPBAR32(EPVC1IST + 4) = 0x00c000c0; |
| 256 | } |
| 257 | |
| 258 | /* Is internal graphics enabled? */ |
Kyösti Mälkki | 3c3e34d | 2014-05-31 11:32:54 +0300 | [diff] [blame] | 259 | if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) { |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 260 | MCHBAR32(MMARB1) |= (1 << 17); |
| 261 | } |
| 262 | |
| 263 | /* Assign Virtual Channel ID 1 to VC1 */ |
| 264 | reg32 = EPBAR32(EPVC1RCTL); |
| 265 | reg32 &= ~(7 << 24); |
| 266 | reg32 |= (1 << 24); |
| 267 | EPBAR32(EPVC1RCTL) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 268 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 269 | reg32 = EPBAR32(EPVC1RCTL); |
| 270 | reg32 &= 0xffffff01; |
| 271 | reg32 |= (1 << 7); |
| 272 | EPBAR32(EPVC1RCTL) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 273 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 274 | EPBAR32(PORTARB + 0x00) = 0x01000001; |
| 275 | EPBAR32(PORTARB + 0x04) = 0x00040000; |
| 276 | EPBAR32(PORTARB + 0x08) = 0x00001000; |
| 277 | EPBAR32(PORTARB + 0x0c) = 0x00000040; |
| 278 | EPBAR32(PORTARB + 0x10) = 0x01000001; |
| 279 | EPBAR32(PORTARB + 0x14) = 0x00040000; |
| 280 | EPBAR32(PORTARB + 0x18) = 0x00001000; |
| 281 | EPBAR32(PORTARB + 0x1c) = 0x00000040; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 282 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 283 | EPBAR32(EPVC1RCTL) |= (1 << 16); |
| 284 | EPBAR32(EPVC1RCTL) |= (1 << 16); |
| 285 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 286 | printk(BIOS_DEBUG, "Loading port arbitration table ..."); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 287 | /* Loop until bit 0 becomes 0 */ |
| 288 | timeout = 0x7fffff; |
Elyes HAOUAS | 7db506c | 2016-10-02 11:56:39 +0200 | [diff] [blame] | 289 | while ((EPBAR16(EPVC1RSTS) & 1) && --timeout); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 290 | if (!timeout) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 291 | printk(BIOS_DEBUG, "timeout!\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 292 | else |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 293 | printk(BIOS_DEBUG, "ok\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 294 | |
| 295 | /* Now enable VC1 */ |
| 296 | EPBAR32(EPVC1RCTL) |= (1 << 31); |
| 297 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 298 | printk(BIOS_DEBUG, "Wait for VC1 negotiation ..."); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 299 | /* Wait for VC1 negotiation pending */ |
| 300 | timeout = 0x7fff; |
Elyes HAOUAS | 7db506c | 2016-10-02 11:56:39 +0200 | [diff] [blame] | 301 | while ((EPBAR16(EPVC1RSTS) & (1 << 1)) && --timeout); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 302 | if (!timeout) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 303 | printk(BIOS_DEBUG, "timeout!\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 304 | else |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 305 | printk(BIOS_DEBUG, "ok\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 306 | |
| 307 | } |
| 308 | |
| 309 | static void ich7_setup_dmi_rcrb(void) |
| 310 | { |
| 311 | u16 reg16; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 312 | u32 reg32; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 313 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 314 | reg16 = RCBA16(LCTL); |
| 315 | reg16 &= ~(3 << 0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 316 | reg16 |= 3; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 317 | RCBA16(LCTL) = reg16; |
| 318 | |
| 319 | RCBA32(V0CTL) = 0x80000001; |
| 320 | RCBA32(V1CAP) = 0x03128010; |
| 321 | RCBA32(ESD) = 0x00000810; |
| 322 | RCBA32(RP1D) = 0x01000003; |
| 323 | RCBA32(RP2D) = 0x02000002; |
| 324 | RCBA32(RP3D) = 0x03000002; |
| 325 | RCBA32(RP4D) = 0x04000002; |
| 326 | RCBA32(HDD) = 0x0f000003; |
| 327 | RCBA32(RP5D) = 0x05000002; |
| 328 | |
| 329 | RCBA32(RPFN) = 0x00543210; |
| 330 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 331 | pci_write_config16(PCI_DEV(0, 0x1c, 0), 0x42, 0x0141); |
| 332 | pci_write_config16(PCI_DEV(0, 0x1c, 4), 0x42, 0x0141); |
| 333 | pci_write_config16(PCI_DEV(0, 0x1c, 5), 0x42, 0x0141); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 334 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 335 | pci_write_config32(PCI_DEV(0, 0x1c, 4), 0x54, 0x00480ce0); |
| 336 | pci_write_config32(PCI_DEV(0, 0x1c, 5), 0x54, 0x00500ce0); |
| 337 | |
| 338 | reg32 = RCBA32(V1CTL); |
| 339 | reg32 &= ~( (0x7f << 1) | (7 << 17) | (7 << 24) ); |
| 340 | reg32 |= (0x40 << 1) | (4 << 17) | (1 << 24) | (1 << 31); |
| 341 | RCBA32(V1CTL) = reg32; |
| 342 | |
| 343 | RCBA32(ESD) |= (2 << 16); |
| 344 | |
| 345 | RCBA32(ULD) |= (1 << 24) | (1 << 16); |
| 346 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 347 | RCBA32(ULBA) = (uintptr_t)DEFAULT_DMIBAR; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 348 | |
| 349 | RCBA32(RP1D) |= (2 << 16); |
| 350 | RCBA32(RP2D) |= (2 << 16); |
| 351 | RCBA32(RP3D) |= (2 << 16); |
| 352 | RCBA32(RP4D) |= (2 << 16); |
| 353 | RCBA32(HDD) |= (2 << 16); |
| 354 | RCBA32(RP5D) |= (2 << 16); |
| 355 | RCBA32(RP6D) |= (2 << 16); |
| 356 | |
| 357 | RCBA32(LCAP) |= (3 << 10); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 358 | } |
| 359 | |
| 360 | static void i945_setup_dmi_rcrb(void) |
| 361 | { |
| 362 | u32 reg32; |
| 363 | u32 timeout; |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 364 | int activate_aspm = 1; /* hardcode ASPM for now */ |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 365 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 366 | printk(BIOS_DEBUG, "Setting up DMI RCRB\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 367 | |
| 368 | /* Virtual Channel 0 Configuration */ |
| 369 | reg32 = DMIBAR32(DMIVC0RCTL0); |
| 370 | reg32 &= 0xffffff01; |
| 371 | DMIBAR32(DMIVC0RCTL0) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 372 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 373 | reg32 = DMIBAR32(DMIPVCCAP1); |
| 374 | reg32 &= ~(7 << 0); |
| 375 | reg32 |= 1; |
| 376 | DMIBAR32(DMIPVCCAP1) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 377 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 378 | reg32 = DMIBAR32(DMIVC1RCTL); |
| 379 | reg32 &= ~(7 << 24); |
| 380 | reg32 |= (1 << 24); /* NOTE: This ID must match ICH7 side */ |
| 381 | DMIBAR32(DMIVC1RCTL) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 382 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 383 | reg32 = DMIBAR32(DMIVC1RCTL); |
| 384 | reg32 &= 0xffffff01; |
| 385 | reg32 |= (1 << 7); |
| 386 | DMIBAR32(DMIVC1RCTL) = reg32; |
| 387 | |
| 388 | /* Now enable VC1 */ |
| 389 | DMIBAR32(DMIVC1RCTL) |= (1 << 31); |
| 390 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 391 | printk(BIOS_DEBUG, "Wait for VC1 negotiation ..."); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 392 | /* Wait for VC1 negotiation pending */ |
| 393 | timeout = 0x7ffff; |
Elyes HAOUAS | 7db506c | 2016-10-02 11:56:39 +0200 | [diff] [blame] | 394 | while ((DMIBAR16(DMIVC1RSTS) & (1 << 1)) && --timeout); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 395 | if (!timeout) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 396 | printk(BIOS_DEBUG, "timeout!\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 397 | else |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 398 | printk(BIOS_DEBUG, "done..\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 399 | #if 1 |
| 400 | /* Enable Active State Power Management (ASPM) L0 state */ |
| 401 | |
| 402 | reg32 = DMIBAR32(DMILCAP); |
| 403 | reg32 &= ~(7 << 12); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 404 | reg32 |= (2 << 12); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 405 | |
| 406 | reg32 &= ~(7 << 15); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 407 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 408 | reg32 |= (2 << 15); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 409 | DMIBAR32(DMILCAP) = reg32; |
| 410 | |
| 411 | reg32 = DMIBAR32(DMICC); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 412 | reg32 &= 0x00ffffff; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 413 | reg32 &= ~(3 << 0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 414 | reg32 |= (1 << 0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 415 | reg32 &= ~(3 << 20); |
| 416 | reg32 |= (1 << 20); |
| 417 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 418 | DMIBAR32(DMICC) = reg32; |
| 419 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 420 | if (activate_aspm) { |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 421 | DMIBAR32(DMILCTL) |= (3 << 0); |
| 422 | } |
| 423 | #endif |
| 424 | |
| 425 | /* Last but not least, some additional steps */ |
| 426 | reg32 = MCHBAR32(FSBSNPCTL); |
| 427 | reg32 &= ~(0xff << 2); |
| 428 | reg32 |= (0xaa << 2); |
| 429 | MCHBAR32(FSBSNPCTL) = reg32; |
| 430 | |
| 431 | DMIBAR32(0x2c) = 0x86000040; |
| 432 | |
| 433 | reg32 = DMIBAR32(0x204); |
| 434 | reg32 &= ~0x3ff; |
| 435 | #if 1 |
| 436 | reg32 |= 0x13f; /* for x4 DMI only */ |
| 437 | #else |
| 438 | reg32 |= 0x1e4; /* for x2 DMI only */ |
| 439 | #endif |
| 440 | DMIBAR32(0x204) = reg32; |
| 441 | |
Kyösti Mälkki | 3c3e34d | 2014-05-31 11:32:54 +0300 | [diff] [blame] | 442 | if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 443 | printk(BIOS_DEBUG, "Internal graphics: enabled\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 444 | DMIBAR32(0x200) |= (1 << 21); |
| 445 | } else { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 446 | printk(BIOS_DEBUG, "Internal graphics: disabled\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 447 | DMIBAR32(0x200) &= ~(1 << 21); |
| 448 | } |
| 449 | |
| 450 | reg32 = DMIBAR32(0x204); |
| 451 | reg32 &= ~((1 << 11) | (1 << 10)); |
| 452 | DMIBAR32(0x204) = reg32; |
| 453 | |
| 454 | reg32 = DMIBAR32(0x204); |
| 455 | reg32 &= ~(0xff << 12); |
| 456 | reg32 |= (0x0d << 12); |
| 457 | DMIBAR32(0x204) = reg32; |
| 458 | |
| 459 | DMIBAR32(DMICTL1) |= (3 << 24); |
| 460 | |
| 461 | reg32 = DMIBAR32(0x200); |
| 462 | reg32 &= ~(0x3 << 26); |
| 463 | reg32 |= (0x02 << 26); |
| 464 | DMIBAR32(0x200) = reg32; |
| 465 | |
| 466 | DMIBAR32(DMIDRCCFG) &= ~(1 << 31); |
| 467 | DMIBAR32(DMICTL2) |= (1 << 31); |
| 468 | |
| 469 | if (i945_silicon_revision() >= 3) { |
| 470 | reg32 = DMIBAR32(0xec0); |
| 471 | reg32 &= 0x0fffffff; |
| 472 | reg32 |= (2 << 28); |
| 473 | DMIBAR32(0xec0) = reg32; |
| 474 | |
| 475 | reg32 = DMIBAR32(0xed4); |
| 476 | reg32 &= 0x0fffffff; |
| 477 | reg32 |= (2 << 28); |
| 478 | DMIBAR32(0xed4) = reg32; |
| 479 | |
| 480 | reg32 = DMIBAR32(0xee8); |
| 481 | reg32 &= 0x0fffffff; |
| 482 | reg32 |= (2 << 28); |
| 483 | DMIBAR32(0xee8) = reg32; |
| 484 | |
| 485 | reg32 = DMIBAR32(0xefc); |
| 486 | reg32 &= 0x0fffffff; |
| 487 | reg32 |= (2 << 28); |
| 488 | DMIBAR32(0xefc) = reg32; |
| 489 | } |
| 490 | |
| 491 | /* wait for bit toggle to 0 */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 492 | printk(BIOS_DEBUG, "Waiting for DMI hardware..."); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 493 | timeout = 0x7fffff; |
Elyes HAOUAS | 7db506c | 2016-10-02 11:56:39 +0200 | [diff] [blame] | 494 | while ((DMIBAR8(0x32) & (1 << 1)) && --timeout); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 495 | if (!timeout) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 496 | printk(BIOS_DEBUG, "timeout!\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 497 | else |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 498 | printk(BIOS_DEBUG, "ok\n"); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 499 | |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 500 | /* Clear Error Status Bits! */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 501 | DMIBAR32(0x1c4) = 0xffffffff; |
| 502 | DMIBAR32(0x1d0) = 0xffffffff; |
| 503 | DMIBAR32(0x228) = 0xffffffff; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 504 | |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 505 | /* Program Read-Only Write-Once Registers */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 506 | DMIBAR32(0x308) = DMIBAR32(0x308); |
| 507 | DMIBAR32(0x314) = DMIBAR32(0x314); |
| 508 | DMIBAR32(0x324) = DMIBAR32(0x324); |
| 509 | DMIBAR32(0x328) = DMIBAR32(0x328); |
| 510 | DMIBAR32(0x338) = DMIBAR32(0x334); |
| 511 | DMIBAR32(0x338) = DMIBAR32(0x338); |
| 512 | |
Patrick Georgi | a341a77 | 2014-09-29 19:51:21 +0200 | [diff] [blame] | 513 | if (i945_silicon_revision() == 1 && (MCHBAR8(DFT_STRAP1) & (1 << 5))) { |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 514 | if ((MCHBAR32(0x214) & 0xf) != 0x3) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 515 | printk(BIOS_INFO, "DMI link requires A1 stepping workaround. Rebooting.\n"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 516 | reg32 = DMIBAR32(0x224); |
| 517 | reg32 &= ~(7 << 0); |
| 518 | reg32 |= (3 << 0); |
| 519 | DMIBAR32(0x224) = reg32; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 520 | outb(0x06, 0xcf9); |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 521 | halt(); /* wait for reset */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 522 | } |
| 523 | } |
| 524 | } |
| 525 | |
| 526 | static void i945_setup_pci_express_x16(void) |
| 527 | { |
| 528 | u32 timeout; |
| 529 | u32 reg32; |
| 530 | u16 reg16; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 531 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 532 | u8 reg8; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 533 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 534 | printk(BIOS_DEBUG, "Enabling PCI Express x16 Link\n"); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 535 | |
| 536 | reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DEVEN); |
| 537 | reg16 |= DEVEN_D1F0; |
| 538 | pci_write_config16(PCI_DEV(0, 0x00, 0), DEVEN, reg16); |
| 539 | |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 540 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x208); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 541 | reg32 &= ~(1 << 8); |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 542 | pci_write_config32(PCI_DEV(0, 0x01, 0), 0x208, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 543 | |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 544 | /* We have no success with querying the usual PCIe registers |
| 545 | * for link setup success on the i945. Hence we assign a temporary |
| 546 | * PCI bus 0x0a and check whether we find a device on 0:a.0 |
| 547 | */ |
| 548 | |
| 549 | /* First we reset the secondary bus */ |
| 550 | reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0x3e); |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 551 | reg16 |= (1 << 6); /* SRESET */ |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 552 | pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16); |
| 553 | /* Read back and clear reset bit. */ |
| 554 | reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0x3e); |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 555 | reg16 &= ~(1 << 6); /* SRESET */ |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 556 | pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16); |
| 557 | |
| 558 | reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0xba); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 559 | printk(BIOS_DEBUG, "SLOTSTS: %04x\n", reg16); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 560 | if (!(reg16 & 0x48)) { |
| 561 | goto disable_pciexpress_x16_link; |
| 562 | } |
| 563 | reg16 |= (1 << 4) | (1 << 0); |
| 564 | pci_write_config16(PCI_DEV(0, 0x01, 0), 0xba, reg16); |
| 565 | |
| 566 | pci_write_config8(PCI_DEV(0, 0x01, 0), 0x19, 0x00); |
| 567 | pci_write_config8(PCI_DEV(0, 0x01, 0), 0x1a, 0x00); |
| 568 | pci_write_config8(PCI_DEV(0, 0x01, 0), 0x19, 0x0a); |
| 569 | pci_write_config8(PCI_DEV(0, 0x01, 0), 0x1a, 0x0a); |
| 570 | |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 571 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x224); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 572 | reg32 &= ~(1 << 8); |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 573 | pci_write_config32(PCI_DEV(0, 0x01, 0), 0x224, reg32); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 574 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 575 | MCHBAR16(UPMC1) &= ~( (1 << 5) | (1 << 0) ); |
| 576 | |
Martin Roth | 128c104 | 2016-11-18 09:29:03 -0700 | [diff] [blame^] | 577 | /* Initialize PEG_CAP */ |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 578 | reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0xa2); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 579 | reg16 |= (1 << 8); |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 580 | pci_write_config16(PCI_DEV(0, 0x01, 0), 0xa2, reg16); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 581 | |
| 582 | /* Setup SLOTCAP */ |
| 583 | /* TODO: These values are mainboard dependent and should |
Uwe Hermann | 607614d | 2010-11-18 20:12:13 +0000 | [diff] [blame] | 584 | * be set from devicetree.cb. |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 585 | */ |
| 586 | /* NOTE: SLOTCAP becomes RO after the first write! */ |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 587 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xb4); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 588 | reg32 &= 0x0007ffff; |
| 589 | |
| 590 | reg32 &= 0xfffe007f; |
| 591 | |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 592 | pci_write_config32(PCI_DEV(0, 0x01, 0), 0xb4, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 593 | |
| 594 | /* Wait for training to succeed */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 595 | printk(BIOS_DEBUG, "PCIe link training ..."); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 596 | timeout = 0x7ffff; |
Elyes HAOUAS | 7db506c | 2016-10-02 11:56:39 +0200 | [diff] [blame] | 597 | while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS) >> 16) & 3) != 3) && --timeout); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 598 | |
| 599 | reg32 = pci_read_config32(PCI_DEV(0x0a, 0x0, 0), 0); |
| 600 | if (reg32 != 0x00000000 && reg32 != 0xffffffff) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 601 | printk(BIOS_DEBUG, " Detected PCIe device %04x:%04x\n", |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 602 | reg32 & 0xffff, reg32 >> 16); |
| 603 | } else { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 604 | printk(BIOS_DEBUG, " timeout!\n"); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 605 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 606 | printk(BIOS_DEBUG, "Restrain PCIe port to x1\n"); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 607 | |
Patrick Georgi | d3060ed | 2014-08-10 15:19:45 +0200 | [diff] [blame] | 608 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 609 | reg32 &= ~(0xf << 1); |
| 610 | reg32 |=1; |
Patrick Georgi | d3060ed | 2014-08-10 15:19:45 +0200 | [diff] [blame] | 611 | pci_write_config32(PCI_DEV(0, 0x01, 0), PEGSTS, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 612 | |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 613 | reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0x3e); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 614 | |
| 615 | reg16 |= (1 << 6); |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 616 | pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 617 | reg16 &= ~(1 << 6); |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 618 | pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 619 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 620 | printk(BIOS_DEBUG, "PCIe link training ..."); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 621 | timeout = 0x7ffff; |
Elyes HAOUAS | 7db506c | 2016-10-02 11:56:39 +0200 | [diff] [blame] | 622 | while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS) >> 16) & 3) != 3) && --timeout); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 623 | |
| 624 | reg32 = pci_read_config32(PCI_DEV(0xa, 0x00, 0), 0); |
| 625 | if (reg32 != 0x00000000 && reg32 != 0xffffffff) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 626 | printk(BIOS_DEBUG, " Detected PCIe x1 device %04x:%04x\n", |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 627 | reg32 & 0xffff, reg32 >> 16); |
| 628 | } else { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 629 | printk(BIOS_DEBUG, " timeout!\n"); |
| 630 | printk(BIOS_DEBUG, "Disabling PCIe x16 port completely.\n"); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 631 | goto disable_pciexpress_x16_link; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 632 | } |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 633 | } |
| 634 | |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 635 | reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0xb2); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 636 | reg16 >>= 4; |
| 637 | reg16 &= 0x3f; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 638 | /* reg16 == 1 -> x1; reg16 == 16 -> x16 */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 639 | printk(BIOS_DEBUG, "PCIe x%d link training succeeded.\n", reg16); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 640 | |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 641 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x204); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 642 | reg32 &= 0xfffffc00; /* clear [9:0] */ |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 643 | if (reg16 == 1) { |
| 644 | reg32 |= 0x32b; |
| 645 | // TODO |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 646 | /* pci_write_config32(PCI_DEV(0, 0x01, 0), 0x204, reg32); */ |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 647 | } else if (reg16 == 16) { |
| 648 | reg32 |= 0x0f4; |
| 649 | // TODO |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 650 | /* pci_write_config32(PCI_DEV(0, 0x01, 0), 0x204, reg32); */ |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 651 | } |
| 652 | |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 653 | reg32 = (pci_read_config32(PCI_DEV(0xa, 0, 0), 0x8) >> 8); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 654 | printk(BIOS_DEBUG, "PCIe device class: %06x\n", reg32); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 655 | if (reg32 == 0x030000) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 656 | printk(BIOS_DEBUG, "PCIe device is VGA. Disabling IGD.\n"); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 657 | reg16 = (1 << 1); |
| 658 | pci_write_config16(PCI_DEV(0, 0x0, 0), 0x52, reg16); |
| 659 | |
Kyösti Mälkki | 3c3e34d | 2014-05-31 11:32:54 +0300 | [diff] [blame] | 660 | reg32 = pci_read_config32(PCI_DEV(0, 0x0, 0), DEVEN); |
| 661 | reg32 &= ~(DEVEN_D2F0 | DEVEN_D2F1); |
| 662 | pci_write_config32(PCI_DEV(0, 0x0, 0), DEVEN, reg32); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 663 | |
| 664 | /* Set VGA enable bit in PCIe bridge */ |
| 665 | reg16 = pci_read_config16(PCI_DEV(0, 0x1, 0), 0x3e); |
| 666 | reg16 |= (1 << 3); |
| 667 | pci_write_config16(PCI_DEV(0, 0x1, 0), 0x3e, reg16); |
| 668 | } |
| 669 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 670 | /* Enable GPEs */ |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 671 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xec); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 672 | reg32 |= (1 << 2) | (1 << 1) | (1 << 0); /* PMEGPE, HPGPE, GENGPE */ |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 673 | pci_write_config32(PCI_DEV(0, 0x01, 0), 0x114, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 674 | |
| 675 | /* Virtual Channel Configuration: Only VC0 on PCIe x16 */ |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 676 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x114); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 677 | reg32 &= 0xffffff01; |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 678 | pci_write_config32(PCI_DEV(0, 0x01, 0), 0x114, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 679 | |
| 680 | /* Extended VC count */ |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 681 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x104); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 682 | reg32 &= ~(7 << 0); |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 683 | pci_write_config32(PCI_DEV(0, 0x01, 0), 0x104, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 684 | |
| 685 | /* Active State Power Management ASPM */ |
| 686 | |
| 687 | /* TODO */ |
| 688 | |
| 689 | /* Clear error bits */ |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 690 | pci_write_config16(PCI_DEV(0, 0x01, 0), 0x06, 0xffff); |
| 691 | pci_write_config16(PCI_DEV(0, 0x01, 0), 0x1e, 0xffff); |
| 692 | pci_write_config16(PCI_DEV(0, 0x01, 0), 0xaa, 0xffff); |
| 693 | pci_write_config32(PCI_DEV(0, 0x01, 0), 0x1c4, 0xffffffff); |
| 694 | pci_write_config32(PCI_DEV(0, 0x01, 0), 0x1d0, 0xffffffff); |
| 695 | pci_write_config32(PCI_DEV(0, 0x01, 0), 0x1f0, 0xffffffff); |
| 696 | pci_write_config32(PCI_DEV(0, 0x01, 0), 0x228, 0xffffffff); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 697 | |
| 698 | /* Program R/WO registers */ |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 699 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x308); |
| 700 | pci_write_config32(PCI_DEV(0, 0x01, 0), 0x308, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 701 | |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 702 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x314); |
| 703 | pci_write_config32(PCI_DEV(0, 0x01, 0), 0x314, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 704 | |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 705 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x324); |
| 706 | pci_write_config32(PCI_DEV(0, 0x01, 0), 0x324, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 707 | |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 708 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x328); |
| 709 | pci_write_config32(PCI_DEV(0, 0x01, 0), 0x328, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 710 | |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 711 | reg8 = pci_read_config8(PCI_DEV(0, 0x01, 0), 0xb4); |
| 712 | pci_write_config8(PCI_DEV(0, 0x01, 0), 0xb4, reg8); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 713 | |
| 714 | /* Additional PCIe graphics setup */ |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 715 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xf0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 716 | reg32 |= (3 << 26); |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 717 | pci_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 718 | |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 719 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xf0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 720 | reg32 |= (3 << 24); |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 721 | pci_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 722 | |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 723 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xf0); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 724 | reg32 |= (1 << 5); |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 725 | pci_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 726 | |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 727 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x200); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 728 | reg32 &= ~(3 << 26); |
| 729 | reg32 |= (2 << 26); |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 730 | pci_write_config32(PCI_DEV(0, 0x01, 0), 0x200, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 731 | |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 732 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xe80); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 733 | if (i945_silicon_revision() >= 2) { |
| 734 | reg32 |= (1 << 12); |
| 735 | } else { |
| 736 | reg32 &= ~(1 << 12); |
| 737 | } |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 738 | pci_write_config32(PCI_DEV(0, 0x01, 0), 0xe80, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 739 | |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 740 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xeb4); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 741 | reg32 &= ~(1 << 31); |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 742 | pci_write_config32(PCI_DEV(0, 0x01, 0), 0xeb4, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 743 | |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 744 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xfc); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 745 | reg32 |= (1 << 31); |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 746 | pci_write_config32(PCI_DEV(0, 0x01, 0), 0xfc, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 747 | |
| 748 | if (i945_silicon_revision() >= 3) { |
| 749 | static const u32 reglist[] = { |
| 750 | 0xec0, 0xed4, 0xee8, 0xefc, 0xf10, 0xf24, |
| 751 | 0xf38, 0xf4c, 0xf60, 0xf74, 0xf88, 0xf9c, |
| 752 | 0xfb0, 0xfc4, 0xfd8, 0xfec |
| 753 | }; |
| 754 | |
| 755 | int i; |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 756 | for (i = 0; i < ARRAY_SIZE(reglist); i++) { |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 757 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), reglist[i]); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 758 | reg32 &= 0x0fffffff; |
| 759 | reg32 |= (2 << 28); |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 760 | pci_write_config32(PCI_DEV(0, 0x01, 0), reglist[i], reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 761 | } |
| 762 | } |
| 763 | |
| 764 | if (i945_silicon_revision() <= 2 ) { |
| 765 | /* Set voltage specific parameters */ |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 766 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xe80); |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 767 | reg32 &= (0xf << 4); /* Default case 1.05V */ |
Patrick Georgi | 3cb86de | 2014-09-29 20:42:33 +0200 | [diff] [blame] | 768 | if ((MCHBAR32(DFT_STRAP1) & (1 << 20)) == 0) { /* 1.50V */ |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 769 | reg32 |= (7 << 4); |
| 770 | } |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 771 | pci_write_config32(PCI_DEV(0, 0x01, 0), 0xe80, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 772 | } |
| 773 | |
| 774 | return; |
| 775 | |
| 776 | disable_pciexpress_x16_link: |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 777 | /* For now we just disable the x16 link */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 778 | printk(BIOS_DEBUG, "Disabling PCI Express x16 Link\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 779 | |
| 780 | MCHBAR16(UPMC1) |= (1 << 5) | (1 << 0); |
| 781 | |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 782 | reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1); |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 783 | reg16 |= (1 << 6); |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 784 | pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 785 | |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 786 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x224); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 787 | reg32 |= (1 << 8); |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 788 | pci_write_config32(PCI_DEV(0, 0x01, 0), 0x224, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 789 | |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 790 | reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1); |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 791 | reg16 &= ~(1 << 6); |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 792 | pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 793 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 794 | printk(BIOS_DEBUG, "Wait for link to enter detect state... "); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 795 | timeout = 0x7fffff; |
Patrick Georgi | d3060ed | 2014-08-10 15:19:45 +0200 | [diff] [blame] | 796 | for (reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS); |
Elyes HAOUAS | 7db506c | 2016-10-02 11:56:39 +0200 | [diff] [blame] | 797 | (reg32 & 0x000f0000) && --timeout;); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 798 | if (!timeout) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 799 | printk(BIOS_DEBUG, "timeout!\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 800 | else |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 801 | printk(BIOS_DEBUG, "ok\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 802 | |
| 803 | /* Finally: Disable the PCI config header */ |
| 804 | reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DEVEN); |
| 805 | reg16 &= ~DEVEN_D1F0; |
| 806 | pci_write_config16(PCI_DEV(0, 0x00, 0), DEVEN, reg16); |
| 807 | } |
| 808 | |
| 809 | static void i945_setup_root_complex_topology(void) |
| 810 | { |
| 811 | u32 reg32; |
| 812 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 813 | printk(BIOS_DEBUG, "Setting up Root Complex Topology\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 814 | /* Egress Port Root Topology */ |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 815 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 816 | reg32 = EPBAR32(EPESD); |
| 817 | reg32 &= 0xff00ffff; |
| 818 | reg32 |= (1 << 16); |
| 819 | EPBAR32(EPESD) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 820 | |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 821 | EPBAR32(EPLE1D) |= (1 << 16) | (1 << 0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 822 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 823 | EPBAR32(EPLE1A) = (uintptr_t)DEFAULT_DMIBAR; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 824 | |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 825 | EPBAR32(EPLE2D) |= (1 << 16) | (1 << 0); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 826 | |
| 827 | /* DMI Port Root Topology */ |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 828 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 829 | reg32 = DMIBAR32(DMILE1D); |
| 830 | reg32 &= 0x00ffffff; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 831 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 832 | reg32 &= 0xff00ffff; |
| 833 | reg32 |= (2 << 16); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 834 | |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 835 | reg32 |= (1 << 0); |
| 836 | DMIBAR32(DMILE1D) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 837 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 838 | DMIBAR32(DMILE1A) = (uintptr_t)DEFAULT_RCBA; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 839 | |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 840 | DMIBAR32(DMILE2D) |= (1 << 16) | (1 << 0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 841 | |
| 842 | DMIBAR32(DMILE2A) = DEFAULT_EPBAR; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 843 | |
| 844 | /* PCI Express x16 Port Root Topology */ |
| 845 | if (pci_read_config8(PCI_DEV(0, 0x00, 0), DEVEN) & DEVEN_D1F0) { |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 846 | pci_write_config32(PCI_DEV(0, 0x01, 0), 0x158, DEFAULT_EPBAR); |
| 847 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x150); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 848 | reg32 |= (1 << 0); |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 849 | pci_write_config32(PCI_DEV(0, 0x01, 0), 0x150, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 850 | } |
| 851 | } |
| 852 | |
| 853 | static void ich7_setup_root_complex_topology(void) |
| 854 | { |
| 855 | RCBA32(0x104) = 0x00000802; |
| 856 | RCBA32(0x110) = 0x00000001; |
| 857 | RCBA32(0x114) = 0x00000000; |
| 858 | RCBA32(0x118) = 0x00000000; |
| 859 | } |
| 860 | |
| 861 | static void ich7_setup_pci_express(void) |
| 862 | { |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 863 | RCBA32(CG) |= (1 << 0); |
| 864 | |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 865 | /* Initialize slot power limit for root ports */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 866 | pci_write_config32(PCI_DEV(0, 0x1c, 0), 0x54, 0x00000060); |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 867 | #if 0 |
| 868 | pci_write_config32(PCI_DEV(0, 0x1c, 4), 0x54, 0x00480ce0); |
| 869 | pci_write_config32(PCI_DEV(0, 0x1c, 5), 0x54, 0x00500ce0); |
| 870 | #endif |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 871 | |
| 872 | pci_write_config32(PCI_DEV(0, 0x1c, 0), 0xd8, 0x00110000); |
| 873 | } |
| 874 | |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 875 | void i945_early_initialization(void) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 876 | { |
| 877 | /* Print some chipset specific information */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 878 | switch (pci_read_config32(PCI_DEV(0, 0x00, 0), 0)) { |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 879 | case 0x27708086: /* 82945G/GZ/GC/P/PL */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 880 | i945_detect_chipset(); |
| 881 | break; |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 882 | case 0x27a08086: /* 945GME/GSE */ |
| 883 | case 0x27ac8086: /* 945GM/PM/GMS/GU/GT, 943/940GML */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 884 | i945m_detect_chipset(); |
| 885 | break; |
| 886 | } |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 887 | |
| 888 | /* Setup all BARs required for early PCIe and raminit */ |
| 889 | i945_setup_bars(); |
| 890 | |
| 891 | /* Change port80 to LPC */ |
| 892 | RCBA32(GCS) &= (~0x04); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 893 | |
| 894 | /* Just do it that way */ |
| 895 | RCBA32(0x2010) |= (1 << 10); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 896 | } |
| 897 | |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 898 | static void i945_prepare_resume(int s3resume) |
| 899 | { |
| 900 | int cbmem_was_initted; |
| 901 | |
| 902 | cbmem_was_initted = !cbmem_recovery(s3resume); |
| 903 | |
| 904 | /* If there is no high memory area, we didn't boot before, so |
| 905 | * this is not a resume. In that case we just create the cbmem toc. |
| 906 | */ |
| 907 | if (s3resume && cbmem_was_initted) { |
Kyösti Mälkki | e6b5a4f | 2016-06-17 22:52:04 +0300 | [diff] [blame] | 908 | acpi_prepare_for_resume(); |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 909 | |
| 910 | /* Magic for S3 resume */ |
| 911 | pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, |
| 912 | SKPAD_ACPI_S3_MAGIC); |
| 913 | } |
| 914 | } |
| 915 | |
| 916 | void i945_late_initialization(int s3resume) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 917 | { |
| 918 | i945_setup_egress_port(); |
| 919 | |
| 920 | ich7_setup_root_complex_topology(); |
| 921 | |
| 922 | ich7_setup_pci_express(); |
| 923 | |
| 924 | ich7_setup_dmi_rcrb(); |
| 925 | |
| 926 | i945_setup_dmi_rcrb(); |
| 927 | |
| 928 | i945_setup_pci_express_x16(); |
| 929 | |
| 930 | i945_setup_root_complex_topology(); |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 931 | |
| 932 | #if !CONFIG_HAVE_ACPI_RESUME |
| 933 | #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 |
| 934 | #if CONFIG_DEBUG_RAM_SETUP |
| 935 | sdram_dump_mchbar_registers(); |
| 936 | |
| 937 | { |
| 938 | /* This will not work if TSEG is in place! */ |
Paul Menzel | 9d3e131 | 2014-06-05 08:50:17 +0200 | [diff] [blame] | 939 | u32 tom = pci_read_config32(PCI_DEV(0, 2, 0), BSM); |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 940 | |
| 941 | printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); |
| 942 | ram_check(0x00000000, 0x000a0000); |
| 943 | ram_check(0x00100000, tom); |
| 944 | } |
| 945 | #endif |
| 946 | #endif |
| 947 | #endif |
| 948 | |
| 949 | MCHBAR16(SSKPD) = 0xCAFE; |
| 950 | |
| 951 | i945_prepare_resume(s3resume); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 952 | } |