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Patrick Georgi0588d192009-08-12 15:00:51 +00001##
Stefan Reinauer16f515a2010-01-20 18:44:30 +00002## This file is part of the coreboot project.
Patrick Georgi0588d192009-08-12 15:00:51 +00003##
Stefan Reinauer16f515a2010-01-20 18:44:30 +00004## Copyright (C) 2009-2010 coresystems GmbH
Patrick Georgi0588d192009-08-12 15:00:51 +00005##
Stefan Reinauer16f515a2010-01-20 18:44:30 +00006## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
15## You should have received a copy of the GNU General Public License
16## along with this program; if not, write to the Free Software
17## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Patrick Georgi0588d192009-08-12 15:00:51 +000018##
19
20mainmenu "Coreboot Configuration"
21
Uwe Hermannc04be932009-10-05 13:55:28 +000022menu "General setup"
23
Uwe Hermanna29ad5c2009-10-18 18:35:50 +000024config EXPERT
25 bool "Expert mode"
26 help
27 This allows you to select certain advanced configuration options.
28
29 Warning: Only enable this option if you really know what you are
30 doing! You have been warned!
31
Uwe Hermannc04be932009-10-05 13:55:28 +000032config LOCALVERSION
Uwe Hermann168b11b2009-10-07 16:15:40 +000033 string "Local version string"
Uwe Hermannc04be932009-10-05 13:55:28 +000034 help
35 Append an extra string to the end of the coreboot version.
36
Uwe Hermann168b11b2009-10-07 16:15:40 +000037 This can be useful if, for instance, you want to append the
38 respective board's hostname or some other identifying string to
39 the coreboot version number, so that you can easily distinguish
40 boot logs of different boards from each other.
41
Patrick Georgi4b8a2412010-02-09 19:35:16 +000042config CBFS_PREFIX
43 string "CBFS prefix to use"
44 default "fallback"
45 help
46 Select the prefix to all files put into the image. It's "fallback"
47 by default, "normal" is a common alternative.
48
Patrick Georgi020f51f2010-03-14 21:25:03 +000049config SCANBUILD_ENABLE
50 bool "build with scan-build for static analysis"
51 default n
52 help
53 Changes the build process to scan-build is used.
54 Requires scan-build in path.
55
56config SCANBUILD_REPORT_LOCATION
57 string "directory to put scan-build report in"
58 default ""
59 depends on SCANBUILD_ENABLE
60 help
61 Where the scan-build report should be stored
62
Uwe Hermannc04be932009-10-05 13:55:28 +000063endmenu
64
Patrick Georgi0588d192009-08-12 15:00:51 +000065source src/mainboard/Kconfig
66source src/arch/i386/Kconfig
Uwe Hermann63a8f2a2009-10-26 21:42:13 +000067
68menu "Chipset"
69
70comment "CPU"
Patrick Georgi0588d192009-08-12 15:00:51 +000071source src/cpu/Kconfig
Uwe Hermann63a8f2a2009-10-26 21:42:13 +000072comment "Northbridge"
Timothy Pearson55cf7bc2010-03-01 10:30:08 +000073
Uwe Hermann2bb4acf2010-03-01 17:19:55 +000074menu "HyperTransport setup"
Timothy Pearson55cf7bc2010-03-01 10:30:08 +000075 depends on (NORTHBRIDGE_AMD_AMDK8 || NORTHBRIDGE_AMD_AMDFAM10) && EXPERT
76
77choice
Uwe Hermann2bb4acf2010-03-01 17:19:55 +000078 prompt "HyperTransport frequency"
Timothy Pearson55cf7bc2010-03-01 10:30:08 +000079 default LIMIT_HT_SPEED_AUTO
80 help
Uwe Hermann2bb4acf2010-03-01 17:19:55 +000081 This option sets the maximum permissible HyperTransport link
82 frequency.
83
84 Use of this option will only limit the autodetected HT frequency.
85 It will not (and cannot) increase the frequency beyond the
86 autodetected limits.
87
88 This is primarily used to work around poorly designed or laid out
89 HT traces on certain motherboards.
Timothy Pearson55cf7bc2010-03-01 10:30:08 +000090
91config LIMIT_HT_SPEED_200
92 bool "Limit HT frequency to 200MHz"
93config LIMIT_HT_SPEED_400
94 bool "Limit HT frequency to 400MHz"
95config LIMIT_HT_SPEED_600
96 bool "Limit HT frequency to 600MHz"
97config LIMIT_HT_SPEED_800
98 bool "Limit HT frequency to 800MHz"
99config LIMIT_HT_SPEED_1000
100 bool "Limit HT frequency to 1.0GHz"
101config LIMIT_HT_SPEED_1200
102 bool "Limit HT frequency to 1.2GHz"
103config LIMIT_HT_SPEED_1400
104 bool "Limit HT frequency to 1.4GHz"
105config LIMIT_HT_SPEED_1600
106 bool "Limit HT frequency to 1.6GHz"
107config LIMIT_HT_SPEED_1800
Uwe Hermann2bb4acf2010-03-01 17:19:55 +0000108 bool "Limit HT frequency to 1.8GHz"
Timothy Pearson55cf7bc2010-03-01 10:30:08 +0000109config LIMIT_HT_SPEED_2000
Uwe Hermann2bb4acf2010-03-01 17:19:55 +0000110 bool "Limit HT frequency to 2.0GHz"
Timothy Pearson55cf7bc2010-03-01 10:30:08 +0000111config LIMIT_HT_SPEED_2200
Uwe Hermann2bb4acf2010-03-01 17:19:55 +0000112 bool "Limit HT frequency to 2.2GHz"
Timothy Pearson55cf7bc2010-03-01 10:30:08 +0000113config LIMIT_HT_SPEED_2400
Uwe Hermann2bb4acf2010-03-01 17:19:55 +0000114 bool "Limit HT frequency to 2.4GHz"
Timothy Pearson55cf7bc2010-03-01 10:30:08 +0000115config LIMIT_HT_SPEED_2600
Uwe Hermann2bb4acf2010-03-01 17:19:55 +0000116 bool "Limit HT frequency to 2.6GHz"
Timothy Pearson55cf7bc2010-03-01 10:30:08 +0000117config LIMIT_HT_SPEED_AUTO
118 bool "Autodetect HT frequency"
119endchoice
120
121choice
Uwe Hermann2bb4acf2010-03-01 17:19:55 +0000122 prompt "HyperTransport downlink width"
Timothy Pearson55cf7bc2010-03-01 10:30:08 +0000123 default LIMIT_HT_DOWN_WIDTH_16
124 help
Uwe Hermann2bb4acf2010-03-01 17:19:55 +0000125 This option sets the maximum permissible HyperTransport
126 downlink width.
127
128 Use of this option will only limit the autodetected HT width.
129 It will not (and cannot) increase the width beyond the autodetected
130 limits.
131
132 This is primarily used to work around poorly designed or laid out HT
133 traces on certain motherboards.
Timothy Pearson55cf7bc2010-03-01 10:30:08 +0000134
135config LIMIT_HT_DOWN_WIDTH_8
136 bool "8 bits"
137config LIMIT_HT_DOWN_WIDTH_16
138 bool "16 bits"
139endchoice
140
141choice
Uwe Hermann2bb4acf2010-03-01 17:19:55 +0000142 prompt "HyperTransport uplink width"
Timothy Pearson55cf7bc2010-03-01 10:30:08 +0000143 default LIMIT_HT_UP_WIDTH_16
144 help
Uwe Hermann2bb4acf2010-03-01 17:19:55 +0000145 This option sets the maximum permissible HyperTransport
146 uplink width.
147
148 Use of this option will only limit the autodetected HT width.
149 It will not (and cannot) increase the width beyond the autodetected
150 limits.
151
152 This is primarily used to work around poorly designed or laid out HT
153 traces on certain motherboards.
Timothy Pearson55cf7bc2010-03-01 10:30:08 +0000154
155config LIMIT_HT_UP_WIDTH_8
156 bool "8 bits"
157config LIMIT_HT_UP_WIDTH_16
158 bool "16 bits"
159endchoice
160
161endmenu
162
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000163source src/northbridge/Kconfig
164comment "Southbridge"
165source src/southbridge/Kconfig
166comment "Super I/O"
167source src/superio/Kconfig
168comment "Devices"
169source src/devices/Kconfig
170
171endmenu
Patrick Georgi0588d192009-08-12 15:00:51 +0000172
Patrick Georgi0588d192009-08-12 15:00:51 +0000173config PCI_BUS_SEGN_BITS
Myles Watson74fb8f22009-09-24 15:09:11 +0000174 int
175 default 0
Patrick Georgi892b0912009-09-24 09:03:06 +0000176
Patrick Georgi0588d192009-08-12 15:00:51 +0000177config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000178 hex
Uwe Hermann748475b2009-10-09 11:47:21 +0000179 default 0x0
Patrick Georgi0588d192009-08-12 15:00:51 +0000180
181config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000182 hex
Uwe Hermann748475b2009-10-09 11:47:21 +0000183 default 0x0
Patrick Georgi0588d192009-08-12 15:00:51 +0000184
185config CPU_ADDR_BITS
186 int
187 default 36
188
189config XIP_ROM_BASE
190 hex
191 default 0xfffe0000
192
193config XIP_ROM_SIZE
194 hex
195 default 0x20000
196
197config LB_CKS_RANGE_START
198 int
199 default 49
200
201config LB_CKS_RANGE_END
202 int
203 default 125
204
205config LB_CKS_LOC
206 int
207 default 126
208
209config LOGICAL_CPUS
Myles Watson45bb25f2009-09-22 18:49:08 +0000210 bool
211 default y
Patrick Georgi0588d192009-08-12 15:00:51 +0000212
213config PCI_ROM_RUN
Patrick Georgi698c0e0e2009-08-25 17:38:24 +0000214 bool
215 default n
Patrick Georgi0588d192009-08-12 15:00:51 +0000216
Patrick Georgi0588d192009-08-12 15:00:51 +0000217config HEAP_SIZE
218 hex
Myles Watson04000f42009-10-16 19:12:49 +0000219 default 0x4000
Patrick Georgi0588d192009-08-12 15:00:51 +0000220
Patrick Georgi0588d192009-08-12 15:00:51 +0000221config DEBUG
222 bool
223 default n
224
225config USE_PRINTK_IN_CAR
226 bool
227 default n
228
229config USE_OPTION_TABLE
230 bool
231 default n
232
233config MAX_CPUS
234 int
235 default 1
236
237config MMCONF_SUPPORT_DEFAULT
238 bool
239 default n
240
241config MMCONF_SUPPORT
242 bool
243 default n
244
Myles Watson0f61a4f2009-10-16 16:32:57 +0000245config RAMTOP
Myles Watson3db199c2009-10-12 22:39:08 +0000246 hex
Myles Watson0f61a4f2009-10-16 16:32:57 +0000247 default 0x200000
Patrick Georgi0588d192009-08-12 15:00:51 +0000248
Patrick Georgi91ff0df2009-10-09 12:32:52 +0000249config ATI_RAGE_XL
250 bool
Patrick Georgi91ff0df2009-10-09 12:32:52 +0000251
Patrick Georgi0588d192009-08-12 15:00:51 +0000252source src/console/Kconfig
253
254config HAVE_ACPI_RESUME
255 bool
256 default n
257
258config ACPI_SSDTX_NUM
259 int
260 default 0
261
Patrick Georgi0588d192009-08-12 15:00:51 +0000262config HAVE_FALLBACK_BOOT
263 bool
264 default y
265
266config USE_FALLBACK_IMAGE
267 bool
268 default y
269
Patrick Georgi37ea3412009-10-03 21:04:13 +0000270config HAVE_FAILOVER_BOOT
271 bool
272 default n
273
274config USE_FAILOVER_IMAGE
275 bool
276 default n
277
Patrick Georgi0588d192009-08-12 15:00:51 +0000278config HAVE_HARD_RESET
279 bool
Patrick Georgi37bdb872010-02-27 08:39:04 +0000280 default y if BOARD_HAS_HARD_RESET
Uwe Hermann748475b2009-10-09 11:47:21 +0000281 default n
Patrick Georgi37bdb872010-02-27 08:39:04 +0000282 help
283 This variable specifies whether a given board has a hard_reset
284 function, no matter if it's provided by board code or chipset code.
285
Patrick Georgi0588d192009-08-12 15:00:51 +0000286config HAVE_INIT_TIMER
287 bool
Patrick Georgi1f807fd2010-01-04 20:09:27 +0000288 default n if UDELAY_IO
Myles Watsond73c1b52009-10-26 15:14:07 +0000289 default y
Patrick Georgi0588d192009-08-12 15:00:51 +0000290
291config HAVE_MAINBOARD_RESOURCES
292 bool
293 default n
294
Patrick Georgi0588d192009-08-12 15:00:51 +0000295config HAVE_OPTION_TABLE
296 bool
297 default y
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000298 help
299 This variable specifies whether a given board has a cmos.layout
300 file containing NVRAM/CMOS bit definitions.
301 It defaults to 'y' but can be changed to 'n' in mainboard/*/Kconfig.
Patrick Georgi0588d192009-08-12 15:00:51 +0000302
Patrick Georgi0588d192009-08-12 15:00:51 +0000303config PIRQ_ROUTE
304 bool
305 default n
306
307config HAVE_SMI_HANDLER
308 bool
309 default n
310
311config PCI_IO_CFG_EXT
312 bool
313 default n
314
315config IOAPIC
316 bool
317 default n
318
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000319# TODO: Can probably be removed once all chipsets have kconfig options for it.
Uwe Hermann70b0cf22009-10-04 17:15:39 +0000320config VIDEO_MB
321 int
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000322 default 0
Uwe Hermann70b0cf22009-10-04 17:15:39 +0000323
Myles Watson45bb25f2009-09-22 18:49:08 +0000324config USE_WATCHDOG_ON_BOOT
325 bool
326 default n
327
328config VGA
329 bool
330 default n
331 help
332 Build board-specific VGA code.
333
334config GFXUMA
335 bool
Myles Watsond73c1b52009-10-26 15:14:07 +0000336 default n
Myles Watson45bb25f2009-09-22 18:49:08 +0000337 help
338 Enable Unified Memory Architecture for graphics.
339
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000340# TODO
341# menu "Drivers"
Uwe Hermann168b11b2009-10-07 16:15:40 +0000342#
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000343# endmenu
Patrick Georgi0588d192009-08-12 15:00:51 +0000344
Myles Watsond73c1b52009-10-26 15:14:07 +0000345#TODO Remove this option or make it useful.
346config HAVE_LOW_TABLES
347 bool
348 default y
349 help
350 This Option is unused in the code. Since two boards try to set it to
351 'n', they may be broken. We either need to make the option useful or
352 get rid of it. The broken boards are:
353 asus/m2v-mx_se
354 supermicro/h8dme
355
356config HAVE_HIGH_TABLES
357 bool
Stefan Reinauer13f2bb02010-02-25 13:45:08 +0000358 default y
Myles Watsond73c1b52009-10-26 15:14:07 +0000359 help
360 This variable specifies whether a given northbridge has high table
361 support.
362 It is set in northbridge/*/Kconfig.
363 Whether or not the high tables are actually written by coreboot is
364 configurable by the user via WRITE_HIGH_TABLES.
365
Myles Watsonb8e20272009-10-15 13:35:47 +0000366config HAVE_ACPI_TABLES
367 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000368 help
369 This variable specifies whether a given board has ACPI table support.
370 It is usually set in mainboard/*/Kconfig.
371 Whether or not the ACPI tables are actually generated by coreboot
372 is configurable by the user via GENERATE_ACPI_TABLES.
Myles Watsonb8e20272009-10-15 13:35:47 +0000373
374config HAVE_MP_TABLE
375 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000376 help
377 This variable specifies whether a given board has MP table support.
378 It is usually set in mainboard/*/Kconfig.
379 Whether or not the MP table is actually generated by coreboot
380 is configurable by the user via GENERATE_MP_TABLE.
Myles Watsonb8e20272009-10-15 13:35:47 +0000381
382config HAVE_PIRQ_TABLE
383 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000384 help
385 This variable specifies whether a given board has PIRQ table support.
386 It is usually set in mainboard/*/Kconfig.
387 Whether or not the PIRQ table is actually generated by coreboot
388 is configurable by the user via GENERATE_PIRQ_TABLE.
Myles Watsonb8e20272009-10-15 13:35:47 +0000389
Myles Watsond73c1b52009-10-26 15:14:07 +0000390#These Options are here to avoid "undefined" warnings.
391#The actual selection and help texts are in the following menu.
392
393config GENERATE_ACPI_TABLES
Myles Watsonb8e20272009-10-15 13:35:47 +0000394 bool
Myles Watsond73c1b52009-10-26 15:14:07 +0000395 default HAVE_ACPI_TABLES
396
397config GENERATE_MP_TABLE
398 bool
399 default HAVE_MP_TABLE
400
401config GENERATE_PIRQ_TABLE
402 bool
403 default HAVE_PIRQ_TABLE
404
405config WRITE_HIGH_TABLES
406 bool
407 default HAVE_HIGH_TABLES
Myles Watsonb8e20272009-10-15 13:35:47 +0000408
Uwe Hermann168b11b2009-10-07 16:15:40 +0000409menu "System tables"
Myles Watson45bb25f2009-09-22 18:49:08 +0000410
Myles Watsonb8e20272009-10-15 13:35:47 +0000411config WRITE_HIGH_TABLES
Myles Watson45bb25f2009-09-22 18:49:08 +0000412 bool "Write 'high' tables to avoid being overwritten in F segment"
Myles Watsonb8e20272009-10-15 13:35:47 +0000413 depends on HAVE_HIGH_TABLES
Myles Watson45bb25f2009-09-22 18:49:08 +0000414 default y
415
416config MULTIBOOT
Uwe Hermann168b11b2009-10-07 16:15:40 +0000417 bool "Generate Multiboot tables (for GRUB2)"
Ronald G. Minnich7f91d922009-11-09 17:56:47 +0000418 default y
Myles Watson45bb25f2009-09-22 18:49:08 +0000419
Myles Watsonb8e20272009-10-15 13:35:47 +0000420config GENERATE_ACPI_TABLES
421 depends on HAVE_ACPI_TABLES
Myles Watson45bb25f2009-09-22 18:49:08 +0000422 bool "Generate ACPI tables"
Myles Watsonb8e20272009-10-15 13:35:47 +0000423 default y
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000424 help
425 Generate ACPI tables for this board.
426
427 If unsure, say Y.
Myles Watson45bb25f2009-09-22 18:49:08 +0000428
Myles Watsonb8e20272009-10-15 13:35:47 +0000429config GENERATE_MP_TABLE
430 depends on HAVE_MP_TABLE
Myles Watson45bb25f2009-09-22 18:49:08 +0000431 bool "Generate an MP table"
Myles Watsonb8e20272009-10-15 13:35:47 +0000432 default y
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000433 help
434 Generate an MP table (conforming to the Intel MultiProcessor
435 specification 1.4) for this board.
436
437 If unsure, say Y.
Myles Watson45bb25f2009-09-22 18:49:08 +0000438
Myles Watsonb8e20272009-10-15 13:35:47 +0000439config GENERATE_PIRQ_TABLE
440 depends on HAVE_PIRQ_TABLE
Myles Watson45bb25f2009-09-22 18:49:08 +0000441 bool "Generate a PIRQ table"
Myles Watsonb8e20272009-10-15 13:35:47 +0000442 default y
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000443 help
444 Generate a PIRQ table for this board.
445
446 If unsure, say Y.
Myles Watson45bb25f2009-09-22 18:49:08 +0000447
448endmenu
449
Patrick Georgi0588d192009-08-12 15:00:51 +0000450menu "Payload"
451
Patrick Georgi0588d192009-08-12 15:00:51 +0000452choice
Uwe Hermann168b11b2009-10-07 16:15:40 +0000453 prompt "Add a payload"
Patrick Georgi0588d192009-08-12 15:00:51 +0000454 default PAYLOAD_NONE
455
Uwe Hermann168b11b2009-10-07 16:15:40 +0000456config PAYLOAD_NONE
457 bool "None"
458 help
459 Select this option if you want to create an "empty" coreboot
460 ROM image for a certain mainboard, i.e. a coreboot ROM image
461 which does not yet contain a payload.
462
463 For such an image to be useful, you have to use 'cbfstool'
464 to add a payload to the ROM image later.
465
Patrick Georgi0588d192009-08-12 15:00:51 +0000466config PAYLOAD_ELF
Uwe Hermann168b11b2009-10-07 16:15:40 +0000467 bool "An ELF executable payload"
Patrick Georgi0588d192009-08-12 15:00:51 +0000468 help
469 Select this option if you have a payload image (an ELF file)
470 which coreboot should run as soon as the basic hardware
471 initialization is completed.
472
473 You will be able to specify the location and file name of the
474 payload image later.
Patrick Georgi0588d192009-08-12 15:00:51 +0000475
476endchoice
477
Patrick Georgi0588d192009-08-12 15:00:51 +0000478config FALLBACK_PAYLOAD_FILE
Cristi Magherusanb5034d42009-08-17 14:47:32 +0000479 string "Payload path and filename"
Patrick Georgi0588d192009-08-12 15:00:51 +0000480 depends on PAYLOAD_ELF
481 default "payload.elf"
482 help
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000483 The path and filename of the ELF executable file to use as payload.
Patrick Georgi0588d192009-08-12 15:00:51 +0000484
Uwe Hermann168b11b2009-10-07 16:15:40 +0000485# TODO: Defined if no payload? Breaks build?
486config COMPRESSED_PAYLOAD_LZMA
487 bool "Use LZMA compression for payloads"
488 default y
489 depends on PAYLOAD_ELF
490 help
491 In order to reduce the size payloads take up in the ROM chip
492 coreboot can compress them using the LZMA algorithm.
493
Myles Watson04000f42009-10-16 19:12:49 +0000494config COMPRESSED_PAYLOAD_NRV2B
Peter Stuged7b37b02009-10-17 03:00:04 +0000495 bool
Myles Watson04000f42009-10-16 19:12:49 +0000496 default n
497
Peter Stugea758ca22009-09-17 16:21:31 +0000498endmenu
499
500menu "VGA BIOS"
501
502config VGA_BIOS
503 bool "Add a VGA BIOS image"
504 help
505 Select this option if you have a VGA BIOS image that you would
506 like to add to your ROM.
507
508 You will be able to specify the location and file name of the
509 image later.
510
Cristi Magherusan488c36c2009-08-17 14:46:13 +0000511config FALLBACK_VGA_BIOS_FILE
512 string "VGA BIOS path and filename"
513 depends on VGA_BIOS
514 default "vgabios.bin"
515 help
516 The path and filename of the file to use as VGA BIOS.
517
518config FALLBACK_VGA_BIOS_ID
Uwe Hermann81b3c0a2009-10-30 12:56:59 +0000519 string "VGA device PCI IDs"
Cristi Magherusan488c36c2009-08-17 14:46:13 +0000520 depends on VGA_BIOS
521 default "1106,3230"
522 help
Uwe Hermann168b11b2009-10-07 16:15:40 +0000523 The comma-separated PCI vendor and device ID that would associate
524 your VGA BIOS to your video card.
525
526 Example: 1106,3230
527
528 In the above example 1106 is the PCI vendor ID (in hex, but without
529 the "0x" prefix) and 3230 specifies the PCI device ID of the
530 video card (also in hex, without "0x" prefix).
Cristi Magherusan488c36c2009-08-17 14:46:13 +0000531
Stefan Reinauer800379f2010-03-01 08:34:19 +0000532config INTEL_MBI
533 bool "Add an MBI image"
534 depends on NORTHBRIDGE_INTEL_I82830
535 help
536 Select this option if you have an Intel MBI image that you would
537 like to add to your ROM.
538
539 You will be able to specify the location and file name of the
540 image later.
541
542config FALLBACK_MBI_FILE
543 string "Intel MBI path and filename"
544 depends on INTEL_MBI
545 default "mbi.bin"
546 help
547 The path and filename of the file to use as VGA BIOS.
548
549endmenu
550
551menu "Bootsplash"
552 depends on PCI_OPTION_ROM_RUN_YABEL
553
554config BOOTSPLASH
555 prompt "Show graphical bootsplash"
556 bool
557 depends on PCI_OPTION_ROM_RUN_YABEL
558 help
559 This option shows a graphical bootsplash screen. The grapics are
560 loaded from the CBFS file bootsplash.jpg.
561
562config FALLBACK_BOOTSPLASH_FILE
563 string "Bootsplash path and filename"
564 depends on BOOTSPLASH
565 default "bootsplash.jpg"
566 help
567 The path and filename of the file to use as graphical bootsplash
568 screen. The file format has to be jpg.
569
570# TODO: Turn this into a "choice".
571config FRAMEBUFFER_VESA_MODE
572 prompt "VESA framebuffer video mode"
573 hex
574 default 0x117
575 depends on BOOTSPLASH
576 help
577 This option sets the resolution used for the coreboot framebuffer and
578 bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will
579 some day make this a "choice".
580
581config COREBOOT_KEEP_FRAMEBUFFER
582 prompt "Keep VESA framebuffer"
583 bool
584 depends on BOOTSPLASH
585 help
586 This option keeps the framebuffer mode set after coreboot finishes
587 execution. If this option is enabled, coreboot will pass a
588 framebuffer entry in its coreboot table and the payload will need a
589 framebuffer driver. If this option is disabled, coreboot will switch
590 back to text mode before handing control to a payload.
591
Patrick Georgi0588d192009-08-12 15:00:51 +0000592endmenu
593
Uwe Hermann168b11b2009-10-07 16:15:40 +0000594menu "Debugging"
595
596# TODO: Better help text and detailed instructions.
Patrick Georgi0588d192009-08-12 15:00:51 +0000597config GDB_STUB
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000598 bool "GDB debugging support"
Patrick Georgi0588d192009-08-12 15:00:51 +0000599 default y
600 help
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000601 If enabled, you will be able to set breakpoints for gdb debugging.
602 See src/arch/i386/lib/c_start.S for details.
Patrick Georgi0588d192009-08-12 15:00:51 +0000603
Uwe Hermann01ce6012010-03-05 10:03:50 +0000604config DEBUG_RAM_SETUP
605 bool "Output verbose RAM init debug messages"
606 default n
607 depends on (NORTHBRIDGE_AMD_AMDFAM10 \
608 || NORTHBRIDGE_AMD_AMDK8 \
609 || NORTHBRIDGE_VIA_CN700 \
610 || NORTHBRIDGE_VIA_CX700 \
611 || NORTHBRIDGE_VIA_VX800 \
612 || NORTHBRIDGE_INTEL_E7501 \
613 || NORTHBRIDGE_INTEL_I440BX \
614 || NORTHBRIDGE_INTEL_I82810 \
615 || NORTHBRIDGE_INTEL_I82830 \
616 || NORTHBRIDGE_INTEL_I945)
617 help
618 This option enables additional RAM init related debug messages.
619 It is recommended to enable this when debugging issues on your
620 board which might be RAM init related.
621
622 Note: This option will increase the size of the coreboot image.
623
624 If unsure, say N.
625
626config DEBUG_SMBUS
627 bool "Output verbose SMBus debug messages"
628 default n
629 depends on (SOUTHBRIDGE_VIA_VT8237R \
630 || NORTHBRIDGE_VIA_VX800 \
631 || NORTHBRIDGE_VIA_CX700 \
632 || NORTHBRIDGE_AMD_AMDK8)
633 help
634 This option enables additional SMBus (and SPD) debug messages.
635
636 Note: This option will increase the size of the coreboot image.
637
638 If unsure, say N.
639
640config DEBUG_SMI
641 bool "Output verbose SMI debug messages"
642 default n
643 depends on HAVE_SMI_HANDLER
644 help
645 This option enables additional SMI related debug messages.
646
647 Note: This option will increase the size of the coreboot image.
648
649 If unsure, say N.
650
651config X86EMU_DEBUG
652 bool "Output verbose x86emu debug messages"
653 default n
654 depends on PCI_OPTION_ROM_RUN_YABEL
655 help
656 This option enables additional x86emu related debug messages.
657
658 Note: This option will increase the size of the coreboot image.
659
660 If unsure, say N.
661
662config X86EMU_DEBUG_JMP
663 bool "Trace JMP/RETF"
664 default n
665 depends on X86EMU_DEBUG
666 help
667 Print information about JMP and RETF opcodes from x86emu.
668
669 Note: This option will increase the size of the coreboot image.
670
671 If unsure, say N.
672
673config X86EMU_DEBUG_TRACE
674 bool "Trace all opcodes"
675 default n
676 depends on X86EMU_DEBUG
677 help
678 Print _all_ opcodes that are executed by x86emu.
679
680 WARNING: This will produce a LOT of output and take a long time.
681
682 Note: This option will increase the size of the coreboot image.
683
684 If unsure, say N.
685
686config X86EMU_DEBUG_PNP
687 bool "Log Plug&Play accesses"
688 default n
689 depends on X86EMU_DEBUG
690 help
691 Print Plug And Play accesses made by option ROMs.
692
693 Note: This option will increase the size of the coreboot image.
694
695 If unsure, say N.
696
697config X86EMU_DEBUG_DISK
698 bool "Log Disk I/O"
699 default n
700 depends on X86EMU_DEBUG
701 help
702 Print Disk I/O related messages.
703
704 Note: This option will increase the size of the coreboot image.
705
706 If unsure, say N.
707
708config X86EMU_DEBUG_PMM
709 bool "Log PMM"
710 default n
711 depends on X86EMU_DEBUG
712 help
713 Print messages related to POST Memory Manager (PMM).
714
715 Note: This option will increase the size of the coreboot image.
716
717 If unsure, say N.
718
719
720config X86EMU_DEBUG_VBE
721 bool "Debug VESA BIOS Extensions"
722 default n
723 depends on X86EMU_DEBUG
724 help
725 Print messages related to VESA BIOS Extension (VBE) functions.
726
727 Note: This option will increase the size of the coreboot image.
728
729 If unsure, say N.
730
731config X86EMU_DEBUG_INT10
732 bool "Redirect INT10 output to console"
733 default n
734 depends on X86EMU_DEBUG
735 help
736 Let INT10 (i.e. character output) calls print messages to debug output.
737
738 Note: This option will increase the size of the coreboot image.
739
740 If unsure, say N.
741
742config X86EMU_DEBUG_INTERRUPTS
743 bool "Log intXX calls"
744 default n
745 depends on X86EMU_DEBUG
746 help
747 Print messages related to interrupt handling.
748
749 Note: This option will increase the size of the coreboot image.
750
751 If unsure, say N.
752
753config X86EMU_DEBUG_CHECK_VMEM_ACCESS
754 bool "Log special memory accesses"
755 default n
756 depends on X86EMU_DEBUG
757 help
758 Print messages related to accesses to certain areas of the virtual
759 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
760
761 Note: This option will increase the size of the coreboot image.
762
763 If unsure, say N.
764
765config X86EMU_DEBUG_MEM
766 bool "Log all memory accesses"
767 default n
768 depends on X86EMU_DEBUG
769 help
770 Print memory accesses made by option ROM.
771 Note: This also includes accesses to fetch instructions.
772
773 Note: This option will increase the size of the coreboot image.
774
775 If unsure, say N.
776
777config X86EMU_DEBUG_IO
778 bool "Log IO accesses"
779 default n
780 depends on X86EMU_DEBUG
781 help
782 Print I/O accesses made by option ROM.
783
784 Note: This option will increase the size of the coreboot image.
785
786 If unsure, say N.
787
Stefan Reinauer5c503922010-03-13 22:07:15 +0000788config LLSHELL
789 bool "Built-in low-level shell"
790 default n
791 help
792 If enabled, you will have a low level shell to examine your machine.
793 Put llshell() in your (romstage) code to start the shell.
794 See src/arch/i386/llshell/llshell.inc for details.
795
Uwe Hermann168b11b2009-10-07 16:15:40 +0000796endmenu
797
Myles Watson8f74c582009-10-20 16:10:04 +0000798config LIFT_BSP_APIC_ID
799 bool
800 default n
Myles Watsond73c1b52009-10-26 15:14:07 +0000801
802# These probably belong somewhere else, but they are needed somewhere.
803config AP_CODE_IN_CAR
804 bool
805 default n
806
807config USE_INIT
808 bool
809 default n
810
811config ENABLE_APIC_EXT_ID
812 bool
813 default n
Myles Watson2e672732009-11-12 16:38:03 +0000814
815config WARNINGS_ARE_ERRORS
816 bool
817 default n
Patrick Georgi436f99b2009-11-27 16:55:13 +0000818
819config ID_SECTION_OFFSET
820 hex
821 default 0x10
Patrick Georgicc669262010-03-14 21:31:05 +0000822
823source src/Kconfig.deprecated_options