Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Andrey Petrov | 42c4e88 | 2016-02-25 14:17:45 -0800 | [diff] [blame] | 2 | |
Arthur Heymans | fdf6d12 | 2022-05-17 13:07:30 +0200 | [diff] [blame] | 3 | #include <arch/null_breakpoint.h> |
Kyösti Mälkki | 4949a3d | 2021-01-09 20:38:43 +0200 | [diff] [blame] | 4 | #include <bootsplash.h> |
Andrey Petrov | 42c4e88 | 2016-02-25 14:17:45 -0800 | [diff] [blame] | 5 | #include <cbfs.h> |
Aaron Durbin | 32ac018 | 2016-07-18 00:35:42 -0500 | [diff] [blame] | 6 | #include <cbmem.h> |
| 7 | #include <commonlib/fsp.h> |
Subrata Banik | 44ffb5d | 2018-05-24 10:51:29 +0530 | [diff] [blame] | 8 | #include <commonlib/stdlib.h> |
Andrey Petrov | 42c4e88 | 2016-02-25 14:17:45 -0800 | [diff] [blame] | 9 | #include <console/console.h> |
| 10 | #include <fsp/api.h> |
| 11 | #include <fsp/util.h> |
Aaron Durbin | 32ac018 | 2016-07-18 00:35:42 -0500 | [diff] [blame] | 12 | #include <program_loading.h> |
Keith Short | c58e3bd | 2019-05-10 11:14:31 -0600 | [diff] [blame] | 13 | #include <soc/intel/common/vbt.h> |
Brandon Breitenstein | c6ec8dd | 2016-11-17 12:23:04 -0800 | [diff] [blame] | 14 | #include <stage_cache.h> |
Andrey Petrov | 42c4e88 | 2016-02-25 14:17:45 -0800 | [diff] [blame] | 15 | #include <string.h> |
Alexandru Gagniuc | 010225c | 2016-05-06 08:22:45 -0700 | [diff] [blame] | 16 | #include <timestamp.h> |
Elyes HAOUAS | bd1683d | 2019-05-15 21:05:37 +0200 | [diff] [blame] | 17 | #include <types.h> |
Patrick Rudolph | 40beb36 | 2020-12-01 10:08:38 +0100 | [diff] [blame] | 18 | #include <mode_switch.h> |
Andrey Petrov | 42c4e88 | 2016-02-25 14:17:45 -0800 | [diff] [blame] | 19 | |
| 20 | struct fsp_header fsps_hdr; |
| 21 | |
Subrata Banik | 33d9c4a | 2020-05-26 18:26:54 +0530 | [diff] [blame] | 22 | struct fsp_multi_phase_get_number_of_phases_params { |
| 23 | uint32_t number_of_phases; |
| 24 | uint32_t phases_executed; |
| 25 | }; |
| 26 | |
| 27 | /* Callbacks for SoC/Mainboard specific overrides */ |
| 28 | void __weak platform_fsp_multi_phase_init_cb(uint32_t phase_index) |
| 29 | { |
| 30 | /* Leave for the SoC/Mainboard to implement if necessary. */ |
| 31 | } |
| 32 | |
Subrata Banik | 33d9c4a | 2020-05-26 18:26:54 +0530 | [diff] [blame] | 33 | /* FSP Specification < 2.2 has only 1 stage like FspSiliconInit. FSP specification >= 2.2 |
| 34 | * has multiple stages as below. |
| 35 | */ |
| 36 | enum fsp_silicon_init_phases { |
| 37 | FSP_SILICON_INIT_API, |
| 38 | FSP_MULTI_PHASE_SI_INIT_GET_NUMBER_OF_PHASES_API, |
| 39 | FSP_MULTI_PHASE_SI_INIT_EXECUTE_PHASE_API |
| 40 | }; |
| 41 | |
| 42 | static void fsps_return_value_handler(enum fsp_silicon_init_phases phases, uint32_t status) |
| 43 | { |
| 44 | uint8_t postcode; |
| 45 | |
| 46 | /* Handle any reset request returned by FSP-S APIs */ |
| 47 | fsp_handle_reset(status); |
| 48 | |
| 49 | if (status == FSP_SUCCESS) |
| 50 | return; |
| 51 | /* Handle all other errors returned by FSP-S APIs */ |
| 52 | /* Assume video failure if attempted to initialize graphics */ |
| 53 | if (CONFIG(RUN_FSP_GOP) && vbt_get()) |
| 54 | postcode = POST_VIDEO_FAILURE; |
| 55 | else |
| 56 | postcode = POST_HW_INIT_FAILURE; /* else generic */ |
| 57 | |
| 58 | switch (phases) { |
| 59 | case FSP_SILICON_INIT_API: |
| 60 | die_with_post_code(postcode, "FspSiliconInit returned with error 0x%08x\n", |
| 61 | status); |
| 62 | break; |
| 63 | case FSP_MULTI_PHASE_SI_INIT_GET_NUMBER_OF_PHASES_API: |
| 64 | printk(BIOS_SPEW, "FspMultiPhaseSiInit NumberOfPhases returned 0x%08x\n", |
| 65 | status); |
| 66 | break; |
| 67 | case FSP_MULTI_PHASE_SI_INIT_EXECUTE_PHASE_API: |
| 68 | printk(BIOS_SPEW, "FspMultiPhaseSiInit ExecutePhase returned 0x%08x\n", |
| 69 | status); |
| 70 | break; |
| 71 | default: |
| 72 | break; |
| 73 | } |
| 74 | } |
| 75 | |
Subrata Banik | 298b359 | 2021-09-14 12:38:08 +0530 | [diff] [blame] | 76 | bool fsp_is_multi_phase_init_enabled(void) |
| 77 | { |
| 78 | return CONFIG(FSPS_USE_MULTI_PHASE_INIT) && |
Julian Schroeder | 8a576f6 | 2021-11-02 16:32:28 -0500 | [diff] [blame] | 79 | (fsps_hdr.fsp_multi_phase_si_init_entry_offset != 0); |
Subrata Banik | 298b359 | 2021-09-14 12:38:08 +0530 | [diff] [blame] | 80 | } |
| 81 | |
| 82 | static void fsp_fill_common_arch_params(FSPS_UPD *supd) |
| 83 | { |
| 84 | #if CONFIG(FSPS_HAS_ARCH_UPD) |
| 85 | FSPS_ARCH_UPD *s_arch_cfg = &supd->FspsArchUpd; |
| 86 | s_arch_cfg->EnableMultiPhaseSiliconInit = fsp_is_multi_phase_init_enabled(); |
| 87 | #endif |
| 88 | } |
| 89 | |
Lee Leahy | 9671faa | 2016-07-24 18:18:52 -0700 | [diff] [blame] | 90 | static void do_silicon_init(struct fsp_header *hdr) |
Andrey Petrov | 42c4e88 | 2016-02-25 14:17:45 -0800 | [diff] [blame] | 91 | { |
Subrata Banik | 44ffb5d | 2018-05-24 10:51:29 +0530 | [diff] [blame] | 92 | FSPS_UPD *upd, *supd; |
Andrey Petrov | 42c4e88 | 2016-02-25 14:17:45 -0800 | [diff] [blame] | 93 | fsp_silicon_init_fn silicon_init; |
Brandon Breitenstein | c31ba0e | 2016-07-27 17:34:45 -0700 | [diff] [blame] | 94 | uint32_t status; |
Subrata Banik | 33d9c4a | 2020-05-26 18:26:54 +0530 | [diff] [blame] | 95 | fsp_multi_phase_si_init_fn multi_phase_si_init; |
| 96 | struct fsp_multi_phase_params multi_phase_params; |
| 97 | struct fsp_multi_phase_get_number_of_phases_params multi_phase_get_number; |
Andrey Petrov | 42c4e88 | 2016-02-25 14:17:45 -0800 | [diff] [blame] | 98 | |
Patrick Rudolph | 31218a4 | 2020-11-30 15:50:06 +0100 | [diff] [blame] | 99 | supd = (FSPS_UPD *) (uintptr_t)(hdr->cfg_region_offset + hdr->image_base); |
Andrey Petrov | 42c4e88 | 2016-02-25 14:17:45 -0800 | [diff] [blame] | 100 | |
Felix Held | 8899598 | 2021-01-28 22:43:52 +0100 | [diff] [blame] | 101 | fsp_verify_upd_header_signature(supd->FspUpdHeader.Signature, FSPS_UPD_SIGNATURE); |
Andrey Petrov | 42c4e88 | 2016-02-25 14:17:45 -0800 | [diff] [blame] | 102 | |
Nikolai Vyssotski | 175e4c5 | 2021-02-11 18:25:43 -0600 | [diff] [blame] | 103 | /* FSPS UPD and coreboot structure sizes should match. However, enforcing the exact |
| 104 | * match mandates simultaneous updates to coreboot and FSP repos. Allow coreboot |
| 105 | * to proceed if its UPD structure is smaller than FSP one to enable staggered UPD |
| 106 | * update process on both sides. The mismatch indicates a temporary build problem, |
| 107 | * don't leave it like this as FSP default settings can be bad choices for coreboot. |
Marshall Dawson | 71dbcf1 | 2019-09-11 14:02:34 -0600 | [diff] [blame] | 108 | */ |
Nikolai Vyssotski | 175e4c5 | 2021-02-11 18:25:43 -0600 | [diff] [blame] | 109 | if (!hdr->cfg_region_size || hdr->cfg_region_size < sizeof(FSPS_UPD)) |
Marshall Dawson | 71dbcf1 | 2019-09-11 14:02:34 -0600 | [diff] [blame] | 110 | die_with_post_code(POST_INVALID_VENDOR_BINARY, |
| 111 | "Invalid FSPS UPD region\n"); |
Nikolai Vyssotski | 175e4c5 | 2021-02-11 18:25:43 -0600 | [diff] [blame] | 112 | else if (hdr->cfg_region_size > sizeof(FSPS_UPD)) |
| 113 | printk(BIOS_ERR, "FSP and coreboot are out of sync! FSPS UPD size > coreboot\n"); |
Subrata Banik | 44ffb5d | 2018-05-24 10:51:29 +0530 | [diff] [blame] | 114 | |
Marshall Dawson | 71dbcf1 | 2019-09-11 14:02:34 -0600 | [diff] [blame] | 115 | upd = xmalloc(hdr->cfg_region_size); |
| 116 | |
| 117 | memcpy(upd, supd, hdr->cfg_region_size); |
Andrey Petrov | 42c4e88 | 2016-02-25 14:17:45 -0800 | [diff] [blame] | 118 | |
Subrata Banik | 298b359 | 2021-09-14 12:38:08 +0530 | [diff] [blame] | 119 | /* Fill common settings on behalf of chipset. */ |
| 120 | if (CONFIG(FSPS_HAS_ARCH_UPD)) |
| 121 | fsp_fill_common_arch_params(upd); |
Andrey Petrov | 42c4e88 | 2016-02-25 14:17:45 -0800 | [diff] [blame] | 122 | /* Give SoC/mainboard a chance to populate entries */ |
Subrata Banik | 44ffb5d | 2018-05-24 10:51:29 +0530 | [diff] [blame] | 123 | platform_fsp_silicon_init_params_cb(upd); |
Andrey Petrov | 42c4e88 | 2016-02-25 14:17:45 -0800 | [diff] [blame] | 124 | |
Wim Vervoorn | d137150 | 2019-12-17 14:10:16 +0100 | [diff] [blame] | 125 | /* Populate logo related entries */ |
Kyösti Mälkki | 4949a3d | 2021-01-09 20:38:43 +0200 | [diff] [blame] | 126 | if (CONFIG(BMP_LOGO)) |
| 127 | soc_load_logo(upd); |
Wim Vervoorn | cbc878d2 | 2019-11-28 14:45:12 +0100 | [diff] [blame] | 128 | |
Lee Leahy | 672df16 | 2016-07-24 18:21:13 -0700 | [diff] [blame] | 129 | /* Call SiliconInit */ |
Patrick Rudolph | 31218a4 | 2020-11-30 15:50:06 +0100 | [diff] [blame] | 130 | silicon_init = (void *) (uintptr_t)(hdr->image_base + |
Julian Schroeder | 8a576f6 | 2021-11-02 16:32:28 -0500 | [diff] [blame] | 131 | hdr->fsp_silicon_init_entry_offset); |
Subrata Banik | 44ffb5d | 2018-05-24 10:51:29 +0530 | [diff] [blame] | 132 | fsp_debug_before_silicon_init(silicon_init, supd, upd); |
Lee Leahy | 672df16 | 2016-07-24 18:21:13 -0700 | [diff] [blame] | 133 | |
| 134 | timestamp_add_now(TS_FSP_SILICON_INIT_START); |
| 135 | post_code(POST_FSP_SILICON_INIT); |
Patrick Rudolph | 40beb36 | 2020-12-01 10:08:38 +0100 | [diff] [blame] | 136 | |
Arthur Heymans | fdf6d12 | 2022-05-17 13:07:30 +0200 | [diff] [blame] | 137 | /* FSP disables the interrupt handler so remove debug exceptions temporarily */ |
| 138 | null_breakpoint_disable(); |
Patrick Rudolph | 31218a4 | 2020-11-30 15:50:06 +0100 | [diff] [blame] | 139 | if (ENV_X86_64 && CONFIG(PLATFORM_USES_FSP2_X86_32)) |
Patrick Rudolph | 40beb36 | 2020-12-01 10:08:38 +0100 | [diff] [blame] | 140 | status = protected_mode_call_1arg(silicon_init, (uintptr_t)upd); |
| 141 | else |
| 142 | status = silicon_init(upd); |
Arthur Heymans | fdf6d12 | 2022-05-17 13:07:30 +0200 | [diff] [blame] | 143 | null_breakpoint_init(); |
Patrick Rudolph | 40beb36 | 2020-12-01 10:08:38 +0100 | [diff] [blame] | 144 | |
Raul E Rangel | 43e993b | 2021-06-29 13:09:55 -0600 | [diff] [blame] | 145 | printk(BIOS_INFO, "FSPS returned %x\n", status); |
Patrick Rudolph | 40beb36 | 2020-12-01 10:08:38 +0100 | [diff] [blame] | 146 | |
Alexandru Gagniuc | 010225c | 2016-05-06 08:22:45 -0700 | [diff] [blame] | 147 | timestamp_add_now(TS_FSP_SILICON_INIT_END); |
Subrata Banik | 0755ab9 | 2017-07-12 15:31:06 +0530 | [diff] [blame] | 148 | post_code(POST_FSP_SILICON_EXIT); |
Alexandru Gagniuc | 010225c | 2016-05-06 08:22:45 -0700 | [diff] [blame] | 149 | |
Kyösti Mälkki | 4949a3d | 2021-01-09 20:38:43 +0200 | [diff] [blame] | 150 | if (CONFIG(BMP_LOGO)) |
| 151 | bmp_release_logo(); |
Wim Vervoorn | cbc878d2 | 2019-11-28 14:45:12 +0100 | [diff] [blame] | 152 | |
Lee Leahy | 672df16 | 2016-07-24 18:21:13 -0700 | [diff] [blame] | 153 | fsp_debug_after_silicon_init(status); |
Subrata Banik | 33d9c4a | 2020-05-26 18:26:54 +0530 | [diff] [blame] | 154 | fsps_return_value_handler(FSP_SILICON_INIT_API, status); |
Aaron Durbin | 35d42c7 | 2016-07-18 12:41:09 -0500 | [diff] [blame] | 155 | |
Subrata Banik | 96b32f1 | 2020-07-31 12:09:11 +0530 | [diff] [blame] | 156 | /* Reinitialize CPUs if FSP-S has done MP Init */ |
| 157 | if (CONFIG(USE_INTEL_FSP_MP_INIT)) |
| 158 | do_mpinit_after_fsp(); |
| 159 | |
Subrata Banik | 33d9c4a | 2020-05-26 18:26:54 +0530 | [diff] [blame] | 160 | if (!CONFIG(PLATFORM_USES_FSP2_2)) |
| 161 | return; |
Marshall Dawson | 7a9e894 | 2019-10-17 07:58:27 -0600 | [diff] [blame] | 162 | |
Subrata Banik | 33d9c4a | 2020-05-26 18:26:54 +0530 | [diff] [blame] | 163 | /* Check if SoC user would like to call Multi Phase Init */ |
Subrata Banik | 298b359 | 2021-09-14 12:38:08 +0530 | [diff] [blame] | 164 | if (!fsp_is_multi_phase_init_enabled()) |
Subrata Banik | 33d9c4a | 2020-05-26 18:26:54 +0530 | [diff] [blame] | 165 | return; |
| 166 | |
| 167 | /* Call MultiPhaseSiInit */ |
Patrick Rudolph | 31218a4 | 2020-11-30 15:50:06 +0100 | [diff] [blame] | 168 | multi_phase_si_init = (void *) (uintptr_t)(hdr->image_base + |
Julian Schroeder | 8a576f6 | 2021-11-02 16:32:28 -0500 | [diff] [blame] | 169 | hdr->fsp_multi_phase_si_init_entry_offset); |
Subrata Banik | 33d9c4a | 2020-05-26 18:26:54 +0530 | [diff] [blame] | 170 | |
| 171 | /* Implementing multi_phase_si_init() is optional as per FSP 2.2 spec */ |
| 172 | if (multi_phase_si_init == NULL) |
| 173 | return; |
| 174 | |
| 175 | post_code(POST_FSP_MULTI_PHASE_SI_INIT_ENTRY); |
| 176 | timestamp_add_now(TS_FSP_MULTI_PHASE_SI_INIT_START); |
| 177 | /* Get NumberOfPhases Value */ |
| 178 | multi_phase_params.multi_phase_action = GET_NUMBER_OF_PHASES; |
| 179 | multi_phase_params.phase_index = 0; |
| 180 | multi_phase_params.multi_phase_param_ptr = &multi_phase_get_number; |
| 181 | status = multi_phase_si_init(&multi_phase_params); |
| 182 | fsps_return_value_handler(FSP_MULTI_PHASE_SI_INIT_GET_NUMBER_OF_PHASES_API, status); |
| 183 | |
| 184 | /* Execute Multi Phase Execution */ |
Angel Pons | fd63e11 | 2021-09-08 11:52:09 +0200 | [diff] [blame] | 185 | for (uint32_t i = 1; i <= multi_phase_get_number.number_of_phases; i++) { |
| 186 | printk(BIOS_SPEW, "Executing Phase %u of FspMultiPhaseSiInit\n", i); |
Subrata Banik | 33d9c4a | 2020-05-26 18:26:54 +0530 | [diff] [blame] | 187 | /* |
| 188 | * Give SoC/mainboard a chance to perform any operation before |
| 189 | * Multi Phase Execution |
| 190 | */ |
| 191 | platform_fsp_multi_phase_init_cb(i); |
| 192 | |
| 193 | multi_phase_params.multi_phase_action = EXECUTE_PHASE; |
| 194 | multi_phase_params.phase_index = i; |
| 195 | multi_phase_params.multi_phase_param_ptr = NULL; |
| 196 | status = multi_phase_si_init(&multi_phase_params); |
| 197 | fsps_return_value_handler(FSP_MULTI_PHASE_SI_INIT_EXECUTE_PHASE_API, status); |
Lee Leahy | 9671faa | 2016-07-24 18:18:52 -0700 | [diff] [blame] | 198 | } |
Subrata Banik | 33d9c4a | 2020-05-26 18:26:54 +0530 | [diff] [blame] | 199 | timestamp_add_now(TS_FSP_MULTI_PHASE_SI_INIT_END); |
| 200 | post_code(POST_FSP_MULTI_PHASE_SI_INIT_EXIT); |
Andrey Petrov | 42c4e88 | 2016-02-25 14:17:45 -0800 | [diff] [blame] | 201 | } |
| 202 | |
Julius Werner | 8205ce6 | 2021-03-10 17:25:01 -0800 | [diff] [blame] | 203 | static void *fsps_allocator(void *arg_unused, size_t size, const union cbfs_mdata *mdata_unused) |
Aaron Durbin | a85febc | 2020-05-15 15:09:10 -0600 | [diff] [blame] | 204 | { |
Julius Werner | 8205ce6 | 2021-03-10 17:25:01 -0800 | [diff] [blame] | 205 | return cbmem_add(CBMEM_ID_REFCODE, size); |
Aaron Durbin | a85febc | 2020-05-15 15:09:10 -0600 | [diff] [blame] | 206 | } |
| 207 | |
Kyösti Mälkki | cc93c6e | 2021-01-09 22:53:52 +0200 | [diff] [blame] | 208 | void fsps_load(void) |
Andrey Petrov | 42c4e88 | 2016-02-25 14:17:45 -0800 | [diff] [blame] | 209 | { |
Aaron Durbin | a85febc | 2020-05-15 15:09:10 -0600 | [diff] [blame] | 210 | struct fsp_load_descriptor fspld = { |
| 211 | .fsp_prog = PROG_INIT(PROG_REFCODE, CONFIG_FSP_S_CBFS), |
Julius Werner | 8205ce6 | 2021-03-10 17:25:01 -0800 | [diff] [blame] | 212 | .alloc = fsps_allocator, |
Aaron Durbin | a85febc | 2020-05-15 15:09:10 -0600 | [diff] [blame] | 213 | }; |
| 214 | struct prog *fsps = &fspld.fsp_prog; |
Furquan Shaikh | f4b20af | 2017-02-20 13:33:32 -0800 | [diff] [blame] | 215 | static int load_done; |
| 216 | |
| 217 | if (load_done) |
| 218 | return; |
Brandon Breitenstein | c6ec8dd | 2016-11-17 12:23:04 -0800 | [diff] [blame] | 219 | |
Kyösti Mälkki | e0165fb | 2021-01-09 13:30:57 +0200 | [diff] [blame] | 220 | if (resume_from_stage_cache()) { |
Brandon Breitenstein | c6ec8dd | 2016-11-17 12:23:04 -0800 | [diff] [blame] | 221 | printk(BIOS_DEBUG, "Loading FSPS from stage_cache\n"); |
Aaron Durbin | a85febc | 2020-05-15 15:09:10 -0600 | [diff] [blame] | 222 | stage_cache_load_stage(STAGE_REFCODE, fsps); |
Julius Werner | 43c9d70 | 2021-04-12 17:00:16 -0700 | [diff] [blame] | 223 | if (fsp_validate_component(&fsps_hdr, prog_start(fsps), prog_size(fsps))) |
Brandon Breitenstein | c6ec8dd | 2016-11-17 12:23:04 -0800 | [diff] [blame] | 224 | die("On resume fsps header is invalid\n"); |
Furquan Shaikh | f4b20af | 2017-02-20 13:33:32 -0800 | [diff] [blame] | 225 | load_done = 1; |
Brandon Breitenstein | c6ec8dd | 2016-11-17 12:23:04 -0800 | [diff] [blame] | 226 | return; |
| 227 | } |
| 228 | |
Aaron Durbin | a85febc | 2020-05-15 15:09:10 -0600 | [diff] [blame] | 229 | if (fsp_load_component(&fspld, &fsps_hdr) != CB_SUCCESS) |
| 230 | die("FSP-S failed to load\n"); |
Aaron Durbin | 32ac018 | 2016-07-18 00:35:42 -0500 | [diff] [blame] | 231 | |
Aaron Durbin | a85febc | 2020-05-15 15:09:10 -0600 | [diff] [blame] | 232 | stage_cache_add(STAGE_REFCODE, fsps); |
Aaron Durbin | 32ac018 | 2016-07-18 00:35:42 -0500 | [diff] [blame] | 233 | |
Furquan Shaikh | f4b20af | 2017-02-20 13:33:32 -0800 | [diff] [blame] | 234 | load_done = 1; |
| 235 | } |
Aaron Durbin | 32ac018 | 2016-07-18 00:35:42 -0500 | [diff] [blame] | 236 | |
Raul E Rangel | 1592846 | 2021-11-05 10:29:24 -0600 | [diff] [blame] | 237 | void preload_fsps(void) |
| 238 | { |
| 239 | if (!CONFIG(CBFS_PRELOAD)) |
| 240 | return; |
| 241 | |
| 242 | printk(BIOS_DEBUG, "Preloading %s\n", CONFIG_FSP_S_CBFS); |
| 243 | cbfs_preload(CONFIG_FSP_S_CBFS); |
| 244 | } |
| 245 | |
Kyösti Mälkki | cc93c6e | 2021-01-09 22:53:52 +0200 | [diff] [blame] | 246 | void fsp_silicon_init(void) |
Furquan Shaikh | f4b20af | 2017-02-20 13:33:32 -0800 | [diff] [blame] | 247 | { |
Martin Roth | 146508d | 2021-04-30 16:45:08 -0600 | [diff] [blame] | 248 | timestamp_add_now(TS_FSP_SILICON_INIT_LOAD); |
Kyösti Mälkki | cc93c6e | 2021-01-09 22:53:52 +0200 | [diff] [blame] | 249 | fsps_load(); |
Furquan Shaikh | f4b20af | 2017-02-20 13:33:32 -0800 | [diff] [blame] | 250 | do_silicon_init(&fsps_hdr); |
Subrata Banik | 6de1d9f | 2022-03-20 19:50:38 +0530 | [diff] [blame] | 251 | |
| 252 | if (CONFIG(DISPLAY_FSP_TIMESTAMPS)) |
| 253 | fsp_display_timestamp(); |
Andrey Petrov | 42c4e88 | 2016-02-25 14:17:45 -0800 | [diff] [blame] | 254 | } |
Wim Vervoorn | d137150 | 2019-12-17 14:10:16 +0100 | [diff] [blame] | 255 | |
Kyösti Mälkki | 4949a3d | 2021-01-09 20:38:43 +0200 | [diff] [blame] | 256 | __weak void soc_load_logo(FSPS_UPD *supd) { } |