post_code: add post code for video initialization failure
Add a new post code POST_VIDEO_FAILURE used when the Intel FSP silicon
initialization returns an error when graphics was also initialized.
BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms
Change-Id: Ibc7f7defbed34038f445949010a37c8e368aae20
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index b0a697d..e9c29db 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -18,6 +18,7 @@
#include <fsp/api.h>
#include <fsp/util.h>
#include <program_loading.h>
+#include <soc/intel/common/vbt.h>
#include <stage_cache.h>
#include <string.h>
#include <timestamp.h>
@@ -29,6 +30,7 @@
FSPS_UPD *upd, *supd;
fsp_silicon_init_fn silicon_init;
uint32_t status;
+ uint8_t postcode;
supd = (FSPS_UPD *) (hdr->cfg_region_offset + hdr->image_base);
@@ -59,8 +61,18 @@
/* Handle any errors returned by FspSiliconInit */
fsp_handle_reset(status);
if (status != FSP_SUCCESS) {
+ if (vbt_get()) {
+ /* Attempted to initialize graphics. Assume failure
+ * is related to a video failure.
+ */
+ postcode = POST_VIDEO_FAILURE;
+ } else {
+ /* Other silicon initialization failed */
+ postcode = POST_HW_INIT_FAILURE;
+ }
printk(BIOS_SPEW, "FspSiliconInit returned 0x%08x\n", status);
- die("FspSiliconINit returned an error!\n");
+ die_with_post_code(postcode,
+ "FspSiliconINit returned an error!\n");
}
}