Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Andrey Petrov | 42c4e88 | 2016-02-25 14:17:45 -0800 | [diff] [blame] | 2 | |
Andrey Petrov | 42c4e88 | 2016-02-25 14:17:45 -0800 | [diff] [blame] | 3 | #include <cbfs.h> |
Aaron Durbin | 32ac018 | 2016-07-18 00:35:42 -0500 | [diff] [blame] | 4 | #include <cbmem.h> |
| 5 | #include <commonlib/fsp.h> |
Subrata Banik | 44ffb5d | 2018-05-24 10:51:29 +0530 | [diff] [blame] | 6 | #include <commonlib/stdlib.h> |
Andrey Petrov | 42c4e88 | 2016-02-25 14:17:45 -0800 | [diff] [blame] | 7 | #include <console/console.h> |
| 8 | #include <fsp/api.h> |
| 9 | #include <fsp/util.h> |
Aaron Durbin | 32ac018 | 2016-07-18 00:35:42 -0500 | [diff] [blame] | 10 | #include <program_loading.h> |
Keith Short | c58e3bd | 2019-05-10 11:14:31 -0600 | [diff] [blame] | 11 | #include <soc/intel/common/vbt.h> |
Brandon Breitenstein | c6ec8dd | 2016-11-17 12:23:04 -0800 | [diff] [blame] | 12 | #include <stage_cache.h> |
Andrey Petrov | 42c4e88 | 2016-02-25 14:17:45 -0800 | [diff] [blame] | 13 | #include <string.h> |
Alexandru Gagniuc | 010225c | 2016-05-06 08:22:45 -0700 | [diff] [blame] | 14 | #include <timestamp.h> |
Elyes HAOUAS | bd1683d | 2019-05-15 21:05:37 +0200 | [diff] [blame] | 15 | #include <types.h> |
Andrey Petrov | 42c4e88 | 2016-02-25 14:17:45 -0800 | [diff] [blame] | 16 | |
| 17 | struct fsp_header fsps_hdr; |
| 18 | |
Subrata Banik | 33d9c4a | 2020-05-26 18:26:54 +0530 | [diff] [blame] | 19 | struct fsp_multi_phase_get_number_of_phases_params { |
| 20 | uint32_t number_of_phases; |
| 21 | uint32_t phases_executed; |
| 22 | }; |
| 23 | |
| 24 | /* Callbacks for SoC/Mainboard specific overrides */ |
| 25 | void __weak platform_fsp_multi_phase_init_cb(uint32_t phase_index) |
| 26 | { |
| 27 | /* Leave for the SoC/Mainboard to implement if necessary. */ |
| 28 | } |
| 29 | |
| 30 | int __weak soc_fsp_multi_phase_init_is_enable(void) |
| 31 | { |
| 32 | return 1; |
| 33 | } |
| 34 | |
| 35 | /* FSP Specification < 2.2 has only 1 stage like FspSiliconInit. FSP specification >= 2.2 |
| 36 | * has multiple stages as below. |
| 37 | */ |
| 38 | enum fsp_silicon_init_phases { |
| 39 | FSP_SILICON_INIT_API, |
| 40 | FSP_MULTI_PHASE_SI_INIT_GET_NUMBER_OF_PHASES_API, |
| 41 | FSP_MULTI_PHASE_SI_INIT_EXECUTE_PHASE_API |
| 42 | }; |
| 43 | |
| 44 | static void fsps_return_value_handler(enum fsp_silicon_init_phases phases, uint32_t status) |
| 45 | { |
| 46 | uint8_t postcode; |
| 47 | |
| 48 | /* Handle any reset request returned by FSP-S APIs */ |
| 49 | fsp_handle_reset(status); |
| 50 | |
| 51 | if (status == FSP_SUCCESS) |
| 52 | return; |
| 53 | /* Handle all other errors returned by FSP-S APIs */ |
| 54 | /* Assume video failure if attempted to initialize graphics */ |
| 55 | if (CONFIG(RUN_FSP_GOP) && vbt_get()) |
| 56 | postcode = POST_VIDEO_FAILURE; |
| 57 | else |
| 58 | postcode = POST_HW_INIT_FAILURE; /* else generic */ |
| 59 | |
| 60 | switch (phases) { |
| 61 | case FSP_SILICON_INIT_API: |
| 62 | die_with_post_code(postcode, "FspSiliconInit returned with error 0x%08x\n", |
| 63 | status); |
| 64 | break; |
| 65 | case FSP_MULTI_PHASE_SI_INIT_GET_NUMBER_OF_PHASES_API: |
| 66 | printk(BIOS_SPEW, "FspMultiPhaseSiInit NumberOfPhases returned 0x%08x\n", |
| 67 | status); |
| 68 | break; |
| 69 | case FSP_MULTI_PHASE_SI_INIT_EXECUTE_PHASE_API: |
| 70 | printk(BIOS_SPEW, "FspMultiPhaseSiInit ExecutePhase returned 0x%08x\n", |
| 71 | status); |
| 72 | break; |
| 73 | default: |
| 74 | break; |
| 75 | } |
| 76 | } |
| 77 | |
Lee Leahy | 9671faa | 2016-07-24 18:18:52 -0700 | [diff] [blame] | 78 | static void do_silicon_init(struct fsp_header *hdr) |
Andrey Petrov | 42c4e88 | 2016-02-25 14:17:45 -0800 | [diff] [blame] | 79 | { |
Subrata Banik | 44ffb5d | 2018-05-24 10:51:29 +0530 | [diff] [blame] | 80 | FSPS_UPD *upd, *supd; |
Andrey Petrov | 42c4e88 | 2016-02-25 14:17:45 -0800 | [diff] [blame] | 81 | fsp_silicon_init_fn silicon_init; |
Brandon Breitenstein | c31ba0e | 2016-07-27 17:34:45 -0700 | [diff] [blame] | 82 | uint32_t status; |
Wim Vervoorn | d137150 | 2019-12-17 14:10:16 +0100 | [diff] [blame] | 83 | const struct cbmem_entry *logo_entry = NULL; |
Subrata Banik | 33d9c4a | 2020-05-26 18:26:54 +0530 | [diff] [blame] | 84 | fsp_multi_phase_si_init_fn multi_phase_si_init; |
| 85 | struct fsp_multi_phase_params multi_phase_params; |
| 86 | struct fsp_multi_phase_get_number_of_phases_params multi_phase_get_number; |
Andrey Petrov | 42c4e88 | 2016-02-25 14:17:45 -0800 | [diff] [blame] | 87 | |
Brandon Breitenstein | c31ba0e | 2016-07-27 17:34:45 -0700 | [diff] [blame] | 88 | supd = (FSPS_UPD *) (hdr->cfg_region_offset + hdr->image_base); |
Andrey Petrov | 42c4e88 | 2016-02-25 14:17:45 -0800 | [diff] [blame] | 89 | |
Lee Leahy | e686ee8 | 2017-03-10 08:45:30 -0800 | [diff] [blame] | 90 | if (supd->FspUpdHeader.Signature != FSPS_UPD_SIGNATURE) |
Keith Short | bb41aba | 2019-05-16 14:07:43 -0600 | [diff] [blame] | 91 | die_with_post_code(POST_INVALID_VENDOR_BINARY, |
| 92 | "Invalid FSPS signature\n"); |
Andrey Petrov | 42c4e88 | 2016-02-25 14:17:45 -0800 | [diff] [blame] | 93 | |
Marshall Dawson | 71dbcf1 | 2019-09-11 14:02:34 -0600 | [diff] [blame] | 94 | /* Disallow invalid config regions. Default settings are likely bad |
| 95 | * choices for coreboot, and different sized UPD from what the region |
| 96 | * allows is potentially a build problem. |
| 97 | */ |
| 98 | if (!hdr->cfg_region_size || hdr->cfg_region_size != sizeof(FSPS_UPD)) |
| 99 | die_with_post_code(POST_INVALID_VENDOR_BINARY, |
| 100 | "Invalid FSPS UPD region\n"); |
Subrata Banik | 44ffb5d | 2018-05-24 10:51:29 +0530 | [diff] [blame] | 101 | |
Marshall Dawson | 71dbcf1 | 2019-09-11 14:02:34 -0600 | [diff] [blame] | 102 | upd = xmalloc(hdr->cfg_region_size); |
| 103 | |
| 104 | memcpy(upd, supd, hdr->cfg_region_size); |
Andrey Petrov | 42c4e88 | 2016-02-25 14:17:45 -0800 | [diff] [blame] | 105 | |
| 106 | /* Give SoC/mainboard a chance to populate entries */ |
Subrata Banik | 44ffb5d | 2018-05-24 10:51:29 +0530 | [diff] [blame] | 107 | platform_fsp_silicon_init_params_cb(upd); |
Andrey Petrov | 42c4e88 | 2016-02-25 14:17:45 -0800 | [diff] [blame] | 108 | |
Wim Vervoorn | d137150 | 2019-12-17 14:10:16 +0100 | [diff] [blame] | 109 | /* Populate logo related entries */ |
| 110 | if (CONFIG(FSP2_0_DISPLAY_LOGO)) |
| 111 | logo_entry = soc_load_logo(upd); |
Wim Vervoorn | cbc878d2 | 2019-11-28 14:45:12 +0100 | [diff] [blame] | 112 | |
Lee Leahy | 672df16 | 2016-07-24 18:21:13 -0700 | [diff] [blame] | 113 | /* Call SiliconInit */ |
Andrey Petrov | 42c4e88 | 2016-02-25 14:17:45 -0800 | [diff] [blame] | 114 | silicon_init = (void *) (hdr->image_base + |
Alexandru Gagniuc | 010225c | 2016-05-06 08:22:45 -0700 | [diff] [blame] | 115 | hdr->silicon_init_entry_offset); |
Subrata Banik | 44ffb5d | 2018-05-24 10:51:29 +0530 | [diff] [blame] | 116 | fsp_debug_before_silicon_init(silicon_init, supd, upd); |
Lee Leahy | 672df16 | 2016-07-24 18:21:13 -0700 | [diff] [blame] | 117 | |
| 118 | timestamp_add_now(TS_FSP_SILICON_INIT_START); |
| 119 | post_code(POST_FSP_SILICON_INIT); |
Subrata Banik | 44ffb5d | 2018-05-24 10:51:29 +0530 | [diff] [blame] | 120 | status = silicon_init(upd); |
Alexandru Gagniuc | 010225c | 2016-05-06 08:22:45 -0700 | [diff] [blame] | 121 | timestamp_add_now(TS_FSP_SILICON_INIT_END); |
Subrata Banik | 0755ab9 | 2017-07-12 15:31:06 +0530 | [diff] [blame] | 122 | post_code(POST_FSP_SILICON_EXIT); |
Alexandru Gagniuc | 010225c | 2016-05-06 08:22:45 -0700 | [diff] [blame] | 123 | |
Wim Vervoorn | d137150 | 2019-12-17 14:10:16 +0100 | [diff] [blame] | 124 | if (logo_entry) |
Wim Vervoorn | cbc878d2 | 2019-11-28 14:45:12 +0100 | [diff] [blame] | 125 | cbmem_entry_remove(logo_entry); |
| 126 | |
Lee Leahy | 672df16 | 2016-07-24 18:21:13 -0700 | [diff] [blame] | 127 | fsp_debug_after_silicon_init(status); |
Subrata Banik | 33d9c4a | 2020-05-26 18:26:54 +0530 | [diff] [blame] | 128 | fsps_return_value_handler(FSP_SILICON_INIT_API, status); |
Aaron Durbin | 35d42c7 | 2016-07-18 12:41:09 -0500 | [diff] [blame] | 129 | |
Subrata Banik | 96b32f1 | 2020-07-31 12:09:11 +0530 | [diff] [blame^] | 130 | /* Reinitialize CPUs if FSP-S has done MP Init */ |
| 131 | if (CONFIG(USE_INTEL_FSP_MP_INIT)) |
| 132 | do_mpinit_after_fsp(); |
| 133 | |
Subrata Banik | 33d9c4a | 2020-05-26 18:26:54 +0530 | [diff] [blame] | 134 | if (!CONFIG(PLATFORM_USES_FSP2_2)) |
| 135 | return; |
Marshall Dawson | 7a9e894 | 2019-10-17 07:58:27 -0600 | [diff] [blame] | 136 | |
Subrata Banik | 33d9c4a | 2020-05-26 18:26:54 +0530 | [diff] [blame] | 137 | /* Check if SoC user would like to call Multi Phase Init */ |
| 138 | if (!soc_fsp_multi_phase_init_is_enable()) |
| 139 | return; |
| 140 | |
| 141 | /* Call MultiPhaseSiInit */ |
| 142 | multi_phase_si_init = (void *) (hdr->image_base + |
| 143 | hdr->multi_phase_si_init_entry_offset); |
| 144 | |
| 145 | /* Implementing multi_phase_si_init() is optional as per FSP 2.2 spec */ |
| 146 | if (multi_phase_si_init == NULL) |
| 147 | return; |
| 148 | |
| 149 | post_code(POST_FSP_MULTI_PHASE_SI_INIT_ENTRY); |
| 150 | timestamp_add_now(TS_FSP_MULTI_PHASE_SI_INIT_START); |
| 151 | /* Get NumberOfPhases Value */ |
| 152 | multi_phase_params.multi_phase_action = GET_NUMBER_OF_PHASES; |
| 153 | multi_phase_params.phase_index = 0; |
| 154 | multi_phase_params.multi_phase_param_ptr = &multi_phase_get_number; |
| 155 | status = multi_phase_si_init(&multi_phase_params); |
| 156 | fsps_return_value_handler(FSP_MULTI_PHASE_SI_INIT_GET_NUMBER_OF_PHASES_API, status); |
| 157 | |
| 158 | /* Execute Multi Phase Execution */ |
| 159 | for (int i = 1; i <= multi_phase_get_number.number_of_phases; i++) { |
| 160 | printk(BIOS_SPEW, "Executing Phase %d of FspMultiPhaseSiInit\n", i); |
| 161 | /* |
| 162 | * Give SoC/mainboard a chance to perform any operation before |
| 163 | * Multi Phase Execution |
| 164 | */ |
| 165 | platform_fsp_multi_phase_init_cb(i); |
| 166 | |
| 167 | multi_phase_params.multi_phase_action = EXECUTE_PHASE; |
| 168 | multi_phase_params.phase_index = i; |
| 169 | multi_phase_params.multi_phase_param_ptr = NULL; |
| 170 | status = multi_phase_si_init(&multi_phase_params); |
| 171 | fsps_return_value_handler(FSP_MULTI_PHASE_SI_INIT_EXECUTE_PHASE_API, status); |
Lee Leahy | 9671faa | 2016-07-24 18:18:52 -0700 | [diff] [blame] | 172 | } |
Subrata Banik | 33d9c4a | 2020-05-26 18:26:54 +0530 | [diff] [blame] | 173 | timestamp_add_now(TS_FSP_MULTI_PHASE_SI_INIT_END); |
| 174 | post_code(POST_FSP_MULTI_PHASE_SI_INIT_EXIT); |
Andrey Petrov | 42c4e88 | 2016-02-25 14:17:45 -0800 | [diff] [blame] | 175 | } |
| 176 | |
Aaron Durbin | a85febc | 2020-05-15 15:09:10 -0600 | [diff] [blame] | 177 | static int fsps_get_dest(const struct fsp_load_descriptor *fspld, void **dest, |
| 178 | size_t size, const struct region_device *source) |
| 179 | { |
| 180 | *dest = cbmem_add(CBMEM_ID_REFCODE, size); |
| 181 | |
| 182 | if (*dest == NULL) |
| 183 | return -1; |
| 184 | |
| 185 | return 0; |
| 186 | } |
| 187 | |
Furquan Shaikh | f4b20af | 2017-02-20 13:33:32 -0800 | [diff] [blame] | 188 | void fsps_load(bool s3wake) |
Andrey Petrov | 42c4e88 | 2016-02-25 14:17:45 -0800 | [diff] [blame] | 189 | { |
Aaron Durbin | a85febc | 2020-05-15 15:09:10 -0600 | [diff] [blame] | 190 | struct fsp_load_descriptor fspld = { |
| 191 | .fsp_prog = PROG_INIT(PROG_REFCODE, CONFIG_FSP_S_CBFS), |
| 192 | .get_destination = fsps_get_dest, |
| 193 | }; |
| 194 | struct prog *fsps = &fspld.fsp_prog; |
Furquan Shaikh | f4b20af | 2017-02-20 13:33:32 -0800 | [diff] [blame] | 195 | static int load_done; |
| 196 | |
| 197 | if (load_done) |
| 198 | return; |
Brandon Breitenstein | c6ec8dd | 2016-11-17 12:23:04 -0800 | [diff] [blame] | 199 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 200 | if (s3wake && !CONFIG(NO_STAGE_CACHE)) { |
Brandon Breitenstein | c6ec8dd | 2016-11-17 12:23:04 -0800 | [diff] [blame] | 201 | printk(BIOS_DEBUG, "Loading FSPS from stage_cache\n"); |
Aaron Durbin | a85febc | 2020-05-15 15:09:10 -0600 | [diff] [blame] | 202 | stage_cache_load_stage(STAGE_REFCODE, fsps); |
| 203 | if (fsp_validate_component(&fsps_hdr, prog_rdev(fsps)) != CB_SUCCESS) |
Brandon Breitenstein | c6ec8dd | 2016-11-17 12:23:04 -0800 | [diff] [blame] | 204 | die("On resume fsps header is invalid\n"); |
Furquan Shaikh | f4b20af | 2017-02-20 13:33:32 -0800 | [diff] [blame] | 205 | load_done = 1; |
Brandon Breitenstein | c6ec8dd | 2016-11-17 12:23:04 -0800 | [diff] [blame] | 206 | return; |
| 207 | } |
| 208 | |
Aaron Durbin | a85febc | 2020-05-15 15:09:10 -0600 | [diff] [blame] | 209 | if (fsp_load_component(&fspld, &fsps_hdr) != CB_SUCCESS) |
| 210 | die("FSP-S failed to load\n"); |
Aaron Durbin | 32ac018 | 2016-07-18 00:35:42 -0500 | [diff] [blame] | 211 | |
Aaron Durbin | a85febc | 2020-05-15 15:09:10 -0600 | [diff] [blame] | 212 | stage_cache_add(STAGE_REFCODE, fsps); |
Aaron Durbin | 32ac018 | 2016-07-18 00:35:42 -0500 | [diff] [blame] | 213 | |
Furquan Shaikh | f4b20af | 2017-02-20 13:33:32 -0800 | [diff] [blame] | 214 | load_done = 1; |
| 215 | } |
Aaron Durbin | 32ac018 | 2016-07-18 00:35:42 -0500 | [diff] [blame] | 216 | |
Furquan Shaikh | f4b20af | 2017-02-20 13:33:32 -0800 | [diff] [blame] | 217 | void fsp_silicon_init(bool s3wake) |
| 218 | { |
| 219 | fsps_load(s3wake); |
| 220 | do_silicon_init(&fsps_hdr); |
Andrey Petrov | 42c4e88 | 2016-02-25 14:17:45 -0800 | [diff] [blame] | 221 | } |
Wim Vervoorn | d137150 | 2019-12-17 14:10:16 +0100 | [diff] [blame] | 222 | |
| 223 | /* Load bmp and set FSP parameters, fsp_load_logo can be used */ |
| 224 | __weak const struct cbmem_entry *soc_load_logo(FSPS_UPD *supd) |
| 225 | { |
| 226 | return NULL; |
| 227 | } |