drivers/intel/fsp2_0/include/fsp: fix fsp_header
This patch aligns fsp_header with the Intel specification 2.0 and 2.3.
The main impetus for this change is to make the fsp_info_header fully
accessible in soc/vendor code. Here items such as image_revision can be
checked.
TEST=verify image revision output in the coreboot serial log.
compare to FSP version shown in serial debug output.
verify Google Guybrush machine boots into OS.
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Change-Id: Ibf50f16b5e9793d946a95970fcdabc4c07289646
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index 83d44b1..05cea11 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -75,7 +75,7 @@
bool fsp_is_multi_phase_init_enabled(void)
{
return CONFIG(FSPS_USE_MULTI_PHASE_INIT) &&
- (fsps_hdr.multi_phase_si_init_entry_offset != 0);
+ (fsps_hdr.fsp_multi_phase_si_init_entry_offset != 0);
}
static void fsp_fill_common_arch_params(FSPS_UPD *supd)
@@ -127,7 +127,7 @@
/* Call SiliconInit */
silicon_init = (void *) (uintptr_t)(hdr->image_base +
- hdr->silicon_init_entry_offset);
+ hdr->fsp_silicon_init_entry_offset);
fsp_debug_before_silicon_init(silicon_init, supd, upd);
timestamp_add_now(TS_FSP_SILICON_INIT_START);
@@ -162,7 +162,7 @@
/* Call MultiPhaseSiInit */
multi_phase_si_init = (void *) (uintptr_t)(hdr->image_base +
- hdr->multi_phase_si_init_entry_offset);
+ hdr->fsp_multi_phase_si_init_entry_offset);
/* Implementing multi_phase_si_init() is optional as per FSP 2.2 spec */
if (multi_phase_si_init == NULL)