intel/fsp: Add and use new post codes for FSP phase indication
New post codes are
POST_FSP_MEMORY_EXIT
POST_FSP_SILICON_EXIT
This patch will make it more consistent to debug FSP hang
and reset issues.
Bug=none
Branch=none
TEST=Build and Boot on eve
Change-Id: I93004a09c2a3a97ac9458a0f686ab42415af19fb
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index 9f0bf7c..bda88d1 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -49,7 +49,7 @@
post_code(POST_FSP_SILICON_INIT);
status = silicon_init(&upd);
timestamp_add_now(TS_FSP_SILICON_INIT_END);
- post_code(POST_FSP_SILICON_INIT);
+ post_code(POST_FSP_SILICON_EXIT);
fsp_debug_after_silicon_init(status);