commit 0755ab98a5f0d6632a4fc856d8812f5e70983a13
author Subrata Banik <subrata.banik@intel.com> Wed Jul 12 15:31:06 2017 +0530
committer Martin Roth <martinroth@google.com> Mon Jul 17 15:16:37 2017 +0000
tree c379cf972fcd13bdf7f04a26063ce97b2bb85de3
parent 0beac81f64162fe8374c9f008b9ea811f5064b34

intel/fsp: Add and use new post codes for FSP phase indication

New post codes are 
POST_FSP_MEMORY_EXIT
POST_FSP_SILICON_EXIT

This patch will make it more consistent to debug FSP hang
and reset issues.

Bug=none
Branch=none
TEST=Build and Boot on eve

Change-Id: I93004a09c2a3a97ac9458a0f686ab42415af19fb
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/drivers/intel/fsp2_0/silicon_init.c

diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index 9f0bf7c..bda88d1 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -49,7 +49,7 @@
 	post_code(POST_FSP_SILICON_INIT);
 	status = silicon_init(&upd);
 	timestamp_add_now(TS_FSP_SILICON_INIT_END);
-	post_code(POST_FSP_SILICON_INIT);
+	post_code(POST_FSP_SILICON_EXIT);
 
 	fsp_debug_after_silicon_init(status);