Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 1 | config SOC_INTEL_ALDERLAKE |
| 2 | bool |
| 3 | help |
| 4 | Intel Alderlake support |
| 5 | |
Varshit Pandya | b5df56f | 2021-01-18 09:44:35 +0530 | [diff] [blame] | 6 | config SOC_INTEL_ALDERLAKE_PCH_M |
| 7 | bool |
| 8 | help |
| 9 | Choose this option if you have PCH-M chipset. |
| 10 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 11 | if SOC_INTEL_ALDERLAKE |
| 12 | |
| 13 | config CPU_SPECIFIC_OPTIONS |
| 14 | def_bool y |
Angel Pons | a25eaff | 2020-09-23 15:37:15 +0200 | [diff] [blame] | 15 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Angel Pons | 8e035e3 | 2021-06-22 12:58:20 +0200 | [diff] [blame] | 16 | select ARCH_X86 |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 17 | select BOOT_DEVICE_SUPPORTS_WRITES |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 18 | select CACHE_MRC_SETTINGS |
| 19 | select CPU_INTEL_COMMON |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 20 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
Michael Niewöhner | fe6070f | 2020-10-04 15:16:04 +0200 | [diff] [blame] | 21 | select CPU_SUPPORTS_PM_TIMER_EMULATION |
Eric Lai | 4ea47c3 | 2020-12-21 16:57:49 +0800 | [diff] [blame] | 22 | select DRIVERS_USB_ACPI |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 23 | select FSP_COMPRESS_FSP_S_LZ4 |
Subrata Banik | 683c95e | 2020-12-19 19:36:45 +0530 | [diff] [blame] | 24 | select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 25 | select FSP_M_XIP |
Subrata Banik | 4ed9f9a | 2020-10-31 22:01:55 +0530 | [diff] [blame] | 26 | select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 27 | select GENERIC_GPIO_LIB |
| 28 | select HAVE_FSP_GOP |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 29 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 30 | select HAVE_SMI_HANDLER |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 31 | select IDT_IN_EVERY_STAGE |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 32 | select INTEL_GMA_ACPI |
| 33 | select INTEL_GMA_ADD_VBT if RUN_FSP_GOP |
Meera Ravindranath | 81d367f | 2021-07-08 09:39:11 +0530 | [diff] [blame] | 34 | select INTEL_GMA_OPREGION_2_1 |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 35 | select IOAPIC |
Subrata Banik | 0aed4e5 | 2020-10-12 17:27:31 +0530 | [diff] [blame] | 36 | select INTEL_TME |
Aamir Bohra | 30cca6c | 2021-02-04 20:57:51 +0530 | [diff] [blame] | 37 | select MP_SERVICES_PPI_V2 |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 38 | select MRC_SETTINGS_PROTECT |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 39 | select PARALLEL_MP_AP_WORK |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 40 | select MICROCODE_BLOB_UNDISCLOSED |
Subrata Banik | ee73594 | 2020-09-07 17:52:23 +0530 | [diff] [blame] | 41 | select PLATFORM_USES_FSP2_2 |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 42 | select REG_SCRIPT |
| 43 | select PMC_GLOBAL_RESET_ENABLE_LOCK |
| 44 | select PMC_LOW_POWER_MODE_PROGRAM |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 45 | select SOC_INTEL_COMMON |
Subrata Banik | 0808992 | 2020-10-03 13:02:06 +0530 | [diff] [blame] | 46 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 47 | select SOC_INTEL_COMMON_BLOCK |
Subrata Banik | 0808992 | 2020-10-03 13:02:06 +0530 | [diff] [blame] | 48 | select SOC_INTEL_COMMON_BLOCK_ACPI |
ravindr1 | 7459657 | 2021-03-29 19:41:25 +0530 | [diff] [blame] | 49 | select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC |
Angel Pons | 98f672a | 2021-02-19 19:42:10 +0100 | [diff] [blame] | 50 | select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO |
Subrata Banik | 21974ab | 2020-10-31 21:40:43 +0530 | [diff] [blame] | 51 | select SOC_INTEL_COMMON_BLOCK_CAR |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 52 | select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 53 | select SOC_INTEL_COMMON_BLOCK_CPU |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 54 | select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT |
Angel Pons | a4cd911 | 2021-02-19 19:23:38 +0100 | [diff] [blame] | 55 | select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 56 | select SOC_INTEL_COMMON_BLOCK_DTT |
| 57 | select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 58 | select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 59 | select SOC_INTEL_COMMON_BLOCK_HDA |
Tim Wawrzynczak | 0c057c2 | 2021-03-04 10:56:28 -0700 | [diff] [blame] | 60 | select SOC_INTEL_COMMON_BLOCK_IPU |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 61 | select SOC_INTEL_COMMON_BLOCK_IRQ |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 62 | select SOC_INTEL_COMMON_BLOCK_MEMINIT |
Rizwan Qureshi | 307be99 | 2021-04-08 20:35:29 +0530 | [diff] [blame] | 63 | select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 |
Lean Sheng Tan | 7502000 | 2021-06-30 01:47:48 -0700 | [diff] [blame] | 64 | select SOC_INTEL_COMMON_BLOCK_PMC_EPOC |
Sumeet R Pawnikar | 77298c6 | 2021-03-10 21:09:37 +0530 | [diff] [blame] | 65 | select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 66 | select SOC_INTEL_COMMON_BLOCK_SA |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 67 | select SOC_INTEL_COMMON_BLOCK_SMM |
| 68 | select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP |
Eric Lai | 4ea47c3 | 2020-12-21 16:57:49 +0800 | [diff] [blame] | 69 | select SOC_INTEL_COMMON_BLOCK_USB4 |
| 70 | select SOC_INTEL_COMMON_BLOCK_USB4_PCIE |
| 71 | select SOC_INTEL_COMMON_BLOCK_USB4_XHCI |
Tim Wawrzynczak | 242da79 | 2020-11-10 10:13:54 -0700 | [diff] [blame] | 72 | select SOC_INTEL_COMMON_BLOCK_XHCI |
| 73 | select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG |
Subrata Banik | 4ed9f9a | 2020-10-31 22:01:55 +0530 | [diff] [blame] | 74 | select SOC_INTEL_COMMON_FSP_RESET |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 75 | select SOC_INTEL_COMMON_PCH_BASE |
| 76 | select SOC_INTEL_COMMON_RESET |
Tim Wawrzynczak | c0e82e7 | 2021-06-17 12:42:35 -0600 | [diff] [blame] | 77 | select SOC_INTEL_CSE_SET_EOP |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 78 | select SSE2 |
| 79 | select SUPPORT_CPU_UCODE_IN_CBFS |
| 80 | select TSC_MONOTONIC_TIMER |
| 81 | select UDELAY_TSC |
Subrata Banik | ee73594 | 2020-09-07 17:52:23 +0530 | [diff] [blame] | 82 | select UDK_202005_BINDING |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 83 | select DISPLAY_FSP_VERSION_INFO |
| 84 | select HECI_DISABLE_USING_SMM |
| 85 | |
Subrata Banik | 095e2a7 | 2021-07-05 20:56:15 +0530 | [diff] [blame] | 86 | config ALDERLAKE_CAR_ENHANCED_NEM |
| 87 | bool |
| 88 | default y if !INTEL_CAR_NEM |
| 89 | select INTEL_CAR_NEM_ENHANCED |
| 90 | select CAR_HAS_SF_MASKS |
| 91 | select COS_MAPPED_TO_MSB |
| 92 | select CAR_HAS_L3_PROTECTED_WAYS |
| 93 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 94 | config MAX_CPUS |
| 95 | int |
| 96 | default 24 |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 97 | |
| 98 | config DCACHE_RAM_BASE |
| 99 | default 0xfef00000 |
| 100 | |
| 101 | config DCACHE_RAM_SIZE |
Subrata Banik | 191bd82 | 2020-11-21 19:30:57 +0530 | [diff] [blame] | 102 | default 0xc0000 |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 103 | help |
| 104 | The size of the cache-as-ram region required during bootblock |
| 105 | and/or romstage. |
| 106 | |
| 107 | config DCACHE_BSP_STACK_SIZE |
| 108 | hex |
Subrata Banik | 191bd82 | 2020-11-21 19:30:57 +0530 | [diff] [blame] | 109 | default 0x80400 |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 110 | help |
| 111 | The amount of anticipated stack usage in CAR by bootblock and |
| 112 | other stages. In the case of FSP_USES_CB_STACK default value will be |
Subrata Banik | 191bd82 | 2020-11-21 19:30:57 +0530 | [diff] [blame] | 113 | sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 114 | (~1KiB). |
| 115 | |
| 116 | config FSP_TEMP_RAM_SIZE |
| 117 | hex |
| 118 | default 0x20000 |
| 119 | help |
| 120 | The amount of anticipated heap usage in CAR by FSP. |
| 121 | Refer to Platform FSP integration guide document to know |
| 122 | the exact FSP requirement for Heap setup. |
| 123 | |
Tim Wawrzynczak | 092813a | 2020-11-24 13:48:56 -0700 | [diff] [blame] | 124 | config CHIPSET_DEVICETREE |
| 125 | string |
| 126 | default "soc/intel/alderlake/chipset.cb" |
| 127 | |
Subrata Banik | 683c95e | 2020-12-19 19:36:45 +0530 | [diff] [blame] | 128 | config EXT_BIOS_WIN_BASE |
| 129 | default 0xf8000000 |
| 130 | |
| 131 | config EXT_BIOS_WIN_SIZE |
| 132 | default 0x2000000 |
| 133 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 134 | config IFD_CHIPSET |
| 135 | string |
| 136 | default "adl" |
| 137 | |
| 138 | config IED_REGION_SIZE |
| 139 | hex |
| 140 | default 0x400000 |
| 141 | |
| 142 | config HEAP_SIZE |
| 143 | hex |
| 144 | default 0x10000 |
| 145 | |
Tim Wawrzynczak | 8d11cdc | 2021-03-12 12:46:02 -0700 | [diff] [blame] | 146 | # Intel recommends reserving the following resources per PCIe TBT root port, |
| 147 | # from ADL BIOS Spec (doc #627270) Revision 0.6.0 Section 7.2.5.1.5 |
| 148 | # - 42 buses |
| 149 | # - 194 MiB Non-prefetchable memory |
| 150 | # - 448 MiB Prefetchable memory |
Furquan Shaikh | d9f5d90 | 2021-08-24 13:53:43 -0700 | [diff] [blame] | 151 | if SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES |
Tim Wawrzynczak | 8d11cdc | 2021-03-12 12:46:02 -0700 | [diff] [blame] | 152 | |
| 153 | config PCIEXP_HOTPLUG_BUSES |
| 154 | int |
| 155 | default 42 |
| 156 | |
| 157 | config PCIEXP_HOTPLUG_MEM |
| 158 | hex |
| 159 | default 0xc200000 |
| 160 | |
| 161 | config PCIEXP_HOTPLUG_PREFETCH_MEM |
| 162 | hex |
| 163 | default 0x1c000000 |
| 164 | |
Furquan Shaikh | d9f5d90 | 2021-08-24 13:53:43 -0700 | [diff] [blame] | 165 | endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES |
Tim Wawrzynczak | 8d11cdc | 2021-03-12 12:46:02 -0700 | [diff] [blame] | 166 | |
Subrata Banik | 85144d9 | 2021-01-09 16:17:45 +0530 | [diff] [blame] | 167 | config MAX_PCH_ROOT_PORTS |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 168 | int |
Varshit Pandya | b5df56f | 2021-01-18 09:44:35 +0530 | [diff] [blame] | 169 | default 10 if SOC_INTEL_ALDERLAKE_PCH_M |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 170 | default 12 |
| 171 | |
Subrata Banik | 85144d9 | 2021-01-09 16:17:45 +0530 | [diff] [blame] | 172 | config MAX_CPU_ROOT_PORTS |
| 173 | int |
Varshit Pandya | b5df56f | 2021-01-18 09:44:35 +0530 | [diff] [blame] | 174 | default 1 if SOC_INTEL_ALDERLAKE_PCH_M |
Subrata Banik | 85144d9 | 2021-01-09 16:17:45 +0530 | [diff] [blame] | 175 | default 3 |
| 176 | |
| 177 | config MAX_ROOT_PORTS |
| 178 | int |
| 179 | default MAX_PCH_ROOT_PORTS |
| 180 | |
Subrata Banik | cffc938 | 2021-01-29 18:41:35 +0530 | [diff] [blame] | 181 | config MAX_PCIE_CLOCK_SRC |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 182 | int |
Subrata Banik | cffc938 | 2021-01-29 18:41:35 +0530 | [diff] [blame] | 183 | default 6 if SOC_INTEL_ALDERLAKE_PCH_M |
| 184 | default 7 |
| 185 | |
| 186 | config MAX_PCIE_CLOCK_REQ |
| 187 | int |
| 188 | default 6 if SOC_INTEL_ALDERLAKE_PCH_M |
| 189 | default 10 |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 190 | |
| 191 | config SMM_TSEG_SIZE |
| 192 | hex |
| 193 | default 0x800000 |
| 194 | |
| 195 | config SMM_RESERVED_SIZE |
| 196 | hex |
| 197 | default 0x200000 |
| 198 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 199 | config PCR_BASE_ADDRESS |
| 200 | hex |
| 201 | default 0xfd000000 |
| 202 | help |
| 203 | This option allows you to select MMIO Base Address of sideband bus. |
| 204 | |
| 205 | config MMCONF_BASE_ADDRESS |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 206 | default 0xc0000000 |
| 207 | |
| 208 | config CPU_BCLK_MHZ |
| 209 | int |
| 210 | default 100 |
| 211 | |
| 212 | config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
| 213 | int |
| 214 | default 120 |
| 215 | |
Michael Niewöhner | dadcbfb | 2020-10-04 14:48:05 +0200 | [diff] [blame] | 216 | config CPU_XTAL_HZ |
| 217 | default 38400000 |
| 218 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 219 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 220 | int |
| 221 | default 133 |
| 222 | |
| 223 | config SOC_INTEL_COMMON_BLOCK_GSPI_MAX |
| 224 | int |
| 225 | default 7 |
| 226 | |
| 227 | config SOC_INTEL_I2C_DEV_MAX |
| 228 | int |
Varshit B Pandya | 339f0e7 | 2021-07-14 11:08:23 +0530 | [diff] [blame] | 229 | default 8 |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 230 | |
| 231 | config SOC_INTEL_UART_DEV_MAX |
| 232 | int |
| 233 | default 7 |
| 234 | |
| 235 | config CONSOLE_UART_BASE_ADDRESS |
| 236 | hex |
Bora Guvendik | 2a70419 | 2020-11-16 11:23:48 -0800 | [diff] [blame] | 237 | default 0xfe03e000 |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 238 | depends on INTEL_LPSS_UART_FOR_CONSOLE |
| 239 | |
Maulik V Vaghela | 996bab4 | 2021-02-05 12:03:19 +0530 | [diff] [blame] | 240 | config VBT_DATA_SIZE_KB |
| 241 | int |
| 242 | default 9 |
| 243 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 244 | # Clock divider parameters for 115200 baud rate |
| 245 | # Baudrate = (UART source clcok * M) /(N *16) |
| 246 | # ADL UART source clock: 120MHz |
| 247 | config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL |
| 248 | hex |
| 249 | default 0x25a |
| 250 | |
| 251 | config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL |
| 252 | hex |
| 253 | default 0x7fff |
| 254 | |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 255 | config VBOOT |
| 256 | select VBOOT_SEPARATE_VERSTAGE |
| 257 | select VBOOT_MUST_REQUEST_DISPLAY |
| 258 | select VBOOT_STARTS_IN_BOOTBLOCK |
| 259 | select VBOOT_VBNV_CMOS |
| 260 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
Subrata Banik | 3423786 | 2021-06-17 23:36:02 +0530 | [diff] [blame] | 261 | select VBOOT_X86_SHA256_ACCELERATION |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 262 | |
MAULIK V VAGHELA | 84532da | 2021-08-25 16:41:23 +0530 | [diff] [blame] | 263 | # Default hash block size is 1KiB. Increasing it to 4KiB to improve |
| 264 | # hashing time as well as read time. This helps in improving |
| 265 | # boot time for Alder Lake. |
| 266 | config VBOOT_HASH_BLOCK_SIZE |
| 267 | hex |
| 268 | default 0x1000 |
| 269 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 270 | config CBFS_SIZE |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 271 | default 0x200000 |
| 272 | |
| 273 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 274 | hex |
Subrata Banik | bf75055 | 2021-07-10 20:30:57 +0530 | [diff] [blame] | 275 | default 0x2000 |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 276 | |
Subrata Banik | ee73594 | 2020-09-07 17:52:23 +0530 | [diff] [blame] | 277 | config FSP_HEADER_PATH |
| 278 | string "Location of FSP headers" |
| 279 | default "src/vendorcode/intel/fsp/fsp2_0/alderlake/" |
| 280 | |
| 281 | config FSP_FD_PATH |
| 282 | string |
| 283 | depends on FSP_USE_REPO |
| 284 | default "3rdparty/fsp/AlderLakeFspBinPkg/Fsp.fd" |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 285 | |
| 286 | config SOC_INTEL_ALDERLAKE_DEBUG_CONSENT |
| 287 | int "Debug Consent for ADL" |
| 288 | # USB DBC is more common for developers so make this default to 3 if |
| 289 | # SOC_INTEL_DEBUG_CONSENT=y |
| 290 | default 3 if SOC_INTEL_DEBUG_CONSENT |
| 291 | default 0 |
| 292 | help |
| 293 | This is to control debug interface on SOC. |
| 294 | Setting non-zero value will allow to use DBC or DCI to debug SOC. |
| 295 | PlatformDebugConsent in FspmUpd.h has the details. |
| 296 | |
| 297 | Desired platform debug type are |
| 298 | 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), |
| 299 | 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), |
| 300 | 6:Enable (2-wire DCI OOB), 7:Manual |
Furquan Shaikh | a1c247b | 2020-12-31 22:50:14 -0800 | [diff] [blame] | 301 | |
| 302 | config DATA_BUS_WIDTH |
| 303 | int |
| 304 | default 128 |
| 305 | |
| 306 | config DIMMS_PER_CHANNEL |
| 307 | int |
| 308 | default 2 |
| 309 | |
| 310 | config MRC_CHANNEL_WIDTH |
| 311 | int |
| 312 | default 16 |
| 313 | |
Francois Toguo | cea4f92 | 2021-04-16 21:20:39 -0700 | [diff] [blame] | 314 | config SOC_INTEL_CRASHLOG |
| 315 | def_bool n |
| 316 | select SOC_INTEL_COMMON_BLOCK_CRASHLOG |
| 317 | select ACPI_BERT |
| 318 | help |
| 319 | Enables CrashLog. |
| 320 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 321 | endif |